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Sujith394cf0a2009-02-09 13:26:54 +05301/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Sujith394cf0a2009-02-09 13:26:54 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef DEBUG_H
18#define DEBUG_H
19
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -070020#include "hw.h"
Felix Fietkau545750d2009-11-23 22:21:01 +010021#include "rc.h"
Zefir Kurtisi29942bc2011-12-14 20:16:34 -080022#include "dfs_debug.h"
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -070023
Sujithfec247c2009-07-27 12:08:16 +053024struct ath_txq;
25struct ath_buf;
26
Felix Fietkaua830df02009-11-23 22:33:27 +010027#ifdef CONFIG_ATH9K_DEBUGFS
Sujithfec247c2009-07-27 12:08:16 +053028#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
Felix Fietkau030d6292011-10-07 02:28:13 +020029#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
Sujithfec247c2009-07-27 12:08:16 +053030#else
31#define TX_STAT_INC(q, c) do { } while (0)
Felix Fietkau030d6292011-10-07 02:28:13 +020032#define RESET_STAT_INC(sc, type) do { } while (0)
Sujithfec247c2009-07-27 12:08:16 +053033#endif
34
Felix Fietkaua830df02009-11-23 22:33:27 +010035#ifdef CONFIG_ATH9K_DEBUGFS
Sujith394cf0a2009-02-09 13:26:54 +053036
37/**
38 * struct ath_interrupt_stats - Contains statistics about interrupts
39 * @total: Total no. of interrupts generated so far
40 * @rxok: RX with no errors
Luis R. Rodrigueza9616f42010-04-15 17:39:30 -040041 * @rxlp: RX with low priority RX
42 * @rxhp: RX with high priority, uapsd only
Sujith394cf0a2009-02-09 13:26:54 +053043 * @rxeol: RX with no more RXDESC available
44 * @rxorn: RX FIFO overrun
45 * @txok: TX completed at the requested rate
46 * @txurn: TX FIFO underrun
47 * @mib: MIB regs reaching its threshold
48 * @rxphyerr: RX with phy errors
49 * @rx_keycache_miss: RX with key cache misses
50 * @swba: Software Beacon Alert
51 * @bmiss: Beacon Miss
52 * @bnr: Beacon Not Ready
53 * @cst: Carrier Sense TImeout
54 * @gtt: Global TX Timeout
55 * @tim: RX beacon TIM occurrence
56 * @cabend: RX End of CAB traffic
57 * @dtimsync: DTIM sync lossage
58 * @dtim: RX Beacon with DTIM
Luis R. Rodriguez08578b82010-05-13 13:33:44 -040059 * @bb_watchdog: Baseband watchdog
Mohammed Shafi Shajakhan6dde1aa2011-04-22 17:27:01 +053060 * @tsfoor: TSF out of range, indicates that the corrected TSF received
61 * from a beacon differs from the PCU's internal TSF by more than a
62 * (programmable) threshold
Ben Greear462e58f2012-04-12 10:04:00 -070063 * @local_timeout: Internal bus timeout.
Sujith394cf0a2009-02-09 13:26:54 +053064 */
65struct ath_interrupt_stats {
66 u32 total;
67 u32 rxok;
Luis R. Rodrigueza9616f42010-04-15 17:39:30 -040068 u32 rxlp;
69 u32 rxhp;
Sujith394cf0a2009-02-09 13:26:54 +053070 u32 rxeol;
71 u32 rxorn;
72 u32 txok;
73 u32 txeol;
74 u32 txurn;
75 u32 mib;
76 u32 rxphyerr;
77 u32 rx_keycache_miss;
78 u32 swba;
79 u32 bmiss;
80 u32 bnr;
81 u32 cst;
82 u32 gtt;
83 u32 tim;
84 u32 cabend;
85 u32 dtimsync;
86 u32 dtim;
Luis R. Rodriguez08578b82010-05-13 13:33:44 -040087 u32 bb_watchdog;
Mohammed Shafi Shajakhan6dde1aa2011-04-22 17:27:01 +053088 u32 tsfoor;
Ben Greear462e58f2012-04-12 10:04:00 -070089
90 /* Sync-cause stats */
91 u32 sync_cause_all;
92 u32 sync_rtc_irq;
93 u32 sync_mac_irq;
94 u32 eeprom_illegal_access;
95 u32 apb_timeout;
96 u32 pci_mode_conflict;
97 u32 host1_fatal;
98 u32 host1_perr;
99 u32 trcv_fifo_perr;
100 u32 radm_cpl_ep;
101 u32 radm_cpl_dllp_abort;
102 u32 radm_cpl_tlp_abort;
103 u32 radm_cpl_ecrc_err;
104 u32 radm_cpl_timeout;
105 u32 local_timeout;
106 u32 pm_access;
107 u32 mac_awake;
108 u32 mac_asleep;
109 u32 mac_sleep_access;
Sujith394cf0a2009-02-09 13:26:54 +0530110};
111
Ben Greear462e58f2012-04-12 10:04:00 -0700112
Sujithfec247c2009-07-27 12:08:16 +0530113/**
114 * struct ath_tx_stats - Statistics about TX
Ben Greear99c15bf2010-10-01 12:26:30 -0700115 * @tx_pkts_all: No. of total frames transmitted, including ones that
116 may have had errors.
117 * @tx_bytes_all: No. of total bytes transmitted, including ones that
118 may have had errors.
Sujithfec247c2009-07-27 12:08:16 +0530119 * @queued: Total MPDUs (non-aggr) queued
120 * @completed: Total MPDUs (non-aggr) completed
121 * @a_aggr: Total no. of aggregates queued
Ben Greearbda8add2011-01-09 23:11:48 -0800122 * @a_queued_hw: Total AMPDUs queued to hardware
123 * @a_queued_sw: Total AMPDUs queued to software queues
Sujithfec247c2009-07-27 12:08:16 +0530124 * @a_completed: Total AMPDUs completed
125 * @a_retries: No. of AMPDUs retried (SW)
126 * @a_xretries: No. of AMPDUs dropped due to xretries
127 * @fifo_underrun: FIFO underrun occurrences
128 Valid only for:
129 - non-aggregate condition.
130 - first packet of aggregate.
131 * @xtxop: No. of frames filtered because of TXOP limit
132 * @timer_exp: Transmit timer expiry
133 * @desc_cfg_err: Descriptor configuration errors
134 * @data_urn: TX data underrun errors
135 * @delim_urn: TX delimiter underrun errors
Ben Greear2dac4fb2011-01-09 23:11:45 -0800136 * @puttxbuf: Number of times hardware was given txbuf to write.
137 * @txstart: Number of times hardware was told to start tx.
138 * @txprocdesc: Number of times tx descriptor was processed
Ben Greeara5a0bca2012-04-03 09:16:55 -0700139 * @txfailed: Out-of-memory or other errors in xmit path.
Sujithfec247c2009-07-27 12:08:16 +0530140 */
141struct ath_tx_stats {
Ben Greear99c15bf2010-10-01 12:26:30 -0700142 u32 tx_pkts_all;
143 u32 tx_bytes_all;
Sujithfec247c2009-07-27 12:08:16 +0530144 u32 queued;
145 u32 completed;
Felix Fietkau5a6f78a2011-05-31 21:21:41 +0200146 u32 xretries;
Sujithfec247c2009-07-27 12:08:16 +0530147 u32 a_aggr;
Ben Greearbda8add2011-01-09 23:11:48 -0800148 u32 a_queued_hw;
149 u32 a_queued_sw;
Sujithfec247c2009-07-27 12:08:16 +0530150 u32 a_completed;
151 u32 a_retries;
152 u32 a_xretries;
153 u32 fifo_underrun;
154 u32 xtxop;
155 u32 timer_exp;
156 u32 desc_cfg_err;
157 u32 data_underrun;
158 u32 delim_underrun;
Ben Greear2dac4fb2011-01-09 23:11:45 -0800159 u32 puttxbuf;
160 u32 txstart;
161 u32 txprocdesc;
Ben Greeara5a0bca2012-04-03 09:16:55 -0700162 u32 txfailed;
Sujithfec247c2009-07-27 12:08:16 +0530163};
164
Ben Greear15072182012-04-03 09:18:59 -0700165#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
166
Sujith1395d3f2010-01-08 10:36:11 +0530167/**
168 * struct ath_rx_stats - RX Statistics
Ben Greear99c15bf2010-10-01 12:26:30 -0700169 * @rx_pkts_all: No. of total frames received, including ones that
170 may have had errors.
171 * @rx_bytes_all: No. of total bytes received, including ones that
172 may have had errors.
Sujith1395d3f2010-01-08 10:36:11 +0530173 * @crc_err: No. of frames with incorrect CRC value
174 * @decrypt_crc_err: No. of frames whose CRC check failed after
175 decryption process completed
176 * @phy_err: No. of frames whose reception failed because the PHY
177 encountered an error
178 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
179 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
180 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
181 * @decrypt_busy_err: Decryption interruptions counter
182 * @phy_err_stats: Individual PHY error statistics
Ben Greear15072182012-04-03 09:18:59 -0700183 * @rx_len_err: No. of frames discarded due to bad length.
184 * @rx_oom_err: No. of frames dropped due to OOM issues.
185 * @rx_rate_err: No. of frames dropped due to rate errors.
186 * @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
187 * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
188 * @rx_beacons: No. of beacons received.
189 * @rx_frags: No. of rx-fragements received.
Sujith1395d3f2010-01-08 10:36:11 +0530190 */
191struct ath_rx_stats {
Ben Greear99c15bf2010-10-01 12:26:30 -0700192 u32 rx_pkts_all;
193 u32 rx_bytes_all;
Sujith1395d3f2010-01-08 10:36:11 +0530194 u32 crc_err;
195 u32 decrypt_crc_err;
196 u32 phy_err;
197 u32 mic_err;
198 u32 pre_delim_crc_err;
199 u32 post_delim_crc_err;
200 u32 decrypt_busy_err;
201 u32 phy_err_stats[ATH9K_PHYERR_MAX];
Ben Greear15072182012-04-03 09:18:59 -0700202 u32 rx_len_err;
203 u32 rx_oom_err;
204 u32 rx_rate_err;
205 u32 rx_too_many_frags_err;
206 u32 rx_drop_rxflush;
207 u32 rx_beacons;
208 u32 rx_frags;
Sujith1395d3f2010-01-08 10:36:11 +0530209};
210
Felix Fietkau030d6292011-10-07 02:28:13 +0200211enum ath_reset_type {
212 RESET_TYPE_BB_HANG,
213 RESET_TYPE_BB_WATCHDOG,
214 RESET_TYPE_FATAL_INT,
215 RESET_TYPE_TX_ERROR,
216 RESET_TYPE_TX_HANG,
217 RESET_TYPE_PLL_HANG,
Rajkumar Manoharan01e18912012-03-15 05:34:27 +0530218 RESET_TYPE_MAC_HANG,
Felix Fietkau030d6292011-10-07 02:28:13 +0200219 __RESET_TYPE_MAX
220};
221
Sujith394cf0a2009-02-09 13:26:54 +0530222struct ath_stats {
223 struct ath_interrupt_stats istats;
Sujithfec247c2009-07-27 12:08:16 +0530224 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
Sujith1395d3f2010-01-08 10:36:11 +0530225 struct ath_rx_stats rxstats;
Zefir Kurtisi29942bc2011-12-14 20:16:34 -0800226 struct ath_dfs_stats dfs_stats;
Felix Fietkau030d6292011-10-07 02:28:13 +0200227 u32 reset[__RESET_TYPE_MAX];
Sujith394cf0a2009-02-09 13:26:54 +0530228};
229
Rajkumar Manoharancf3af742011-08-27 16:17:47 +0530230#define ATH_DBG_MAX_SAMPLES 10
231struct ath_dbg_bb_mac_samp {
232 u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
233 u32 pcu_obs, pcu_cr, noise;
234 struct {
235 u64 jiffies;
236 int8_t rssi_ctl0;
237 int8_t rssi_ctl1;
238 int8_t rssi_ctl2;
239 int8_t rssi_ext0;
240 int8_t rssi_ext1;
241 int8_t rssi_ext2;
242 int8_t rssi;
243 bool isok;
244 u8 rts_fail_cnt;
245 u8 data_fail_cnt;
246 u8 rateindex;
247 u8 qid;
248 u8 tid;
Mohammed Shafi Shajakhan129321802011-09-21 14:22:49 +0530249 u32 ba_low;
250 u32 ba_high;
Rajkumar Manoharancf3af742011-08-27 16:17:47 +0530251 } ts[ATH_DBG_MAX_SAMPLES];
252 struct {
253 u64 jiffies;
254 int8_t rssi_ctl0;
255 int8_t rssi_ctl1;
256 int8_t rssi_ctl2;
257 int8_t rssi_ext0;
258 int8_t rssi_ext1;
259 int8_t rssi_ext2;
260 int8_t rssi;
261 bool is_mybeacon;
262 u8 antenna;
263 u8 rate;
264 } rs[ATH_DBG_MAX_SAMPLES];
265 struct ath_cycle_counters cc;
266 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
267};
268
Sujith394cf0a2009-02-09 13:26:54 +0530269struct ath9k_debug {
Sujith394cf0a2009-02-09 13:26:54 +0530270 struct dentry *debugfs_phy;
Felix Fietkau9bff0bc2010-05-11 17:23:02 +0200271 u32 regidx;
Sujith394cf0a2009-02-09 13:26:54 +0530272 struct ath_stats stats;
Felix Fietkau5baec742012-03-03 15:17:03 +0100273#ifdef CONFIG_ATH9K_MAC_DEBUG
Rajkumar Manoharancf3af742011-08-27 16:17:47 +0530274 spinlock_t samp_lock;
275 struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
276 u8 sampidx;
277 u8 tsidx;
278 u8 rsidx;
Felix Fietkau5baec742012-03-03 15:17:03 +0100279#endif
Sujith394cf0a2009-02-09 13:26:54 +0530280};
281
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -0700282int ath9k_init_debug(struct ath_hw *ah);
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -0700283
Sujith394cf0a2009-02-09 13:26:54 +0530284void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
Felix Fietkau066dae92010-11-07 14:59:39 +0100285void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
Felix Fietkau55797b12011-09-14 21:24:16 +0200286 struct ath_tx_status *ts, struct ath_txq *txq,
287 unsigned int flags);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700288void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
Sujith394cf0a2009-02-09 13:26:54 +0530289
290#else
291
Ben Greear15072182012-04-03 09:18:59 -0700292#define RX_STAT_INC(c) /* NOP */
293
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -0700294static inline int ath9k_init_debug(struct ath_hw *ah)
Sujith394cf0a2009-02-09 13:26:54 +0530295{
296 return 0;
297}
298
Sujith394cf0a2009-02-09 13:26:54 +0530299static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
300 enum ath9k_int status)
301{
302}
303
Sujithfec247c2009-07-27 12:08:16 +0530304static inline void ath_debug_stat_tx(struct ath_softc *sc,
Felix Fietkau32ffb1f2010-03-31 15:41:36 -0700305 struct ath_buf *bf,
Felix Fietkau3bf63e52011-01-28 17:52:49 +0100306 struct ath_tx_status *ts,
Felix Fietkau55797b12011-09-14 21:24:16 +0200307 struct ath_txq *txq,
308 unsigned int flags)
Sujithfec247c2009-07-27 12:08:16 +0530309{
310}
311
Sujith1395d3f2010-01-08 10:36:11 +0530312static inline void ath_debug_stat_rx(struct ath_softc *sc,
Felix Fietkau32ffb1f2010-03-31 15:41:36 -0700313 struct ath_rx_status *rs)
Sujith1395d3f2010-01-08 10:36:11 +0530314{
315}
316
Felix Fietkaua830df02009-11-23 22:33:27 +0100317#endif /* CONFIG_ATH9K_DEBUGFS */
Sujith394cf0a2009-02-09 13:26:54 +0530318
Felix Fietkau5baec742012-03-03 15:17:03 +0100319#ifdef CONFIG_ATH9K_MAC_DEBUG
320
321void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
322
323#else
324
325static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
326{
327}
328
329#endif
330
331
Sujith394cf0a2009-02-09 13:26:54 +0530332#endif /* DEBUG_H */