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Rob Clarka3376e32013-08-30 13:02:15 -04001/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "hdmi.h"
19
20struct hdmi_bridge {
21 struct drm_bridge base;
Rob Clarka3376e32013-08-30 13:02:15 -040022 struct hdmi *hdmi;
Rob Clarka3376e32013-08-30 13:02:15 -040023};
24#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
25
Ajay Kumar3d3f8b12015-01-20 22:08:44 +053026void hdmi_bridge_destroy(struct drm_bridge *bridge)
Rob Clarka3376e32013-08-30 13:02:15 -040027{
Rob Clarka3376e32013-08-30 13:02:15 -040028}
29
Rob Clarkdada25b2013-12-01 12:12:54 -050030static void power_on(struct drm_bridge *bridge)
31{
32 struct drm_device *dev = bridge->dev;
33 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
34 struct hdmi *hdmi = hdmi_bridge->hdmi;
35 const struct hdmi_platform_config *config = hdmi->config;
36 int i, ret;
37
38 for (i = 0; i < config->pwr_reg_cnt; i++) {
39 ret = regulator_enable(hdmi->pwr_regs[i]);
40 if (ret) {
41 dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
42 config->pwr_reg_names[i], ret);
43 }
44 }
45
46 if (config->pwr_clk_cnt > 0) {
Rob Clarkc0c0d9e2013-12-11 14:44:02 -050047 DBG("pixclock: %lu", hdmi->pixclock);
48 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
Rob Clarkdada25b2013-12-01 12:12:54 -050049 if (ret) {
50 dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
51 config->pwr_clk_names[0], ret);
52 }
53 }
54
55 for (i = 0; i < config->pwr_clk_cnt; i++) {
56 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
57 if (ret) {
58 dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
59 config->pwr_clk_names[i], ret);
60 }
61 }
62}
63
64static void power_off(struct drm_bridge *bridge)
65{
66 struct drm_device *dev = bridge->dev;
67 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
68 struct hdmi *hdmi = hdmi_bridge->hdmi;
69 const struct hdmi_platform_config *config = hdmi->config;
70 int i, ret;
71
72 /* TODO do we need to wait for final vblank somewhere before
73 * cutting the clocks?
74 */
75 mdelay(16 + 4);
76
77 for (i = 0; i < config->pwr_clk_cnt; i++)
78 clk_disable_unprepare(hdmi->pwr_clks[i]);
79
80 for (i = 0; i < config->pwr_reg_cnt; i++) {
81 ret = regulator_disable(hdmi->pwr_regs[i]);
82 if (ret) {
83 dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
84 config->pwr_reg_names[i], ret);
85 }
86 }
87}
88
Rob Clarka3376e32013-08-30 13:02:15 -040089static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
90{
91 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
92 struct hdmi *hdmi = hdmi_bridge->hdmi;
93 struct hdmi_phy *phy = hdmi->phy;
94
95 DBG("power up");
Rob Clarkdada25b2013-12-01 12:12:54 -050096
Rob Clarkc0c0d9e2013-12-11 14:44:02 -050097 if (!hdmi->power_on) {
Rob Clarkdada25b2013-12-01 12:12:54 -050098 power_on(bridge);
Rob Clarkc0c0d9e2013-12-11 14:44:02 -050099 hdmi->power_on = true;
100 hdmi_audio_update(hdmi);
Rob Clarkdada25b2013-12-01 12:12:54 -0500101 }
102
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500103 phy->funcs->powerup(phy, hdmi->pixclock);
Rob Clarka3376e32013-08-30 13:02:15 -0400104 hdmi_set_mode(hdmi, true);
105}
106
107static void hdmi_bridge_enable(struct drm_bridge *bridge)
108{
109}
110
111static void hdmi_bridge_disable(struct drm_bridge *bridge)
112{
113}
114
115static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
116{
117 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
118 struct hdmi *hdmi = hdmi_bridge->hdmi;
119 struct hdmi_phy *phy = hdmi->phy;
120
121 DBG("power down");
122 hdmi_set_mode(hdmi, false);
123 phy->funcs->powerdown(phy);
Rob Clarkdada25b2013-12-01 12:12:54 -0500124
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500125 if (hdmi->power_on) {
Rob Clarkdada25b2013-12-01 12:12:54 -0500126 power_off(bridge);
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500127 hdmi->power_on = false;
128 hdmi_audio_update(hdmi);
Rob Clarkdada25b2013-12-01 12:12:54 -0500129 }
Rob Clarka3376e32013-08-30 13:02:15 -0400130}
131
132static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
133 struct drm_display_mode *mode,
134 struct drm_display_mode *adjusted_mode)
135{
136 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
137 struct hdmi *hdmi = hdmi_bridge->hdmi;
138 int hstart, hend, vstart, vend;
139 uint32_t frame_ctrl;
140
141 mode = adjusted_mode;
142
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500143 hdmi->pixclock = mode->clock * 1000;
Rob Clarka3376e32013-08-30 13:02:15 -0400144
145 hdmi->hdmi_mode = drm_match_cea_mode(mode) > 1;
146
147 hstart = mode->htotal - mode->hsync_start;
148 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
149
150 vstart = mode->vtotal - mode->vsync_start - 1;
151 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
152
153 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
154 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
155
156 hdmi_write(hdmi, REG_HDMI_TOTAL,
157 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
158 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
159
160 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
161 HDMI_ACTIVE_HSYNC_START(hstart) |
162 HDMI_ACTIVE_HSYNC_END(hend));
163 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
164 HDMI_ACTIVE_VSYNC_START(vstart) |
165 HDMI_ACTIVE_VSYNC_END(vend));
166
167 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
168 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
169 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
170 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
171 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
172 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
173 } else {
174 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
175 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
176 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
177 HDMI_VSYNC_ACTIVE_F2_START(0) |
178 HDMI_VSYNC_ACTIVE_F2_END(0));
179 }
180
181 frame_ctrl = 0;
182 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
183 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
184 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
185 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
186 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
187 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
188 DBG("frame_ctrl=%08x", frame_ctrl);
189 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
190
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500191 hdmi_audio_update(hdmi);
Rob Clarka3376e32013-08-30 13:02:15 -0400192}
193
194static const struct drm_bridge_funcs hdmi_bridge_funcs = {
195 .pre_enable = hdmi_bridge_pre_enable,
196 .enable = hdmi_bridge_enable,
197 .disable = hdmi_bridge_disable,
198 .post_disable = hdmi_bridge_post_disable,
199 .mode_set = hdmi_bridge_mode_set,
Rob Clarka3376e32013-08-30 13:02:15 -0400200};
201
202
203/* initialize bridge */
204struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
205{
206 struct drm_bridge *bridge = NULL;
207 struct hdmi_bridge *hdmi_bridge;
208 int ret;
209
Rob Clark475ac0a2015-01-31 11:45:09 -0500210 hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
211 sizeof(*hdmi_bridge), GFP_KERNEL);
Rob Clarka3376e32013-08-30 13:02:15 -0400212 if (!hdmi_bridge) {
213 ret = -ENOMEM;
214 goto fail;
215 }
216
Rob Clarkd1a717b2014-11-18 08:40:44 -0500217 hdmi_bridge->hdmi = hdmi;
Rob Clarka3376e32013-08-30 13:02:15 -0400218
219 bridge = &hdmi_bridge->base;
Ajay Kumarb07b90f2015-01-20 22:08:43 +0530220 bridge->funcs = &hdmi_bridge_funcs;
Rob Clarka3376e32013-08-30 13:02:15 -0400221
Rob Clark475ac0a2015-01-31 11:45:09 -0500222 ret = drm_bridge_attach(hdmi->dev, bridge);
223 if (ret)
224 goto fail;
Rob Clarka3376e32013-08-30 13:02:15 -0400225
226 return bridge;
227
228fail:
229 if (bridge)
230 hdmi_bridge_destroy(bridge);
231
232 return ERR_PTR(ret);
233}