blob: 2896aafc952028f11a80dd022556e355ccd4916a [file] [log] [blame]
Zhi Wang82d375d2016-07-05 12:40:49 -04001/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
26 *
27 * Contributors:
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 *
32 */
33
34#include "i915_drv.h"
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +080035#include "gvt.h"
36#include "i915_pvinfo.h"
Zhi Wang82d375d2016-07-05 12:40:49 -040037
Ping Gao23736d12016-10-26 09:38:52 +080038void populate_pvinfo_page(struct intel_vgpu *vgpu)
Zhi Wang82d375d2016-07-05 12:40:49 -040039{
40 /* setup the ballooning information */
41 vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
42 vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
43 vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
44 vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
45 vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
Weinan Lia2ae95a2017-10-20 15:16:46 +080046
Tina Zhang6b3816d2017-08-14 15:24:14 +080047 vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
Weinan Lia2ae95a2017-10-20 15:16:46 +080048 vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
49
Zhi Wang82d375d2016-07-05 12:40:49 -040050 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
51 vgpu_aperture_gmadr_base(vgpu);
52 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
53 vgpu_aperture_sz(vgpu);
54 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
55 vgpu_hidden_gmadr_base(vgpu);
56 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
57 vgpu_hidden_sz(vgpu);
58
59 vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
60
61 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
62 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
63 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
64 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
65 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
66 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
67
68 WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
69}
70
Ping Gaobc90d092017-03-30 00:36:37 +080071#define VGPU_MAX_WEIGHT 16
72#define VGPU_WEIGHT(vgpu_num) \
73 (VGPU_MAX_WEIGHT / (vgpu_num))
74
Zhenyu Wang191020b2017-02-23 14:46:23 +080075static struct {
76 unsigned int low_mm;
77 unsigned int high_mm;
78 unsigned int fence;
Ping Gaobc90d092017-03-30 00:36:37 +080079
80 /* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
81 * with a weight of 4 on a contended host, different vGPU type has
82 * different weight set. Legal weights range from 1 to 16.
83 */
84 unsigned int weight;
Zhenyu Wangd1a513b2017-02-24 10:58:21 +080085 enum intel_vgpu_edid edid;
Zhenyu Wang191020b2017-02-23 14:46:23 +080086 char *name;
87} vgpu_types[] = {
88/* Fixed vGPU type table */
Ping Gaobc90d092017-03-30 00:36:37 +080089 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
90 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
91 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
92 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
Zhenyu Wang191020b2017-02-23 14:46:23 +080093};
94
Zhi Wang82d375d2016-07-05 12:40:49 -040095/**
Zhenyu Wang1f31c822016-11-03 18:38:31 +080096 * intel_gvt_init_vgpu_types - initialize vGPU type list
97 * @gvt : GVT device
98 *
99 * Initialize vGPU type list based on available resource.
100 *
101 */
102int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
103{
104 unsigned int num_types;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800105 unsigned int i, low_avail, high_avail;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800106 unsigned int min_low;
107
108 /* vGPU type name is defined as GVTg_Vx_y which contains
Zhenyu Wang191020b2017-02-23 14:46:23 +0800109 * physical GPU generation type (e.g V4 as BDW server, V5 as
110 * SKL server).
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800111 *
112 * Depend on physical SKU resource, might see vGPU types like
113 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
114 * different types of vGPU on same physical GPU depending on
115 * available resource. Each vGPU type will have "avail_instance"
116 * to indicate how many vGPU instance can be created for this
117 * type.
118 *
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800119 */
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800120 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
121 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800122 num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800123
124 gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
125 GFP_KERNEL);
126 if (!gvt->types)
127 return -ENOMEM;
128
129 min_low = MB_TO_BYTES(32);
130 for (i = 0; i < num_types; ++i) {
Zhenyu Wang191020b2017-02-23 14:46:23 +0800131 if (low_avail / vgpu_types[i].low_mm == 0)
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800132 break;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800133
134 gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
135 gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
136 gvt->types[i].fence = vgpu_types[i].fence;
Ping Gaobc90d092017-03-30 00:36:37 +0800137
138 if (vgpu_types[i].weight < 1 ||
139 vgpu_types[i].weight > VGPU_MAX_WEIGHT)
140 return -EINVAL;
141
142 gvt->types[i].weight = vgpu_types[i].weight;
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800143 gvt->types[i].resolution = vgpu_types[i].edid;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800144 gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
145 high_avail / vgpu_types[i].high_mm);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800146
147 if (IS_GEN8(gvt->dev_priv))
Zhenyu Wang191020b2017-02-23 14:46:23 +0800148 sprintf(gvt->types[i].name, "GVTg_V4_%s",
149 vgpu_types[i].name);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800150 else if (IS_GEN9(gvt->dev_priv))
Zhenyu Wang191020b2017-02-23 14:46:23 +0800151 sprintf(gvt->types[i].name, "GVTg_V5_%s",
152 vgpu_types[i].name);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800153
Ping Gaobc90d092017-03-30 00:36:37 +0800154 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
Zhenyu Wang191020b2017-02-23 14:46:23 +0800155 i, gvt->types[i].name,
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800156 gvt->types[i].avail_instance,
157 gvt->types[i].low_gm_size,
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800158 gvt->types[i].high_gm_size, gvt->types[i].fence,
Ping Gaobc90d092017-03-30 00:36:37 +0800159 gvt->types[i].weight,
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800160 vgpu_edid_str(gvt->types[i].resolution));
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800161 }
162
163 gvt->num_types = i;
164 return 0;
165}
166
167void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
168{
169 kfree(gvt->types);
170}
171
172static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
173{
174 int i;
175 unsigned int low_gm_avail, high_gm_avail, fence_avail;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800176 unsigned int low_gm_min, high_gm_min, fence_min;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800177
178 /* Need to depend on maxium hw resource size but keep on
179 * static config for now.
180 */
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800181 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800182 gvt->gm.vgpu_allocated_low_gm_size;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800183 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800184 gvt->gm.vgpu_allocated_high_gm_size;
185 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
186 gvt->fence.vgpu_allocated_fence_num;
187
188 for (i = 0; i < gvt->num_types; i++) {
189 low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
190 high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
191 fence_min = fence_avail / gvt->types[i].fence;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800192 gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
193 fence_min);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800194
Zhenyu Wang191020b2017-02-23 14:46:23 +0800195 gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
196 i, gvt->types[i].name,
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800197 gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
198 gvt->types[i].high_gm_size, gvt->types[i].fence);
199 }
200}
201
202/**
Zhi Wangb79c52a2017-03-30 01:48:39 +0800203 * intel_gvt_active_vgpu - activate a virtual GPU
204 * @vgpu: virtual GPU
205 *
206 * This function is called when user wants to activate a virtual GPU.
207 *
208 */
209void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
210{
211 mutex_lock(&vgpu->gvt->lock);
212 vgpu->active = true;
213 mutex_unlock(&vgpu->gvt->lock);
214}
215
216/**
217 * intel_gvt_deactive_vgpu - deactivate a virtual GPU
218 * @vgpu: virtual GPU
219 *
220 * This function is called when user wants to deactivate a virtual GPU.
221 * All virtual GPU runtime information will be destroyed.
222 *
223 */
224void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
225{
226 struct intel_gvt *gvt = vgpu->gvt;
227
228 mutex_lock(&gvt->lock);
229
230 vgpu->active = false;
231
Zhi Wang1406a142017-09-10 21:15:18 +0800232 if (atomic_read(&vgpu->submission.running_workload_num)) {
Zhi Wangb79c52a2017-03-30 01:48:39 +0800233 mutex_unlock(&gvt->lock);
234 intel_gvt_wait_vgpu_idle(vgpu);
235 mutex_lock(&gvt->lock);
236 }
237
238 intel_vgpu_stop_schedule(vgpu);
239
240 mutex_unlock(&gvt->lock);
241}
242
243/**
Zhi Wang82d375d2016-07-05 12:40:49 -0400244 * intel_gvt_destroy_vgpu - destroy a virtual GPU
245 * @vgpu: virtual GPU
246 *
247 * This function is called when user wants to destroy a virtual GPU.
248 *
249 */
250void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
251{
252 struct intel_gvt *gvt = vgpu->gvt;
253
254 mutex_lock(&gvt->lock);
255
Zhi Wangb79c52a2017-03-30 01:48:39 +0800256 WARN(vgpu->active, "vGPU is still active!\n");
257
Changbin Dubc7b0be2017-09-26 16:19:13 +0800258 intel_gvt_debugfs_remove_vgpu(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400259 idr_remove(&gvt->vgpu_idr, vgpu->id);
Zhi Wang4b639602016-05-01 17:09:58 -0400260 intel_vgpu_clean_sched_policy(vgpu);
Zhi Wang874b6a92017-09-10 20:08:18 +0800261 intel_vgpu_clean_submission(vgpu);
Zhi Wang04d348a2016-04-25 18:28:56 -0400262 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400263 intel_vgpu_clean_opregion(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800264 intel_vgpu_clean_gtt(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400265 intel_gvt_hypervisor_detach_vgpu(vgpu);
266 intel_vgpu_free_resource(vgpu);
Changbin Ducdcc4342017-01-13 11:16:00 +0800267 intel_vgpu_clean_mmio(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400268 vfree(vgpu);
269
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800270 intel_gvt_update_vgpu_types(gvt);
Zhi Wang82d375d2016-07-05 12:40:49 -0400271 mutex_unlock(&gvt->lock);
272}
273
Ping Gaoafe04fb2017-03-30 00:36:39 +0800274#define IDLE_VGPU_IDR 0
275
276/**
277 * intel_gvt_create_idle_vgpu - create an idle virtual GPU
278 * @gvt: GVT device
279 *
280 * This function is called when user wants to create an idle virtual GPU.
281 *
282 * Returns:
283 * pointer to intel_vgpu, error pointer if failed.
284 */
285struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
286{
287 struct intel_vgpu *vgpu;
288 enum intel_engine_id i;
289 int ret;
290
291 vgpu = vzalloc(sizeof(*vgpu));
292 if (!vgpu)
293 return ERR_PTR(-ENOMEM);
294
295 vgpu->id = IDLE_VGPU_IDR;
296 vgpu->gvt = gvt;
297
298 for (i = 0; i < I915_NUM_ENGINES; i++)
Zhi Wang1406a142017-09-10 21:15:18 +0800299 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
Ping Gaoafe04fb2017-03-30 00:36:39 +0800300
301 ret = intel_vgpu_init_sched_policy(vgpu);
302 if (ret)
303 goto out_free_vgpu;
304
305 vgpu->active = false;
306
307 return vgpu;
308
309out_free_vgpu:
310 vfree(vgpu);
311 return ERR_PTR(ret);
312}
313
314/**
315 * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
316 * @vgpu: virtual GPU
317 *
318 * This function is called when user wants to destroy an idle virtual GPU.
319 *
320 */
321void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
322{
323 intel_vgpu_clean_sched_policy(vgpu);
324 vfree(vgpu);
325}
326
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800327static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
Zhi Wang82d375d2016-07-05 12:40:49 -0400328 struct intel_vgpu_creation_params *param)
329{
330 struct intel_vgpu *vgpu;
331 int ret;
332
333 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
334 param->handle, param->low_gm_sz, param->high_gm_sz,
335 param->fence_sz);
336
337 vgpu = vzalloc(sizeof(*vgpu));
338 if (!vgpu)
339 return ERR_PTR(-ENOMEM);
340
341 mutex_lock(&gvt->lock);
342
Ping Gaoafe04fb2017-03-30 00:36:39 +0800343 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
344 GFP_KERNEL);
Zhi Wang82d375d2016-07-05 12:40:49 -0400345 if (ret < 0)
346 goto out_free_vgpu;
347
348 vgpu->id = ret;
349 vgpu->handle = param->handle;
350 vgpu->gvt = gvt;
Ping Gaobc90d092017-03-30 00:36:37 +0800351 vgpu->sched_ctl.weight = param->weight;
Zhi Wang82d375d2016-07-05 12:40:49 -0400352
Changbin Du536fc232017-01-13 11:15:58 +0800353 intel_vgpu_init_cfg_space(vgpu, param->primary);
Zhi Wang82d375d2016-07-05 12:40:49 -0400354
Changbin Ducdcc4342017-01-13 11:16:00 +0800355 ret = intel_vgpu_init_mmio(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400356 if (ret)
Jike Song4e537892017-01-06 15:16:22 +0800357 goto out_clean_idr;
Zhi Wang82d375d2016-07-05 12:40:49 -0400358
359 ret = intel_vgpu_alloc_resource(vgpu, param);
360 if (ret)
361 goto out_clean_vgpu_mmio;
362
363 populate_pvinfo_page(vgpu);
364
365 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
366 if (ret)
367 goto out_clean_vgpu_resource;
368
Zhi Wang2707e442016-03-28 23:23:16 +0800369 ret = intel_vgpu_init_gtt(vgpu);
370 if (ret)
371 goto out_detach_hypervisor_vgpu;
372
Xiong Zhang4dff1102017-11-20 15:31:15 +0800373 ret = intel_vgpu_init_opregion(vgpu);
Zhi Wang04d348a2016-04-25 18:28:56 -0400374 if (ret)
Jike Song8f897432016-11-03 18:38:32 +0800375 goto out_clean_gtt;
Zhi Wang04d348a2016-04-25 18:28:56 -0400376
Xiong Zhang4dff1102017-11-20 15:31:15 +0800377 ret = intel_vgpu_init_display(vgpu, param->resolution);
378 if (ret)
379 goto out_clean_opregion;
380
Zhi Wangad1d3632017-09-13 00:31:29 +0800381 ret = intel_vgpu_setup_submission(vgpu);
Zhi Wang8453d672016-05-01 02:48:25 -0400382 if (ret)
383 goto out_clean_display;
384
Zhi Wang4b639602016-05-01 17:09:58 -0400385 ret = intel_vgpu_init_sched_policy(vgpu);
386 if (ret)
Zhi Wangad1d3632017-09-13 00:31:29 +0800387 goto out_clean_submission;
Zhi Wang4b639602016-05-01 17:09:58 -0400388
Changbin Dubc7b0be2017-09-26 16:19:13 +0800389 ret = intel_gvt_debugfs_add_vgpu(vgpu);
390 if (ret)
391 goto out_clean_sched_policy;
392
Zhi Wang82d375d2016-07-05 12:40:49 -0400393 mutex_unlock(&gvt->lock);
394
395 return vgpu;
396
Changbin Dubc7b0be2017-09-26 16:19:13 +0800397out_clean_sched_policy:
398 intel_vgpu_clean_sched_policy(vgpu);
Zhi Wangad1d3632017-09-13 00:31:29 +0800399out_clean_submission:
Zhi Wang874b6a92017-09-10 20:08:18 +0800400 intel_vgpu_clean_submission(vgpu);
Zhi Wang8453d672016-05-01 02:48:25 -0400401out_clean_display:
402 intel_vgpu_clean_display(vgpu);
Xiong Zhang4dff1102017-11-20 15:31:15 +0800403out_clean_opregion:
404 intel_vgpu_clean_opregion(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400405out_clean_gtt:
406 intel_vgpu_clean_gtt(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800407out_detach_hypervisor_vgpu:
408 intel_gvt_hypervisor_detach_vgpu(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400409out_clean_vgpu_resource:
410 intel_vgpu_free_resource(vgpu);
411out_clean_vgpu_mmio:
Changbin Ducdcc4342017-01-13 11:16:00 +0800412 intel_vgpu_clean_mmio(vgpu);
Jike Song4e537892017-01-06 15:16:22 +0800413out_clean_idr:
414 idr_remove(&gvt->vgpu_idr, vgpu->id);
Zhi Wang82d375d2016-07-05 12:40:49 -0400415out_free_vgpu:
416 vfree(vgpu);
417 mutex_unlock(&gvt->lock);
418 return ERR_PTR(ret);
419}
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800420
421/**
422 * intel_gvt_create_vgpu - create a virtual GPU
423 * @gvt: GVT device
424 * @type: type of the vGPU to create
425 *
426 * This function is called when user wants to create a virtual GPU.
427 *
428 * Returns:
429 * pointer to intel_vgpu, error pointer if failed.
430 */
431struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
432 struct intel_vgpu_type *type)
433{
434 struct intel_vgpu_creation_params param;
435 struct intel_vgpu *vgpu;
436
437 param.handle = 0;
Du, Changbine992fae2016-11-21 17:08:14 +0800438 param.primary = 1;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800439 param.low_gm_sz = type->low_gm_size;
440 param.high_gm_sz = type->high_gm_size;
441 param.fence_sz = type->fence;
Ping Gaobc90d092017-03-30 00:36:37 +0800442 param.weight = type->weight;
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800443 param.resolution = type->resolution;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800444
445 /* XXX current param based on MB */
446 param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
447 param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
448
449 vgpu = __intel_gvt_create_vgpu(gvt, &param);
450 if (IS_ERR(vgpu))
451 return vgpu;
452
453 /* calculate left instance change for types */
454 intel_gvt_update_vgpu_types(gvt);
455
456 return vgpu;
457}
Jike Song9ec1e662016-11-03 18:38:35 +0800458
459/**
Changbin Ducfe65f42017-01-13 11:16:02 +0800460 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
461 * @vgpu: virtual GPU
462 * @dmlr: vGPU Device Model Level Reset or GT Reset
463 * @engine_mask: engines to reset for GT reset
464 *
465 * This function is called when user wants to reset a virtual GPU through
466 * device model reset or GT reset. The caller should hold the gvt lock.
467 *
468 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
469 * the whole vGPU to default state as when it is created. This vGPU function
470 * is required both for functionary and security concerns.The ultimate goal
471 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
472 * assign a vGPU to a virtual machine we must isse such reset first.
473 *
474 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
475 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
476 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
477 * the reset request. Guest driver can issue a GT reset by programming the
478 * virtual GDRST register to reset specific virtual GPU engine or all
479 * engines.
480 *
481 * The parameter dev_level is to identify if we will do DMLR or GT reset.
482 * The parameter engine_mask is to specific the engines that need to be
483 * resetted. If value ALL_ENGINES is given for engine_mask, it means
484 * the caller requests a full GT reset that we will reset all virtual
485 * GPU engines. For FLR, engine_mask is ignored.
486 */
487void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
488 unsigned int engine_mask)
489{
490 struct intel_gvt *gvt = vgpu->gvt;
491 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
Chuanxiao Dong6184cc82017-08-01 17:47:25 +0800492 unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
Changbin Ducfe65f42017-01-13 11:16:02 +0800493
494 gvt_dbg_core("------------------------------------------\n");
495 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
496 vgpu->id, dmlr, engine_mask);
Chuanxiao Dong6184cc82017-08-01 17:47:25 +0800497
498 vgpu->resetting_eng = resetting_eng;
Changbin Ducfe65f42017-01-13 11:16:02 +0800499
500 intel_vgpu_stop_schedule(vgpu);
501 /*
502 * The current_vgpu will set to NULL after stopping the
503 * scheduler when the reset is triggered by current vgpu.
504 */
505 if (scheduler->current_vgpu == NULL) {
506 mutex_unlock(&gvt->lock);
507 intel_gvt_wait_vgpu_idle(vgpu);
508 mutex_lock(&gvt->lock);
509 }
510
Zhi Wang06bb3722017-09-13 01:41:35 +0800511 intel_vgpu_reset_submission(vgpu, resetting_eng);
Changbin Ducfe65f42017-01-13 11:16:02 +0800512 /* full GPU reset or device model level reset */
513 if (engine_mask == ALL_ENGINES || dmlr) {
Zhi Wang06bb3722017-09-13 01:41:35 +0800514 intel_vgpu_select_submission_ops(vgpu, 0);
fred gao615c16a2017-05-25 15:33:52 +0800515
fred gao615c16a2017-05-25 15:33:52 +0800516 /*fence will not be reset during virtual reset */
Chuanxiao Dong4d3e67b2017-08-04 13:08:59 +0800517 if (dmlr) {
518 intel_vgpu_reset_gtt(vgpu);
fred gao615c16a2017-05-25 15:33:52 +0800519 intel_vgpu_reset_resource(vgpu);
Chuanxiao Dong4d3e67b2017-08-04 13:08:59 +0800520 }
fred gao615c16a2017-05-25 15:33:52 +0800521
522 intel_vgpu_reset_mmio(vgpu, dmlr);
Changbin Ducfe65f42017-01-13 11:16:02 +0800523 populate_pvinfo_page(vgpu);
Changbin Du6294b612017-02-14 14:50:18 +0800524 intel_vgpu_reset_display(vgpu);
Changbin Ducfe65f42017-01-13 11:16:02 +0800525
Min Hefd64be62017-02-17 15:02:36 +0800526 if (dmlr) {
Changbin Ducfe65f42017-01-13 11:16:02 +0800527 intel_vgpu_reset_cfg_space(vgpu);
Min Hefd64be62017-02-17 15:02:36 +0800528 /* only reset the failsafe mode when dmlr reset */
529 vgpu->failsafe = false;
530 vgpu->pv_notified = false;
531 }
Changbin Ducfe65f42017-01-13 11:16:02 +0800532 }
533
Chuanxiao Dong6184cc82017-08-01 17:47:25 +0800534 vgpu->resetting_eng = 0;
Changbin Ducfe65f42017-01-13 11:16:02 +0800535 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
536 gvt_dbg_core("------------------------------------------\n");
537}
538
539/**
540 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
Jike Song9ec1e662016-11-03 18:38:35 +0800541 * @vgpu: virtual GPU
542 *
543 * This function is called when user wants to reset a virtual GPU.
544 *
545 */
546void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
547{
Changbin Ducfe65f42017-01-13 11:16:02 +0800548 mutex_lock(&vgpu->gvt->lock);
549 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
550 mutex_unlock(&vgpu->gvt->lock);
Jike Song9ec1e662016-11-03 18:38:35 +0800551}