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David E. Box461844152014-01-08 13:27:51 -08001/*
Andy Shevchenko4077a382015-11-11 19:59:29 +02002 * Intel OnChip System Fabric MailBox access support
David E. Box461844152014-01-08 13:27:51 -08003 */
4
5#ifndef IOSF_MBI_SYMS_H
6#define IOSF_MBI_SYMS_H
7
8#define MBI_MCR_OFFSET 0xD0
9#define MBI_MDR_OFFSET 0xD4
10#define MBI_MCRX_OFFSET 0xD8
11
12#define MBI_RD_MASK 0xFEFFFFFF
13#define MBI_WR_MASK 0X01000000
14
15#define MBI_MASK_HI 0xFFFFFF00
16#define MBI_MASK_LO 0x000000FF
17#define MBI_ENABLE 0xF0
18
Andy Shevchenko4077a382015-11-11 19:59:29 +020019/* IOSF SB read/write opcodes */
20#define MBI_MMIO_READ 0x00
21#define MBI_MMIO_WRITE 0x01
Andy Shevchenkoeebb3e82015-12-12 02:45:06 +010022#define MBI_CFG_READ 0x04
23#define MBI_CFG_WRITE 0x05
Andy Shevchenko4077a382015-11-11 19:59:29 +020024#define MBI_CR_READ 0x06
25#define MBI_CR_WRITE 0x07
26#define MBI_REG_READ 0x10
27#define MBI_REG_WRITE 0x11
28#define MBI_ESRAM_READ 0x12
29#define MBI_ESRAM_WRITE 0x13
30
David E. Box461844152014-01-08 13:27:51 -080031/* Baytrail available units */
32#define BT_MBI_UNIT_AUNIT 0x00
33#define BT_MBI_UNIT_SMC 0x01
34#define BT_MBI_UNIT_CPU 0x02
35#define BT_MBI_UNIT_BUNIT 0x03
36#define BT_MBI_UNIT_PMC 0x04
37#define BT_MBI_UNIT_GFX 0x06
38#define BT_MBI_UNIT_SMI 0x0C
39#define BT_MBI_UNIT_USB 0x43
40#define BT_MBI_UNIT_SATA 0xA3
41#define BT_MBI_UNIT_PCIE 0xA6
42
Ong Boon Leong7ef1def2014-05-09 13:44:06 -070043/* Quark available units */
44#define QRK_MBI_UNIT_HBA 0x00
Andy Shevchenko7e1ff152015-07-08 17:45:08 +030045#define QRK_MBI_UNIT_HB 0x03
Ong Boon Leong7ef1def2014-05-09 13:44:06 -070046#define QRK_MBI_UNIT_RMU 0x04
Andy Shevchenko7e1ff152015-07-08 17:45:08 +030047#define QRK_MBI_UNIT_MM 0x05
Ong Boon Leong7ef1def2014-05-09 13:44:06 -070048#define QRK_MBI_UNIT_SOC 0x31
49
David E. Box6b8f0c82014-05-09 13:44:05 -070050#if IS_ENABLED(CONFIG_IOSF_MBI)
51
52bool iosf_mbi_available(void);
53
David E. Box461844152014-01-08 13:27:51 -080054/**
55 * iosf_mbi_read() - MailBox Interface read command
56 * @port: port indicating subunit being accessed
57 * @opcode: port specific read or write opcode
58 * @offset: register address offset
59 * @mdr: register data to be read
60 *
61 * Locking is handled by spinlock - cannot sleep.
62 * Return: Nonzero on error
63 */
64int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
65
66/**
67 * iosf_mbi_write() - MailBox unmasked write command
68 * @port: port indicating subunit being accessed
69 * @opcode: port specific read or write opcode
70 * @offset: register address offset
71 * @mdr: register data to be written
72 *
73 * Locking is handled by spinlock - cannot sleep.
74 * Return: Nonzero on error
75 */
76int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
77
78/**
79 * iosf_mbi_modify() - MailBox masked write command
80 * @port: port indicating subunit being accessed
81 * @opcode: port specific read or write opcode
82 * @offset: register address offset
83 * @mdr: register data being modified
84 * @mask: mask indicating bits in mdr to be modified
85 *
86 * Locking is handled by spinlock - cannot sleep.
87 * Return: Nonzero on error
88 */
89int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
90
Hans de Goede9260a042017-02-10 11:27:51 +010091/**
92 * iosf_mbi_punit_acquire() - Acquire access to the P-Unit
93 *
94 * One some systems the P-Unit accesses the PMIC to change various voltages
95 * through the same bus as other kernel drivers use for e.g. battery monitoring.
96 *
97 * If a driver sends requests to the P-Unit which require the P-Unit to access
98 * the PMIC bus while another driver is also accessing the PMIC bus various bad
99 * things happen.
100 *
101 * To avoid these problems this function must be called before accessing the
102 * P-Unit or the PMIC, be it through iosf_mbi* functions or through other means.
103 *
104 * Note on these systems the i2c-bus driver will request a sempahore from the
105 * P-Unit for exclusive access to the PMIC bus when i2c drivers are accessing
106 * it, but this does not appear to be sufficient, we still need to avoid making
107 * certain P-Unit requests during the access window to avoid problems.
108 *
109 * This function locks a mutex, as such it may sleep.
110 */
111void iosf_mbi_punit_acquire(void);
112
113/**
114 * iosf_mbi_punit_release() - Release access to the P-Unit
115 */
116void iosf_mbi_punit_release(void);
117
David E. Box6b8f0c82014-05-09 13:44:05 -0700118#else /* CONFIG_IOSF_MBI is not enabled */
119static inline
120bool iosf_mbi_available(void)
121{
122 return false;
123}
124
125static inline
126int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
127{
128 WARN(1, "IOSF_MBI driver not available");
129 return -EPERM;
130}
131
132static inline
133int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
134{
135 WARN(1, "IOSF_MBI driver not available");
136 return -EPERM;
137}
138
139static inline
140int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
141{
142 WARN(1, "IOSF_MBI driver not available");
143 return -EPERM;
144}
Hans de Goede9260a042017-02-10 11:27:51 +0100145
146static inline void iosf_mbi_punit_acquire(void) {}
147static inline void iosf_mbi_punit_release(void) {}
148
David E. Box6b8f0c82014-05-09 13:44:05 -0700149#endif /* CONFIG_IOSF_MBI */
150
David E. Box461844152014-01-08 13:27:51 -0800151#endif /* IOSF_MBI_SYMS_H */