blob: 1752ef006d26e44f2154293ba9c6f052cf2480e0 [file] [log] [blame]
Sreedhara DS9a58a332010-04-26 18:13:05 +01001/*
2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3 *
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * SCU runing in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
18 */
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/sysdev.h>
23#include <linux/pm.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
Alan Cox209009b2010-09-13 15:55:05 +010026#include <linux/sfi.h>
Sreedhara DS14d10f02010-07-26 10:02:25 +010027#include <asm/mrst.h>
Sreedhara DS9a58a332010-04-26 18:13:05 +010028#include <asm/intel_scu_ipc.h>
Feng Tang1da4b1c2010-11-09 11:22:58 +000029#include <asm/mrst.h>
Sreedhara DS9a58a332010-04-26 18:13:05 +010030
31/* IPC defines the following message types */
32#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
33#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
34#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
35#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
36#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
37
38/* Command id associated with message IPCMSG_PCNTRL */
39#define IPC_CMD_PCNTRL_W 0 /* Register write */
40#define IPC_CMD_PCNTRL_R 1 /* Register read */
41#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
42
Sreedhara DS9a58a332010-04-26 18:13:05 +010043/*
44 * IPC register summary
45 *
46 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
47 * To read or write information to the SCU, driver writes to IPC-1 memory
48 * mapped registers (base address 0xFF11C000). The following is the IPC
49 * mechanism
50 *
51 * 1. IA core cDMI interface claims this transaction and converts it to a
52 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
53 *
54 * 2. South Complex cDMI block receives this message and writes it to
55 * the IPC-1 register block, causing an interrupt to the SCU
56 *
57 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
58 * message handler is called within firmware.
59 */
60
61#define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
62#define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
Arjan van de Ven51cd5252010-07-26 10:04:24 +010063#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
64#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
Sreedhara DS9a58a332010-04-26 18:13:05 +010065#define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
66#define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
67
68static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
69static void ipc_remove(struct pci_dev *pdev);
70
71struct intel_scu_ipc_dev {
72 struct pci_dev *pdev;
73 void __iomem *ipc_base;
74 void __iomem *i2c_base;
75};
76
77static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
78
Sreedhara DS14d10f02010-07-26 10:02:25 +010079static int platform; /* Platform type */
Sreedhara DS9a58a332010-04-26 18:13:05 +010080
81/*
82 * IPC Read Buffer (Read Only):
83 * 16 byte buffer for receiving data from SCU, if IPC command
84 * processing results in response data
85 */
86#define IPC_READ_BUFFER 0x90
87
88#define IPC_I2C_CNTRL_ADDR 0
89#define I2C_DATA_ADDR 0x04
90
91static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
92
93/*
94 * Command Register (Write Only):
95 * A write to this register results in an interrupt to the SCU core processor
96 * Format:
97 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
98 */
99static inline void ipc_command(u32 cmd) /* Send ipc command */
100{
101 writel(cmd, ipcdev.ipc_base);
102}
103
104/*
105 * IPC Write Buffer (Write Only):
106 * 16-byte buffer for sending data associated with IPC command to
107 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
108 */
109static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
110{
111 writel(data, ipcdev.ipc_base + 0x80 + offset);
112}
113
114/*
Sreedhara DS9a58a332010-04-26 18:13:05 +0100115 * Status Register (Read Only):
116 * Driver will read this register to get the ready/busy status of the IPC
117 * block and error status of the IPC command that was just processed by SCU
118 * Format:
119 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
120 */
121
122static inline u8 ipc_read_status(void)
123{
124 return __raw_readl(ipcdev.ipc_base + 0x04);
125}
126
127static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
128{
129 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
130}
131
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100132static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
Sreedhara DS9a58a332010-04-26 18:13:05 +0100133{
134 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
135}
136
137static inline int busy_loop(void) /* Wait till scu status is busy */
138{
139 u32 status = 0;
140 u32 loop_count = 0;
141
142 status = ipc_read_status();
143 while (status & 1) {
144 udelay(1); /* scu processing time is in few u secods */
145 status = ipc_read_status();
146 loop_count++;
147 /* break if scu doesn't reset busy bit after huge retry */
148 if (loop_count > 100000) {
149 dev_err(&ipcdev.pdev->dev, "IPC timed out");
150 return -ETIMEDOUT;
151 }
152 }
Hong Liu77e01d62010-07-26 10:06:12 +0100153 if ((status >> 1) & 1)
154 return -EIO;
155
156 return 0;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100157}
158
159/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
160static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
161{
Hong Liu215c3302010-07-26 10:05:52 +0100162 int i, nc, bytes, d;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100163 u32 offset = 0;
164 u32 err = 0;
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100165 u8 cbuf[IPC_WWBUF_SIZE] = { };
Sreedhara DS9a58a332010-04-26 18:13:05 +0100166 u32 *wbuf = (u32 *)&cbuf;
167
168 mutex_lock(&ipclock);
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100169
Arjan van de Vened6f2b42010-07-26 10:04:37 +0100170 memset(cbuf, 0, sizeof(cbuf));
171
Sreedhara DS9a58a332010-04-26 18:13:05 +0100172 if (ipcdev.pdev == NULL) {
173 mutex_unlock(&ipclock);
174 return -ENODEV;
175 }
176
Alan Cox9dd3ade2010-07-26 10:03:58 +0100177 if (platform != MRST_CPU_CHIP_PENWELL) {
Andy Ross6c8d0fd2010-07-26 10:05:03 +0100178 bytes = 0;
Hong Liu215c3302010-07-26 10:05:52 +0100179 d = 0;
180 for (i = 0; i < count; i++) {
Andy Ross6c8d0fd2010-07-26 10:05:03 +0100181 cbuf[bytes++] = addr[i];
182 cbuf[bytes++] = addr[i] >> 8;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100183 if (id != IPC_CMD_PCNTRL_R)
Hong Liu215c3302010-07-26 10:05:52 +0100184 cbuf[bytes++] = data[d++];
Andy Ross6c8d0fd2010-07-26 10:05:03 +0100185 if (id == IPC_CMD_PCNTRL_M)
Hong Liu215c3302010-07-26 10:05:52 +0100186 cbuf[bytes++] = data[d++];
Sreedhara DS9a58a332010-04-26 18:13:05 +0100187 }
Hong Liu215c3302010-07-26 10:05:52 +0100188 for (i = 0; i < bytes; i += 4)
Andy Ross6c8d0fd2010-07-26 10:05:03 +0100189 ipc_data_writel(wbuf[i/4], i);
190 ipc_command(bytes << 16 | id << 12 | 0 << 8 | op);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100191 } else {
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100192 for (nc = 0; nc < count; nc++, offset += 2) {
193 cbuf[offset] = addr[nc];
194 cbuf[offset + 1] = addr[nc] >> 8;
195 }
196
197 if (id == IPC_CMD_PCNTRL_R) {
198 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
199 ipc_data_writel(wbuf[nc], offset);
200 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
201 } else if (id == IPC_CMD_PCNTRL_W) {
202 for (nc = 0; nc < count; nc++, offset += 1)
203 cbuf[offset] = data[nc];
204 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
205 ipc_data_writel(wbuf[nc], offset);
206 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
207 } else if (id == IPC_CMD_PCNTRL_M) {
208 cbuf[offset] = data[0];
209 cbuf[offset + 1] = data[1];
210 ipc_data_writel(wbuf[0], 0); /* Write wbuff */
211 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100212 }
213 }
214
Sreedhara DS9a58a332010-04-26 18:13:05 +0100215 err = busy_loop();
Sreedhara DS9a58a332010-04-26 18:13:05 +0100216 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
217 /* Workaround: values are read as 0 without memcpy_fromio */
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100218 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
Alan Cox9dd3ade2010-07-26 10:03:58 +0100219 if (platform != MRST_CPU_CHIP_PENWELL) {
Sreedhara DS9a58a332010-04-26 18:13:05 +0100220 for (nc = 0, offset = 2; nc < count; nc++, offset += 3)
221 data[nc] = ipc_data_readb(offset);
222 } else {
223 for (nc = 0; nc < count; nc++)
224 data[nc] = ipc_data_readb(nc);
225 }
226 }
227 mutex_unlock(&ipclock);
228 return err;
229}
230
231/**
232 * intel_scu_ipc_ioread8 - read a word via the SCU
233 * @addr: register on SCU
234 * @data: return pointer for read byte
235 *
236 * Read a single register. Returns 0 on success or an error code. All
237 * locking between SCU accesses is handled for the caller.
238 *
239 * This function may sleep.
240 */
241int intel_scu_ipc_ioread8(u16 addr, u8 *data)
242{
243 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
244}
245EXPORT_SYMBOL(intel_scu_ipc_ioread8);
246
247/**
248 * intel_scu_ipc_ioread16 - read a word via the SCU
249 * @addr: register on SCU
250 * @data: return pointer for read word
251 *
252 * Read a register pair. Returns 0 on success or an error code. All
253 * locking between SCU accesses is handled for the caller.
254 *
255 * This function may sleep.
256 */
257int intel_scu_ipc_ioread16(u16 addr, u16 *data)
258{
259 u16 x[2] = {addr, addr + 1 };
260 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
261}
262EXPORT_SYMBOL(intel_scu_ipc_ioread16);
263
264/**
265 * intel_scu_ipc_ioread32 - read a dword via the SCU
266 * @addr: register on SCU
267 * @data: return pointer for read dword
268 *
269 * Read four registers. Returns 0 on success or an error code. All
270 * locking between SCU accesses is handled for the caller.
271 *
272 * This function may sleep.
273 */
274int intel_scu_ipc_ioread32(u16 addr, u32 *data)
275{
276 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
277 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
278}
279EXPORT_SYMBOL(intel_scu_ipc_ioread32);
280
281/**
282 * intel_scu_ipc_iowrite8 - write a byte via the SCU
283 * @addr: register on SCU
284 * @data: byte to write
285 *
286 * Write a single register. Returns 0 on success or an error code. All
287 * locking between SCU accesses is handled for the caller.
288 *
289 * This function may sleep.
290 */
291int intel_scu_ipc_iowrite8(u16 addr, u8 data)
292{
293 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
294}
295EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
296
297/**
298 * intel_scu_ipc_iowrite16 - write a word via the SCU
299 * @addr: register on SCU
300 * @data: word to write
301 *
302 * Write two registers. Returns 0 on success or an error code. All
303 * locking between SCU accesses is handled for the caller.
304 *
305 * This function may sleep.
306 */
307int intel_scu_ipc_iowrite16(u16 addr, u16 data)
308{
309 u16 x[2] = {addr, addr + 1 };
310 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
311}
312EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
313
314/**
315 * intel_scu_ipc_iowrite32 - write a dword via the SCU
316 * @addr: register on SCU
317 * @data: dword to write
318 *
319 * Write four registers. Returns 0 on success or an error code. All
320 * locking between SCU accesses is handled for the caller.
321 *
322 * This function may sleep.
323 */
324int intel_scu_ipc_iowrite32(u16 addr, u32 data)
325{
326 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
327 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
328}
329EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
330
331/**
332 * intel_scu_ipc_readvv - read a set of registers
333 * @addr: register list
334 * @data: bytes to return
335 * @len: length of array
336 *
337 * Read registers. Returns 0 on success or an error code. All
338 * locking between SCU accesses is handled for the caller.
339 *
340 * The largest array length permitted by the hardware is 5 items.
341 *
342 * This function may sleep.
343 */
344int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
345{
346 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
347}
348EXPORT_SYMBOL(intel_scu_ipc_readv);
349
350/**
351 * intel_scu_ipc_writev - write a set of registers
352 * @addr: register list
353 * @data: bytes to write
354 * @len: length of array
355 *
356 * Write registers. Returns 0 on success or an error code. All
357 * locking between SCU accesses is handled for the caller.
358 *
359 * The largest array length permitted by the hardware is 5 items.
360 *
361 * This function may sleep.
362 *
363 */
364int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
365{
366 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
367}
368EXPORT_SYMBOL(intel_scu_ipc_writev);
369
370
371/**
372 * intel_scu_ipc_update_register - r/m/w a register
373 * @addr: register address
374 * @bits: bits to update
375 * @mask: mask of bits to update
376 *
377 * Read-modify-write power control unit register. The first data argument
378 * must be register value and second is mask value
379 * mask is a bitmap that indicates which bits to update.
380 * 0 = masked. Don't modify this bit, 1 = modify this bit.
381 * returns 0 on success or an error code.
382 *
383 * This function may sleep. Locking between SCU accesses is handled
384 * for the caller.
385 */
386int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
387{
388 u8 data[2] = { bits, mask };
389 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
390}
391EXPORT_SYMBOL(intel_scu_ipc_update_register);
392
393/**
Sreedhara DS9a58a332010-04-26 18:13:05 +0100394 * intel_scu_ipc_simple_command - send a simple command
395 * @cmd: command
396 * @sub: sub type
397 *
398 * Issue a simple command to the SCU. Do not use this interface if
399 * you must then access data as any data values may be overwritten
400 * by another SCU access by the time this function returns.
401 *
402 * This function may sleep. Locking for SCU accesses is handled for
403 * the caller.
404 */
405int intel_scu_ipc_simple_command(int cmd, int sub)
406{
407 u32 err = 0;
408
409 mutex_lock(&ipclock);
410 if (ipcdev.pdev == NULL) {
411 mutex_unlock(&ipclock);
412 return -ENODEV;
413 }
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100414 ipc_command(sub << 12 | cmd);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100415 err = busy_loop();
416 mutex_unlock(&ipclock);
417 return err;
418}
419EXPORT_SYMBOL(intel_scu_ipc_simple_command);
420
421/**
422 * intel_scu_ipc_command - command with data
423 * @cmd: command
424 * @sub: sub type
425 * @in: input data
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100426 * @inlen: input length in dwords
Sreedhara DS9a58a332010-04-26 18:13:05 +0100427 * @out: output data
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100428 * @outlein: output length in dwords
Sreedhara DS9a58a332010-04-26 18:13:05 +0100429 *
430 * Issue a command to the SCU which involves data transfers. Do the
431 * data copies under the lock but leave it for the caller to interpret
432 */
433
434int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
435 u32 *out, int outlen)
436{
437 u32 err = 0;
438 int i = 0;
439
440 mutex_lock(&ipclock);
441 if (ipcdev.pdev == NULL) {
442 mutex_unlock(&ipclock);
443 return -ENODEV;
444 }
445
446 for (i = 0; i < inlen; i++)
447 ipc_data_writel(*in++, 4 * i);
448
Hong Liu5aa06932010-07-26 10:06:31 +0100449 ipc_command((inlen << 16) | (sub << 12) | cmd);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100450 err = busy_loop();
451
452 for (i = 0; i < outlen; i++)
453 *out++ = ipc_data_readl(4 * i);
454
455 mutex_unlock(&ipclock);
456 return err;
457}
458EXPORT_SYMBOL(intel_scu_ipc_command);
459
460/*I2C commands */
461#define IPC_I2C_WRITE 1 /* I2C Write command */
462#define IPC_I2C_READ 2 /* I2C Read command */
463
464/**
465 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
466 * @addr: I2C address + command bits
467 * @data: data to read/write
468 *
469 * Perform an an I2C read/write operation via the SCU. All locking is
470 * handled for the caller. This function may sleep.
471 *
472 * Returns an error code or 0 on success.
473 *
474 * This has to be in the IPC driver for the locking.
475 */
476int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
477{
478 u32 cmd = 0;
479
480 mutex_lock(&ipclock);
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100481 if (ipcdev.pdev == NULL) {
482 mutex_unlock(&ipclock);
483 return -ENODEV;
484 }
Sreedhara DS9a58a332010-04-26 18:13:05 +0100485 cmd = (addr >> 24) & 0xFF;
486 if (cmd == IPC_I2C_READ) {
487 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
488 /* Write not getting updated without delay */
489 mdelay(1);
490 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
491 } else if (cmd == IPC_I2C_WRITE) {
Jianwei Yang32e2f632010-08-24 14:32:38 +0100492 writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100493 mdelay(1);
494 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
495 } else {
496 dev_err(&ipcdev.pdev->dev,
497 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
498
499 mutex_unlock(&ipclock);
Sreedhara DS5369c02d2010-10-22 15:43:55 +0100500 return -EIO;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100501 }
502 mutex_unlock(&ipclock);
503 return 0;
504}
505EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
506
507#define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */
508#define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */
509#define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */
510#define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */
511/* IPC inform SCU to get ready for update process */
512#define IPC_CMD_FW_UPDATE_READY 0x10FE
513/* IPC inform SCU to go for update process */
514#define IPC_CMD_FW_UPDATE_GO 0x20FE
515/* Status code for fw update */
516#define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */
517#define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */
518#define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */
519#define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */
520
521struct fw_update_mailbox {
522 u32 status;
523 u32 scu_flag;
524 u32 driver_flag;
525};
526
527
528/**
529 * intel_scu_ipc_fw_update - Firmware update utility
530 * @buffer: firmware buffer
531 * @length: size of firmware buffer
532 *
533 * This function provides an interface to load the firmware into
534 * the SCU. Returns 0 on success or -1 on failure
535 */
536int intel_scu_ipc_fw_update(u8 *buffer, u32 length)
537{
538 void __iomem *fw_update_base;
539 struct fw_update_mailbox __iomem *mailbox = NULL;
540 int retry_cnt = 0;
541 u32 status;
542
543 mutex_lock(&ipclock);
544 fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024));
545 if (fw_update_base == NULL) {
546 mutex_unlock(&ipclock);
547 return -ENOMEM;
548 }
549 mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR,
550 sizeof(struct fw_update_mailbox));
551 if (mailbox == NULL) {
552 iounmap(fw_update_base);
553 mutex_unlock(&ipclock);
554 return -ENOMEM;
555 }
556
557 ipc_command(IPC_CMD_FW_UPDATE_READY);
558
559 /* Intitialize mailbox */
560 writel(0, &mailbox->status);
561 writel(0, &mailbox->scu_flag);
562 writel(0, &mailbox->driver_flag);
563
564 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/
565 memcpy_toio(fw_update_base, buffer, 0x800);
566
567 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02).
568 * Upon receiving this command, SCU will write the 2K MIP header
569 * from 0xFFFC0000 into NAND.
570 * SCU will write a status code into the Mailbox, and then set scu_flag.
571 */
572
573 ipc_command(IPC_CMD_FW_UPDATE_GO);
574
575 /*Driver stalls until scu_flag is set */
576 while (readl(&mailbox->scu_flag) != 1) {
577 rmb();
578 mdelay(1);
579 }
580
581 /* Driver checks Mailbox status.
582 * If the status is 'BADN', then abort (bad NAND).
583 * If the status is 'IPC_FW_TXLOW', then continue.
584 */
585 while (readl(&mailbox->status) != IPC_FW_TXLOW) {
586 rmb();
587 mdelay(10);
588 }
589 mdelay(10);
590
591update_retry:
592 if (retry_cnt > 5)
593 goto update_end;
594
595 if (readl(&mailbox->status) != IPC_FW_TXLOW)
596 goto update_end;
597 buffer = buffer + 0x800;
598 memcpy_toio(fw_update_base, buffer, 0x20000);
599 writel(1, &mailbox->driver_flag);
600 while (readl(&mailbox->scu_flag) == 1) {
601 rmb();
602 mdelay(1);
603 }
604
605 /* check for 'BADN' */
606 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
607 goto update_end;
608
609 while (readl(&mailbox->status) != IPC_FW_TXHIGH) {
610 rmb();
611 mdelay(10);
612 }
613 mdelay(10);
614
615 if (readl(&mailbox->status) != IPC_FW_TXHIGH)
616 goto update_end;
617
618 buffer = buffer + 0x20000;
619 memcpy_toio(fw_update_base, buffer, 0x20000);
620 writel(0, &mailbox->driver_flag);
621
622 while (mailbox->scu_flag == 0) {
623 rmb();
624 mdelay(1);
625 }
626
627 /* check for 'BADN' */
628 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
629 goto update_end;
630
631 if (readl(&mailbox->status) == IPC_FW_TXLOW) {
632 ++retry_cnt;
633 goto update_retry;
634 }
635
636update_end:
637 status = readl(&mailbox->status);
638
639 iounmap(fw_update_base);
640 iounmap(mailbox);
641 mutex_unlock(&ipclock);
642
643 if (status == IPC_FW_UPDATE_SUCCESS)
644 return 0;
Sreedhara DS5369c02d2010-10-22 15:43:55 +0100645 return -EIO;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100646}
647EXPORT_SYMBOL(intel_scu_ipc_fw_update);
648
649/*
650 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
651 * When ioc bit is set to 1, caller api must wait for interrupt handler called
652 * which in turn unlocks the caller api. Currently this is not used
653 *
654 * This is edge triggered so we need take no action to clear anything
655 */
656static irqreturn_t ioc(int irq, void *dev_id)
657{
658 return IRQ_HANDLED;
659}
660
661/**
662 * ipc_probe - probe an Intel SCU IPC
663 * @dev: the PCI device matching
664 * @id: entry in the match table
665 *
666 * Enable and install an intel SCU IPC. This appears in the PCI space
667 * but uses some hard coded addresses as well.
668 */
669static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
670{
671 int err;
672 resource_size_t pci_resource;
673
674 if (ipcdev.pdev) /* We support only one SCU */
675 return -EBUSY;
676
677 ipcdev.pdev = pci_dev_get(dev);
678
679 err = pci_enable_device(dev);
680 if (err)
681 return err;
682
683 err = pci_request_regions(dev, "intel_scu_ipc");
684 if (err)
685 return err;
686
687 pci_resource = pci_resource_start(dev, 0);
688 if (!pci_resource)
689 return -ENOMEM;
690
691 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
692 return -EBUSY;
693
694 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
695 if (!ipcdev.ipc_base)
696 return -ENOMEM;
697
698 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
699 if (!ipcdev.i2c_base) {
700 iounmap(ipcdev.ipc_base);
701 return -ENOMEM;
702 }
Feng Tang1da4b1c2010-11-09 11:22:58 +0000703
704 intel_scu_devices_create();
705
Sreedhara DS9a58a332010-04-26 18:13:05 +0100706 return 0;
707}
708
709/**
710 * ipc_remove - remove a bound IPC device
711 * @pdev: PCI device
712 *
713 * In practice the SCU is not removable but this function is also
714 * called for each device on a module unload or cleanup which is the
715 * path that will get used.
716 *
717 * Free up the mappings and release the PCI resources
718 */
719static void ipc_remove(struct pci_dev *pdev)
720{
721 free_irq(pdev->irq, &ipcdev);
722 pci_release_regions(pdev);
723 pci_dev_put(ipcdev.pdev);
724 iounmap(ipcdev.ipc_base);
725 iounmap(ipcdev.i2c_base);
726 ipcdev.pdev = NULL;
Feng Tang1da4b1c2010-11-09 11:22:58 +0000727 intel_scu_devices_destroy();
Sreedhara DS9a58a332010-04-26 18:13:05 +0100728}
729
730static const struct pci_device_id pci_ids[] = {
731 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)},
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100732 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
Sreedhara DS9a58a332010-04-26 18:13:05 +0100733 { 0,}
734};
735MODULE_DEVICE_TABLE(pci, pci_ids);
736
737static struct pci_driver ipc_driver = {
738 .name = "intel_scu_ipc",
739 .id_table = pci_ids,
740 .probe = ipc_probe,
741 .remove = ipc_remove,
742};
743
744
745static int __init intel_scu_ipc_init(void)
746{
Alan Cox9dd3ade2010-07-26 10:03:58 +0100747 platform = mrst_identify_cpu();
748 if (platform == 0)
749 return -ENODEV;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100750 return pci_register_driver(&ipc_driver);
751}
752
753static void __exit intel_scu_ipc_exit(void)
754{
755 pci_unregister_driver(&ipc_driver);
756}
757
758MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
759MODULE_DESCRIPTION("Intel SCU IPC driver");
760MODULE_LICENSE("GPL");
761
762module_init(intel_scu_ipc_init);
763module_exit(intel_scu_ipc_exit);