| Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 1 | #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ |
| 2 | #define _ASM_POWERPC_BOOK3S_64_MMU_H_ |
| 3 | |
| 4 | #ifndef __ASSEMBLY__ |
| 5 | /* |
| 6 | * Page size definition |
| 7 | * |
| 8 | * shift : is the "PAGE_SHIFT" value for that page size |
| 9 | * sllp : is a bit mask with the value of SLB L || LP to be or'ed |
| 10 | * directly to a slbmte "vsid" value |
| 11 | * penc : is the HPTE encoding mask for the "LP" field: |
| 12 | * |
| 13 | */ |
| 14 | struct mmu_psize_def { |
| 15 | unsigned int shift; /* number of bits */ |
| 16 | int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ |
| 17 | unsigned int tlbiel; /* tlbiel supported for that page size */ |
| 18 | unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ |
| 19 | unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ |
| 20 | }; |
| 21 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; |
| 22 | #endif /* __ASSEMBLY__ */ |
| 23 | |
| Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 24 | /* 64-bit classic hash table MMU */ |
| 25 | #include <asm/book3s/64/mmu-hash.h> |
| Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 26 | |
| 27 | #ifndef __ASSEMBLY__ |
| Aneesh Kumar K.V | e998334 | 2016-04-29 23:25:42 +1000 | [diff] [blame] | 28 | /* |
| 29 | * ISA 3.0 partiton and process table entry format |
| 30 | */ |
| 31 | struct prtb_entry { |
| 32 | __be64 prtb0; |
| 33 | __be64 prtb1; |
| 34 | }; |
| 35 | extern struct prtb_entry *process_tb; |
| 36 | |
| 37 | struct patb_entry { |
| 38 | __be64 patb0; |
| 39 | __be64 patb1; |
| 40 | }; |
| 41 | extern struct patb_entry *partition_tb; |
| 42 | |
| 43 | #define PATB_HR (1UL << 63) |
| 44 | #define PATB_GR (1UL << 63) |
| 45 | #define RPDB_MASK 0x0ffffffffffff00fUL |
| 46 | #define RPDB_SHIFT (1UL << 8) |
| 47 | /* |
| 48 | * Limit process table to PAGE_SIZE table. This |
| 49 | * also limit the max pid we can support. |
| 50 | * MAX_USER_CONTEXT * 16 bytes of space. |
| 51 | */ |
| 52 | #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4) |
| 53 | /* |
| 54 | * Power9 currently only support 64K partition table size. |
| 55 | */ |
| 56 | #define PATB_SIZE_SHIFT 16 |
| Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 57 | |
| 58 | typedef unsigned long mm_context_id_t; |
| 59 | struct spinlock; |
| 60 | |
| 61 | typedef struct { |
| 62 | mm_context_id_t id; |
| 63 | u16 user_psize; /* page size index */ |
| 64 | |
| 65 | #ifdef CONFIG_PPC_MM_SLICES |
| 66 | u64 low_slices_psize; /* SLB page size encodings */ |
| 67 | unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; |
| 68 | #else |
| 69 | u16 sllp; /* SLB page size encoding */ |
| 70 | #endif |
| 71 | unsigned long vdso_base; |
| 72 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
| 73 | struct subpage_prot_table spt; |
| 74 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ |
| 75 | #ifdef CONFIG_PPC_ICSWX |
| 76 | struct spinlock *cop_lockp; /* guard acop and cop_pid */ |
| 77 | unsigned long acop; /* mask of enabled coprocessor types */ |
| 78 | unsigned int cop_pid; /* pid value used with coprocessors */ |
| 79 | #endif /* CONFIG_PPC_ICSWX */ |
| 80 | #ifdef CONFIG_PPC_64K_PAGES |
| 81 | /* for 4K PTE fragment support */ |
| 82 | void *pte_frag; |
| 83 | #endif |
| 84 | #ifdef CONFIG_SPAPR_TCE_IOMMU |
| 85 | struct list_head iommu_group_mem_list; |
| 86 | #endif |
| 87 | } mm_context_t; |
| 88 | |
| 89 | /* |
| 90 | * The current system page and segment sizes |
| 91 | */ |
| 92 | extern int mmu_linear_psize; |
| 93 | extern int mmu_virtual_psize; |
| 94 | extern int mmu_vmalloc_psize; |
| 95 | extern int mmu_vmemmap_psize; |
| 96 | extern int mmu_io_psize; |
| 97 | |
| 98 | #endif /* __ASSEMBLY__ */ |
| 99 | #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */ |