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gerrit-public.fairphone.software / kernel / msm-5.4 / 56f6ed1ce13b0cb85ae9537f839df7c4ba1f5369 / . / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.h
blob: 0769b40399eaec90b0896de86225702883e8b5a5 [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Don Skidmorec97506a2014-02-27 20:32:43 -0800[diff] [blame]4 Copyright(c) 1999 - 2014 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Jacob Kellerb89aae72014-02-22 01:23:50 +0000[diff] [blame]23 Linux NICS <linux.nics@intel.com>
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_PHY_H_
30#define _IXGBE_PHY_H_
31
32#include "ixgbe_type.h"
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]33#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame]34#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]35
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]36/* EEPROM byte offsets */
Don Skidmore8f583322013-07-27 06:25:38 +0000[diff] [blame]37#define IXGBE_SFF_IDENTIFIER 0x0
38#define IXGBE_SFF_IDENTIFIER_SFP 0x3
39#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
40#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
41#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
42#define IXGBE_SFF_1GBE_COMP_CODES 0x6
43#define IXGBE_SFF_10GBE_COMP_CODES 0x3
44#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
45#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
46#define IXGBE_SFF_SFF_8472_SWAP 0x5C
47#define IXGBE_SFF_SFF_8472_COMP 0x5E
48#define IXGBE_SFF_SFF_8472_OSCB 0x6E
49#define IXGBE_SFF_SFF_8472_ESCB 0x76
50#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD
51#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
52#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
53#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
Emil Tantilov9a84fea2013-08-16 23:11:14 +0000[diff] [blame]54#define IXGBE_SFF_QSFP_CONNECTOR 0x82
Don Skidmore8f583322013-07-27 06:25:38 +0000[diff] [blame]55#define IXGBE_SFF_QSFP_10GBE_COMP 0x83
56#define IXGBE_SFF_QSFP_1GBE_COMP 0x86
Emil Tantilov9a84fea2013-08-16 23:11:14 +0000[diff] [blame]57#define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
58#define IXGBE_SFF_QSFP_DEVICE_TECH 0x93
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]59
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]60/* Bitmasks */
Jeff Kirsherb0007482013-10-01 04:33:53 -0700[diff] [blame]61#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
62#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
63#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
64#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
65#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
66#define IXGBE_SFF_1GBASET_CAPABLE 0x8
67#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
68#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
Jeff Kirsherb0007482013-10-01 04:33:53 -0700[diff] [blame]69#define IXGBE_SFF_ADDRESSING_MODE 0x4
70#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
71#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
Emil Tantilov9a84fea2013-08-16 23:11:14 +0000[diff] [blame]72#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
73#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
Jeff Kirsherb0007482013-10-01 04:33:53 -0700[diff] [blame]74#define IXGBE_I2C_EEPROM_READ_MASK 0x100
75#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
76#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
77#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
78#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
79#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
Don Skidmore6a14ee02014-12-05 03:59:50 +0000[diff] [blame]80#define IXGBE_CS4227 0xBE /* CS4227 address */
81#define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */
82#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
83#define IXGBE_CS4227_EDC_MODE_SR 0x0004
84
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000[diff] [blame]85/* Flow control defines */
86#define IXGBE_TAF_SYM_PAUSE 0x400
87#define IXGBE_TAF_ASM_PAUSE 0x800
88
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]89/* Bit-shift macros */
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]90#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
91#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
92#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]93
94/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
95#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
96#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
97#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]98#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]99
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]100/* I2C SDA and SCL timing parameters for standard mode */
101#define IXGBE_I2C_T_HD_STA 4
102#define IXGBE_I2C_T_LOW 5
103#define IXGBE_I2C_T_HIGH 4
104#define IXGBE_I2C_T_SU_STA 5
105#define IXGBE_I2C_T_HD_DATA 5
106#define IXGBE_I2C_T_SU_DATA 1
107#define IXGBE_I2C_T_RISE 1
108#define IXGBE_I2C_T_FALL 1
109#define IXGBE_I2C_T_SU_STO 4
110#define IXGBE_I2C_T_BUF 5
111
Mark Rustad56f6ed12015-08-08 16:18:22 -0700[diff] [blame^]112#define IXGBE_SFP_DETECT_RETRIES 2
113
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -0700[diff] [blame]114#define IXGBE_TN_LASI_STATUS_REG 0x9005
115#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]116
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame]117/* SFP+ SFF-8472 Compliance code */
118#define IXGBE_SFF_SFF_8472_UNSUP 0x00
119
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]120s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
121s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
122s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]123 u32 device_type, u16 *phy_data);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]124s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]125 u32 device_type, u16 phy_data);
Emil Tantilov3dcc2f412013-05-29 06:23:05 +0000[diff] [blame]126s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
127 u32 device_type, u16 *phy_data);
128s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
129 u32 device_type, u16 phy_data);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]130s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
131s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]132 ixgbe_link_speed speed,
133 bool autoneg_wait_to_complete);
Don Skidmorea391f1d2010-11-16 19:27:15 -0800[diff] [blame]134s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]135 ixgbe_link_speed *speed,
136 bool *autoneg);
Jean Sacren6425f0f2014-03-11 05:57:56 +0000[diff] [blame]137bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]138
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]139/* PHY specific */
140s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]141 ixgbe_link_speed *speed,
142 bool *link_up);
Emil Tantilov9dda1732011-03-05 01:28:07 +0000[diff] [blame]143s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]144s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]145 u16 *firmware_version);
Don Skidmorefe15e8e12010-11-16 19:27:16 -0800[diff] [blame]146s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]147 u16 *firmware_version);
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]148
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]149s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
Don Skidmore961fac82015-06-09 16:09:47 -0700[diff] [blame]150s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
Don Skidmore8f583322013-07-27 06:25:38 +0000[diff] [blame]151s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]152s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
153s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]154 u16 *list_offset,
155 u16 *data_offset);
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -0700[diff] [blame]156s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]157s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]158 u8 dev_addr, u8 *data);
Mark Rustadbb5ce9a52015-08-08 16:18:02 -0700[diff] [blame]159s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
160 u8 dev_addr, u8 *data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]161s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]162 u8 dev_addr, u8 data);
Mark Rustadbb5ce9a52015-08-08 16:18:02 -0700[diff] [blame]163s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
164 u8 dev_addr, u8 data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]165s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]166 u8 *eeprom_data);
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame]167s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
168 u8 *sff8472_data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]169s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000[diff] [blame]170 u8 eeprom_data);
Don Skidmore28abba02014-11-29 05:22:43 +0000[diff] [blame]171s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
172 u16 reg, u16 *val);
Mark Rustadbb5ce9a52015-08-08 16:18:02 -0700[diff] [blame]173s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
174 u16 reg, u16 *val);
Don Skidmore28abba02014-11-29 05:22:43 +0000[diff] [blame]175s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
176 u16 reg, u16 val);
Mark Rustadbb5ce9a52015-08-08 16:18:02 -0700[diff] [blame]177s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
178 u16 reg, u16 val);
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]179#endif /* _IXGBE_PHY_H_ */