Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / d3c19c0a72b7e1affce86a4eaa634af0c72fce61 / . / drivers / net / ethernet / amd / xgbe / xgbe-phy-v2.c
blob: 348cc8cf5e74f9b7920e0028b9c70fd7d7f3554a [file] [log] [blame]
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/module.h>
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]118#include <linux/device.h>
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]119#include <linux/kmod.h>
120#include <linux/mdio.h>
121#include <linux/phy.h>
122
123#include "xgbe.h"
124#include "xgbe-common.h"
125
126#define XGBE_PHY_PORT_SPEED_100 BIT(0)
127#define XGBE_PHY_PORT_SPEED_1000 BIT(1)
128#define XGBE_PHY_PORT_SPEED_2500 BIT(2)
129#define XGBE_PHY_PORT_SPEED_10000 BIT(3)
130
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]131#define XGBE_MUTEX_RELEASE 0x80000000
132
133#define XGBE_SFP_DIRECT 7
134
135/* I2C target addresses */
136#define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
137#define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
138#define XGBE_SFP_PHY_ADDRESS 0x56
139#define XGBE_GPIO_ADDRESS_PCA9555 0x20
140
141/* SFP sideband signal indicators */
142#define XGBE_GPIO_NO_TX_FAULT BIT(0)
143#define XGBE_GPIO_NO_RATE_SELECT BIT(1)
144#define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
145#define XGBE_GPIO_NO_RX_LOS BIT(3)
146
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]147/* Rate-change complete wait/retry count */
148#define XGBE_RATECHANGE_COUNT 500
149
150enum xgbe_port_mode {
151 XGBE_PORT_MODE_RSVD = 0,
152 XGBE_PORT_MODE_BACKPLANE,
153 XGBE_PORT_MODE_BACKPLANE_2500,
154 XGBE_PORT_MODE_1000BASE_T,
155 XGBE_PORT_MODE_1000BASE_X,
156 XGBE_PORT_MODE_NBASE_T,
157 XGBE_PORT_MODE_10GBASE_T,
158 XGBE_PORT_MODE_10GBASE_R,
159 XGBE_PORT_MODE_SFP,
160 XGBE_PORT_MODE_MAX,
161};
162
163enum xgbe_conn_type {
164 XGBE_CONN_TYPE_NONE = 0,
165 XGBE_CONN_TYPE_SFP,
166 XGBE_CONN_TYPE_MDIO,
167 XGBE_CONN_TYPE_BACKPLANE,
168 XGBE_CONN_TYPE_MAX,
169};
170
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]171/* SFP/SFP+ related definitions */
172enum xgbe_sfp_comm {
173 XGBE_SFP_COMM_DIRECT = 0,
174 XGBE_SFP_COMM_PCA9545,
175};
176
177enum xgbe_sfp_cable {
178 XGBE_SFP_CABLE_UNKNOWN = 0,
179 XGBE_SFP_CABLE_ACTIVE,
180 XGBE_SFP_CABLE_PASSIVE,
181};
182
183enum xgbe_sfp_base {
184 XGBE_SFP_BASE_UNKNOWN = 0,
185 XGBE_SFP_BASE_1000_T,
186 XGBE_SFP_BASE_1000_SX,
187 XGBE_SFP_BASE_1000_LX,
188 XGBE_SFP_BASE_1000_CX,
189 XGBE_SFP_BASE_10000_SR,
190 XGBE_SFP_BASE_10000_LR,
191 XGBE_SFP_BASE_10000_LRM,
192 XGBE_SFP_BASE_10000_ER,
193 XGBE_SFP_BASE_10000_CR,
194};
195
196enum xgbe_sfp_speed {
197 XGBE_SFP_SPEED_UNKNOWN = 0,
198 XGBE_SFP_SPEED_100_1000,
199 XGBE_SFP_SPEED_1000,
200 XGBE_SFP_SPEED_10000,
201};
202
203/* SFP Serial ID Base ID values relative to an offset of 0 */
204#define XGBE_SFP_BASE_ID 0
205#define XGBE_SFP_ID_SFP 0x03
206
207#define XGBE_SFP_BASE_EXT_ID 1
208#define XGBE_SFP_EXT_ID_SFP 0x04
209
210#define XGBE_SFP_BASE_10GBE_CC 3
211#define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
212#define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
213#define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
214#define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
215
216#define XGBE_SFP_BASE_1GBE_CC 6
217#define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
218#define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
219#define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
220#define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
221
222#define XGBE_SFP_BASE_CABLE 8
223#define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
224#define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
225
226#define XGBE_SFP_BASE_BR 12
227#define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
228#define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
229#define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
230#define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
231
232#define XGBE_SFP_BASE_CU_CABLE_LEN 18
233
234#define XGBE_SFP_BASE_VENDOR_NAME 20
235#define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
236#define XGBE_SFP_BASE_VENDOR_PN 40
237#define XGBE_SFP_BASE_VENDOR_PN_LEN 16
238#define XGBE_SFP_BASE_VENDOR_REV 56
239#define XGBE_SFP_BASE_VENDOR_REV_LEN 4
240
241#define XGBE_SFP_BASE_CC 63
242
243/* SFP Serial ID Extended ID values relative to an offset of 64 */
244#define XGBE_SFP_BASE_VENDOR_SN 4
245#define XGBE_SFP_BASE_VENDOR_SN_LEN 16
246
247#define XGBE_SFP_EXTD_DIAG 28
248#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
249
250#define XGBE_SFP_EXTD_SFF_8472 30
251
252#define XGBE_SFP_EXTD_CC 31
253
254struct xgbe_sfp_eeprom {
255 u8 base[64];
256 u8 extd[32];
257 u8 vendor[32];
258};
259
260#define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
261#define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
262
263struct xgbe_sfp_ascii {
264 union {
265 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
266 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
267 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
268 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
269 } u;
270};
271
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]272/* MDIO PHY reset types */
273enum xgbe_mdio_reset {
274 XGBE_MDIO_RESET_NONE = 0,
275 XGBE_MDIO_RESET_I2C_GPIO,
276 XGBE_MDIO_RESET_INT_GPIO,
277 XGBE_MDIO_RESET_MAX,
278};
279
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]280/* Re-driver related definitions */
281enum xgbe_phy_redrv_if {
282 XGBE_PHY_REDRV_IF_MDIO = 0,
283 XGBE_PHY_REDRV_IF_I2C,
284 XGBE_PHY_REDRV_IF_MAX,
285};
286
287enum xgbe_phy_redrv_model {
288 XGBE_PHY_REDRV_MODEL_4223 = 0,
289 XGBE_PHY_REDRV_MODEL_4227,
290 XGBE_PHY_REDRV_MODEL_MAX,
291};
292
293enum xgbe_phy_redrv_mode {
294 XGBE_PHY_REDRV_MODE_CX = 5,
295 XGBE_PHY_REDRV_MODE_SR = 9,
296};
297
298#define XGBE_PHY_REDRV_MODE_REG 0x12b0
299
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]300/* PHY related configuration information */
301struct xgbe_phy_data {
302 enum xgbe_port_mode port_mode;
303
304 unsigned int port_id;
305
306 unsigned int port_speeds;
307
308 enum xgbe_conn_type conn_type;
309
310 enum xgbe_mode cur_mode;
311 enum xgbe_mode start_mode;
312
313 unsigned int rrc_count;
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]314
315 unsigned int mdio_addr;
316
317 unsigned int comm_owned;
318
319 /* SFP Support */
320 enum xgbe_sfp_comm sfp_comm;
321 unsigned int sfp_mux_address;
322 unsigned int sfp_mux_channel;
323
324 unsigned int sfp_gpio_address;
325 unsigned int sfp_gpio_mask;
326 unsigned int sfp_gpio_rx_los;
327 unsigned int sfp_gpio_tx_fault;
328 unsigned int sfp_gpio_mod_absent;
329 unsigned int sfp_gpio_rate_select;
330
331 unsigned int sfp_rx_los;
332 unsigned int sfp_tx_fault;
333 unsigned int sfp_mod_absent;
334 unsigned int sfp_diags;
335 unsigned int sfp_changed;
336 unsigned int sfp_phy_avail;
337 unsigned int sfp_cable_len;
338 enum xgbe_sfp_base sfp_base;
339 enum xgbe_sfp_cable sfp_cable;
340 enum xgbe_sfp_speed sfp_speed;
341 struct xgbe_sfp_eeprom sfp_eeprom;
342
343 /* External PHY support */
344 enum xgbe_mdio_mode phydev_mode;
345 struct mii_bus *mii;
346 struct phy_device *phydev;
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]347 enum xgbe_mdio_reset mdio_reset;
348 unsigned int mdio_reset_addr;
349 unsigned int mdio_reset_gpio;
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]350
351 /* Re-driver support */
352 unsigned int redrv;
353 unsigned int redrv_if;
354 unsigned int redrv_addr;
355 unsigned int redrv_lane;
356 unsigned int redrv_model;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]357};
358
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]359/* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
360static DEFINE_MUTEX(xgbe_phy_comm_lock);
361
362static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
363
364static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
365 struct xgbe_i2c_op *i2c_op)
366{
367 struct xgbe_phy_data *phy_data = pdata->phy_data;
368
369 /* Be sure we own the bus */
370 if (WARN_ON(!phy_data->comm_owned))
371 return -EIO;
372
373 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
374}
375
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]376static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
377 unsigned int val)
378{
379 struct xgbe_phy_data *phy_data = pdata->phy_data;
380 struct xgbe_i2c_op i2c_op;
381 __be16 *redrv_val;
382 u8 redrv_data[5], csum;
383 unsigned int i, retry;
384 int ret;
385
386 /* High byte of register contains read/write indicator */
387 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
388 redrv_data[1] = reg & 0xff;
389 redrv_val = (__be16 *)&redrv_data[2];
390 *redrv_val = cpu_to_be16(val);
391
392 /* Calculate 1 byte checksum */
393 csum = 0;
394 for (i = 0; i < 4; i++) {
395 csum += redrv_data[i];
396 if (redrv_data[i] > csum)
397 csum++;
398 }
399 redrv_data[4] = ~csum;
400
401 retry = 1;
402again1:
403 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
404 i2c_op.target = phy_data->redrv_addr;
405 i2c_op.len = sizeof(redrv_data);
406 i2c_op.buf = redrv_data;
407 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
408 if (ret) {
409 if ((ret == -EAGAIN) && retry--)
410 goto again1;
411
412 return ret;
413 }
414
415 retry = 1;
416again2:
417 i2c_op.cmd = XGBE_I2C_CMD_READ;
418 i2c_op.target = phy_data->redrv_addr;
419 i2c_op.len = 1;
420 i2c_op.buf = redrv_data;
421 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
422 if (ret) {
423 if ((ret == -EAGAIN) && retry--)
424 goto again2;
425
426 return ret;
427 }
428
429 if (redrv_data[0] != 0xff) {
430 netif_dbg(pdata, drv, pdata->netdev,
431 "Redriver write checksum error\n");
432 ret = -EIO;
433 }
434
435 return ret;
436}
437
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]438static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
439 void *val, unsigned int val_len)
440{
441 struct xgbe_i2c_op i2c_op;
442 int retry, ret;
443
444 retry = 1;
445again:
446 /* Write the specfied register */
447 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
448 i2c_op.target = target;
449 i2c_op.len = val_len;
450 i2c_op.buf = val;
451 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
452 if ((ret == -EAGAIN) && retry--)
453 goto again;
454
455 return ret;
456}
457
458static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
459 void *reg, unsigned int reg_len,
460 void *val, unsigned int val_len)
461{
462 struct xgbe_i2c_op i2c_op;
463 int retry, ret;
464
465 retry = 1;
466again1:
467 /* Set the specified register to read */
468 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
469 i2c_op.target = target;
470 i2c_op.len = reg_len;
471 i2c_op.buf = reg;
472 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
473 if (ret) {
474 if ((ret == -EAGAIN) && retry--)
475 goto again1;
476
477 return ret;
478 }
479
480 retry = 1;
481again2:
482 /* Read the specfied register */
483 i2c_op.cmd = XGBE_I2C_CMD_READ;
484 i2c_op.target = target;
485 i2c_op.len = val_len;
486 i2c_op.buf = val;
487 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
488 if ((ret == -EAGAIN) && retry--)
489 goto again2;
490
491 return ret;
492}
493
494static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
495{
496 struct xgbe_phy_data *phy_data = pdata->phy_data;
497 struct xgbe_i2c_op i2c_op;
498 u8 mux_channel;
499
500 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
501 return 0;
502
503 /* Select no mux channels */
504 mux_channel = 0;
505 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
506 i2c_op.target = phy_data->sfp_mux_address;
507 i2c_op.len = sizeof(mux_channel);
508 i2c_op.buf = &mux_channel;
509
510 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
511}
512
513static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
514{
515 struct xgbe_phy_data *phy_data = pdata->phy_data;
516 struct xgbe_i2c_op i2c_op;
517 u8 mux_channel;
518
519 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
520 return 0;
521
522 /* Select desired mux channel */
523 mux_channel = 1 << phy_data->sfp_mux_channel;
524 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
525 i2c_op.target = phy_data->sfp_mux_address;
526 i2c_op.len = sizeof(mux_channel);
527 i2c_op.buf = &mux_channel;
528
529 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
530}
531
532static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
533{
534 struct xgbe_phy_data *phy_data = pdata->phy_data;
535
536 phy_data->comm_owned = 0;
537
538 mutex_unlock(&xgbe_phy_comm_lock);
539}
540
541static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
542{
543 struct xgbe_phy_data *phy_data = pdata->phy_data;
544 unsigned long timeout;
545 unsigned int mutex_id;
546
547 if (phy_data->comm_owned)
548 return 0;
549
550 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
551 * the driver needs to take the software mutex and then the hardware
552 * mutexes before being able to use the busses.
553 */
554 mutex_lock(&xgbe_phy_comm_lock);
555
556 /* Clear the mutexes */
557 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
558 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
559
560 /* Mutex formats are the same for I2C and MDIO/GPIO */
561 mutex_id = 0;
562 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
563 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
564
565 timeout = jiffies + (5 * HZ);
566 while (time_before(jiffies, timeout)) {
567 /* Must be all zeroes in order to obtain the mutex */
568 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
569 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
570 usleep_range(100, 200);
571 continue;
572 }
573
574 /* Obtain the mutex */
575 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
576 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
577
578 phy_data->comm_owned = 1;
579 return 0;
580 }
581
582 mutex_unlock(&xgbe_phy_comm_lock);
583
584 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
585
586 return -ETIMEDOUT;
587}
588
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]589static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
590 int reg, u16 val)
591{
592 struct xgbe_phy_data *phy_data = pdata->phy_data;
593
594 if (reg & MII_ADDR_C45) {
595 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
596 return -ENOTSUPP;
597 } else {
598 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
599 return -ENOTSUPP;
600 }
601
602 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
603}
604
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]605static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
606{
607 __be16 *mii_val;
608 u8 mii_data[3];
609 int ret;
610
611 ret = xgbe_phy_sfp_get_mux(pdata);
612 if (ret)
613 return ret;
614
615 mii_data[0] = reg & 0xff;
616 mii_val = (__be16 *)&mii_data[1];
617 *mii_val = cpu_to_be16(val);
618
619 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
620 mii_data, sizeof(mii_data));
621
622 xgbe_phy_sfp_put_mux(pdata);
623
624 return ret;
625}
626
627static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
628{
629 struct xgbe_prv_data *pdata = mii->priv;
630 struct xgbe_phy_data *phy_data = pdata->phy_data;
631 int ret;
632
633 ret = xgbe_phy_get_comm_ownership(pdata);
634 if (ret)
635 return ret;
636
637 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
638 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]639 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
640 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]641 else
642 ret = -ENOTSUPP;
643
644 xgbe_phy_put_comm_ownership(pdata);
645
646 return ret;
647}
648
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]649static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
650 int reg)
651{
652 struct xgbe_phy_data *phy_data = pdata->phy_data;
653
654 if (reg & MII_ADDR_C45) {
655 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
656 return -ENOTSUPP;
657 } else {
658 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
659 return -ENOTSUPP;
660 }
661
662 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
663}
664
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]665static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
666{
667 __be16 mii_val;
668 u8 mii_reg;
669 int ret;
670
671 ret = xgbe_phy_sfp_get_mux(pdata);
672 if (ret)
673 return ret;
674
675 mii_reg = reg;
676 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
677 &mii_reg, sizeof(mii_reg),
678 &mii_val, sizeof(mii_val));
679 if (!ret)
680 ret = be16_to_cpu(mii_val);
681
682 xgbe_phy_sfp_put_mux(pdata);
683
684 return ret;
685}
686
687static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
688{
689 struct xgbe_prv_data *pdata = mii->priv;
690 struct xgbe_phy_data *phy_data = pdata->phy_data;
691 int ret;
692
693 ret = xgbe_phy_get_comm_ownership(pdata);
694 if (ret)
695 return ret;
696
697 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
698 ret = xgbe_phy_i2c_mii_read(pdata, reg);
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]699 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
700 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]701 else
702 ret = -ENOTSUPP;
703
704 xgbe_phy_put_comm_ownership(pdata);
705
706 return ret;
707}
708
709static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
710{
711 struct xgbe_phy_data *phy_data = pdata->phy_data;
712
713 if (phy_data->sfp_mod_absent) {
714 pdata->phy.speed = SPEED_UNKNOWN;
715 pdata->phy.duplex = DUPLEX_UNKNOWN;
716 pdata->phy.autoneg = AUTONEG_ENABLE;
717 pdata->phy.advertising = pdata->phy.supported;
718 }
719
720 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
721 pdata->phy.advertising &= ~ADVERTISED_TP;
722 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
723 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
724 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
725 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
726 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
727
728 switch (phy_data->sfp_base) {
729 case XGBE_SFP_BASE_1000_T:
730 case XGBE_SFP_BASE_1000_SX:
731 case XGBE_SFP_BASE_1000_LX:
732 case XGBE_SFP_BASE_1000_CX:
733 pdata->phy.speed = SPEED_UNKNOWN;
734 pdata->phy.duplex = DUPLEX_UNKNOWN;
735 pdata->phy.autoneg = AUTONEG_ENABLE;
736 pdata->phy.advertising |= ADVERTISED_Autoneg;
737 break;
738 case XGBE_SFP_BASE_10000_SR:
739 case XGBE_SFP_BASE_10000_LR:
740 case XGBE_SFP_BASE_10000_LRM:
741 case XGBE_SFP_BASE_10000_ER:
742 case XGBE_SFP_BASE_10000_CR:
743 default:
744 pdata->phy.speed = SPEED_10000;
745 pdata->phy.duplex = DUPLEX_FULL;
746 pdata->phy.autoneg = AUTONEG_DISABLE;
747 break;
748 }
749
750 switch (phy_data->sfp_base) {
751 case XGBE_SFP_BASE_1000_T:
752 case XGBE_SFP_BASE_1000_CX:
753 case XGBE_SFP_BASE_10000_CR:
754 pdata->phy.advertising |= ADVERTISED_TP;
755 break;
756 default:
757 pdata->phy.advertising |= ADVERTISED_FIBRE;
758 }
759
760 switch (phy_data->sfp_speed) {
761 case XGBE_SFP_SPEED_100_1000:
762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
763 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
764 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
765 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
766 break;
767 case XGBE_SFP_SPEED_1000:
768 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
769 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
770 break;
771 case XGBE_SFP_SPEED_10000:
772 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
773 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
774 break;
775 default:
776 /* Choose the fastest supported speed */
777 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
778 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
779 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
780 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
781 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
782 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
783 }
784}
785
786static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
787 enum xgbe_sfp_speed sfp_speed)
788{
789 u8 *sfp_base, min, max;
790
791 sfp_base = sfp_eeprom->base;
792
793 switch (sfp_speed) {
794 case XGBE_SFP_SPEED_1000:
795 min = XGBE_SFP_BASE_BR_1GBE_MIN;
796 max = XGBE_SFP_BASE_BR_1GBE_MAX;
797 break;
798 case XGBE_SFP_SPEED_10000:
799 min = XGBE_SFP_BASE_BR_10GBE_MIN;
800 max = XGBE_SFP_BASE_BR_10GBE_MAX;
801 break;
802 default:
803 return false;
804 }
805
806 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
807 (sfp_base[XGBE_SFP_BASE_BR] <= max));
808}
809
810static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
811{
812 struct xgbe_phy_data *phy_data = pdata->phy_data;
813
814 if (phy_data->phydev) {
815 phy_detach(phy_data->phydev);
816 phy_device_remove(phy_data->phydev);
817 phy_device_free(phy_data->phydev);
818 phy_data->phydev = NULL;
819 }
820}
821
822static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
823{
824 struct xgbe_phy_data *phy_data = pdata->phy_data;
825 unsigned int phy_id = phy_data->phydev->phy_id;
826
827 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
828 return false;
829
830 /* Enable Base-T AN */
831 phy_write(phy_data->phydev, 0x16, 0x0001);
832 phy_write(phy_data->phydev, 0x00, 0x9140);
833 phy_write(phy_data->phydev, 0x16, 0x0000);
834
835 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
836 phy_write(phy_data->phydev, 0x1b, 0x9084);
837 phy_write(phy_data->phydev, 0x09, 0x0e00);
838 phy_write(phy_data->phydev, 0x00, 0x8140);
839 phy_write(phy_data->phydev, 0x04, 0x0d01);
840 phy_write(phy_data->phydev, 0x00, 0x9140);
841
842 phy_data->phydev->supported = PHY_GBIT_FEATURES;
843 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
844 phy_data->phydev->advertising = phy_data->phydev->supported;
845
846 netif_dbg(pdata, drv, pdata->netdev,
847 "Finisar PHY quirk in place\n");
848
849 return true;
850}
851
852static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
853{
854 if (xgbe_phy_finisar_phy_quirks(pdata))
855 return;
856}
857
858static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
859{
860 struct xgbe_phy_data *phy_data = pdata->phy_data;
861 struct phy_device *phydev;
862 int ret;
863
864 /* If we already have a PHY, just return */
865 if (phy_data->phydev)
866 return 0;
867
868 /* Check for the use of an external PHY */
869 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
870 return 0;
871
872 /* For SFP, only use an external PHY if available */
873 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
874 !phy_data->sfp_phy_avail)
875 return 0;
876
877 /* Create and connect to the PHY device */
878 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
879 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
880 if (IS_ERR(phydev)) {
881 netdev_err(pdata->netdev, "get_phy_device failed\n");
882 return -ENODEV;
883 }
884 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
885 phydev->phy_id);
886
887 /*TODO: If c45, add request_module based on one of the MMD ids? */
888
889 ret = phy_device_register(phydev);
890 if (ret) {
891 netdev_err(pdata->netdev, "phy_device_register failed\n");
892 phy_device_free(phydev);
893 return ret;
894 }
895
896 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
897 PHY_INTERFACE_MODE_SGMII);
898 if (ret) {
899 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
900 phy_device_remove(phydev);
901 phy_device_free(phydev);
902 return ret;
903 }
904 phy_data->phydev = phydev;
905
906 xgbe_phy_external_phy_quirks(pdata);
907 phydev->advertising &= pdata->phy.advertising;
908
909 phy_start_aneg(phy_data->phydev);
910
911 return 0;
912}
913
914static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
915{
916 struct xgbe_phy_data *phy_data = pdata->phy_data;
917 int ret;
918
919 if (!phy_data->sfp_changed)
920 return;
921
922 phy_data->sfp_phy_avail = 0;
923
924 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
925 return;
926
927 /* Check access to the PHY by reading CTRL1 */
928 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
929 if (ret < 0)
930 return;
931
932 /* Successfully accessed the PHY */
933 phy_data->sfp_phy_avail = 1;
934}
935
936static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata)
937{
938 struct xgbe_phy_data *phy_data = pdata->phy_data;
939 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
940
941 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
942 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
943 return false;
944
945 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
946 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) {
947 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
948 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
949 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
950 if (phy_data->sfp_changed)
951 netif_dbg(pdata, drv, pdata->netdev,
952 "Bel-Fuse SFP quirk in place\n");
953 return true;
954 }
955
956 return false;
957}
958
959static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata)
960{
961 if (xgbe_phy_belfuse_parse_quirks(pdata))
962 return true;
963
964 return false;
965}
966
967static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
968{
969 struct xgbe_phy_data *phy_data = pdata->phy_data;
970 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
971 u8 *sfp_base;
972
973 sfp_base = sfp_eeprom->base;
974
975 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
976 return;
977
978 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
979 return;
980
981 if (xgbe_phy_sfp_parse_quirks(pdata))
982 return;
983
984 /* Assume ACTIVE cable unless told it is PASSIVE */
985 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
986 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
987 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
988 } else {
989 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
990 }
991
992 /* Determine the type of SFP */
993 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
994 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
995 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
996 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
997 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
998 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
999 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1000 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1001 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1002 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1003 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1004 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1005 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1006 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1007 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1008 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1009 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1010 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1011 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1012
1013 switch (phy_data->sfp_base) {
1014 case XGBE_SFP_BASE_1000_T:
1015 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1016 break;
1017 case XGBE_SFP_BASE_1000_SX:
1018 case XGBE_SFP_BASE_1000_LX:
1019 case XGBE_SFP_BASE_1000_CX:
1020 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1021 break;
1022 case XGBE_SFP_BASE_10000_SR:
1023 case XGBE_SFP_BASE_10000_LR:
1024 case XGBE_SFP_BASE_10000_LRM:
1025 case XGBE_SFP_BASE_10000_ER:
1026 case XGBE_SFP_BASE_10000_CR:
1027 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1028 break;
1029 default:
1030 break;
1031 }
1032}
1033
1034static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1035 struct xgbe_sfp_eeprom *sfp_eeprom)
1036{
1037 struct xgbe_sfp_ascii sfp_ascii;
1038 char *sfp_data = (char *)&sfp_ascii;
1039
1040 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1041 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1042 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1043 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1044 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1045 sfp_data);
1046
1047 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1048 XGBE_SFP_BASE_VENDOR_PN_LEN);
1049 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1050 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1051 sfp_data);
1052
1053 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1054 XGBE_SFP_BASE_VENDOR_REV_LEN);
1055 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1056 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1057 sfp_data);
1058
1059 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1060 XGBE_SFP_BASE_VENDOR_SN_LEN);
1061 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1062 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1063 sfp_data);
1064}
1065
1066static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1067{
1068 u8 cc;
1069
1070 for (cc = 0; len; buf++, len--)
1071 cc += *buf;
1072
1073 return (cc == cc_in) ? true : false;
1074}
1075
1076static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1077{
1078 struct xgbe_phy_data *phy_data = pdata->phy_data;
1079 struct xgbe_sfp_eeprom sfp_eeprom;
1080 u8 eeprom_addr;
1081 int ret;
1082
1083 ret = xgbe_phy_sfp_get_mux(pdata);
1084 if (ret) {
1085 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1086 return ret;
1087 }
1088
1089 /* Read the SFP serial ID eeprom */
1090 eeprom_addr = 0;
1091 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1092 &eeprom_addr, sizeof(eeprom_addr),
1093 &sfp_eeprom, sizeof(sfp_eeprom));
1094 if (ret) {
1095 netdev_err(pdata->netdev, "I2C error reading SFP EEPROM\n");
1096 goto put;
1097 }
1098
1099 /* Validate the contents read */
1100 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1101 sfp_eeprom.base,
1102 sizeof(sfp_eeprom.base) - 1)) {
1103 ret = -EINVAL;
1104 goto put;
1105 }
1106
1107 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1108 sfp_eeprom.extd,
1109 sizeof(sfp_eeprom.extd) - 1)) {
1110 ret = -EINVAL;
1111 goto put;
1112 }
1113
1114 /* Check for an added or changed SFP */
1115 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1116 phy_data->sfp_changed = 1;
1117
1118 if (netif_msg_drv(pdata))
1119 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1120
1121 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1122
1123 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) {
1124 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG];
1125
1126 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
1127 phy_data->sfp_diags = 1;
1128 }
1129
1130 xgbe_phy_free_phy_device(pdata);
1131 } else {
1132 phy_data->sfp_changed = 0;
1133 }
1134
1135put:
1136 xgbe_phy_sfp_put_mux(pdata);
1137
1138 return ret;
1139}
1140
1141static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1142{
1143 struct xgbe_phy_data *phy_data = pdata->phy_data;
1144 unsigned int gpio_input;
1145 u8 gpio_reg, gpio_ports[2];
1146 int ret;
1147
1148 /* Read the input port registers */
1149 gpio_reg = 0;
1150 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1151 &gpio_reg, sizeof(gpio_reg),
1152 gpio_ports, sizeof(gpio_ports));
1153 if (ret) {
1154 netdev_err(pdata->netdev, "I2C error reading SFP GPIOs\n");
1155 return;
1156 }
1157
1158 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
1159
1160 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) {
1161 /* No GPIO, just assume the module is present for now */
1162 phy_data->sfp_mod_absent = 0;
1163 } else {
1164 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
1165 phy_data->sfp_mod_absent = 0;
1166 }
1167
1168 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) &&
1169 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
1170 phy_data->sfp_rx_los = 1;
1171
1172 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) &&
1173 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
1174 phy_data->sfp_tx_fault = 1;
1175}
1176
1177static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1178{
1179 struct xgbe_phy_data *phy_data = pdata->phy_data;
1180
1181 xgbe_phy_free_phy_device(pdata);
1182
1183 phy_data->sfp_mod_absent = 1;
1184 phy_data->sfp_phy_avail = 0;
1185 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1186}
1187
1188static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1189{
1190 phy_data->sfp_rx_los = 0;
1191 phy_data->sfp_tx_fault = 0;
1192 phy_data->sfp_mod_absent = 1;
1193 phy_data->sfp_diags = 0;
1194 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1195 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1196 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1197}
1198
1199static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1200{
1201 struct xgbe_phy_data *phy_data = pdata->phy_data;
1202 int ret;
1203
1204 /* Reset the SFP signals and info */
1205 xgbe_phy_sfp_reset(phy_data);
1206
1207 ret = xgbe_phy_get_comm_ownership(pdata);
1208 if (ret)
1209 return;
1210
1211 /* Read the SFP signals and check for module presence */
1212 xgbe_phy_sfp_signals(pdata);
1213 if (phy_data->sfp_mod_absent) {
1214 xgbe_phy_sfp_mod_absent(pdata);
1215 goto put;
1216 }
1217
1218 ret = xgbe_phy_sfp_read_eeprom(pdata);
1219 if (ret) {
1220 /* Treat any error as if there isn't an SFP plugged in */
1221 xgbe_phy_sfp_reset(phy_data);
1222 xgbe_phy_sfp_mod_absent(pdata);
1223 goto put;
1224 }
1225
1226 xgbe_phy_sfp_parse_eeprom(pdata);
1227
1228 xgbe_phy_sfp_external_phy(pdata);
1229
1230put:
1231 xgbe_phy_sfp_phy_settings(pdata);
1232
1233 xgbe_phy_put_comm_ownership(pdata);
1234}
1235
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1236static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1237{
1238 struct xgbe_phy_data *phy_data = pdata->phy_data;
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1239 u16 lcl_adv = 0, rmt_adv = 0;
1240 u8 fc;
1241
1242 pdata->phy.tx_pause = 0;
1243 pdata->phy.rx_pause = 0;
1244
1245 if (!phy_data->phydev)
1246 return;
1247
1248 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1249 lcl_adv |= ADVERTISE_PAUSE_CAP;
1250 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1251 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1252
1253 if (phy_data->phydev->pause) {
1254 pdata->phy.lp_advertising |= ADVERTISED_Pause;
1255 rmt_adv |= LPA_PAUSE_CAP;
1256 }
1257 if (phy_data->phydev->asym_pause) {
1258 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1259 rmt_adv |= LPA_PAUSE_ASYM;
1260 }
1261
1262 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1263 if (fc & FLOW_CTRL_TX)
1264 pdata->phy.tx_pause = 1;
1265 if (fc & FLOW_CTRL_RX)
1266 pdata->phy.rx_pause = 1;
1267}
1268
1269static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1270{
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1271 enum xgbe_mode mode;
1272
1273 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1274 pdata->phy.lp_advertising |= ADVERTISED_TP;
1275
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1276 /* Use external PHY to determine flow control */
1277 if (pdata->phy.pause_autoneg)
1278 xgbe_phy_phydev_flowctrl(pdata);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1279
1280 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1281 case XGBE_SGMII_AN_LINK_SPEED_100:
1282 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1283 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
1284 mode = XGBE_MODE_SGMII_100;
1285 } else {
1286 /* Half-duplex not supported */
1287 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Half;
1288 mode = XGBE_MODE_UNKNOWN;
1289 }
1290 break;
1291 case XGBE_SGMII_AN_LINK_SPEED_1000:
1292 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1293 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1294 mode = XGBE_MODE_SGMII_1000;
1295 } else {
1296 /* Half-duplex not supported */
1297 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
1298 mode = XGBE_MODE_UNKNOWN;
1299 }
1300 break;
1301 default:
1302 mode = XGBE_MODE_UNKNOWN;
1303 }
1304
1305 return mode;
1306}
1307
1308static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1309{
1310 enum xgbe_mode mode;
1311 unsigned int ad_reg, lp_reg;
1312
1313 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1314 pdata->phy.lp_advertising |= ADVERTISED_FIBRE;
1315
1316 /* Compare Advertisement and Link Partner register */
1317 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1318 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1319 if (lp_reg & 0x100)
1320 pdata->phy.lp_advertising |= ADVERTISED_Pause;
1321 if (lp_reg & 0x80)
1322 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1323
1324 if (pdata->phy.pause_autoneg) {
1325 /* Set flow control based on auto-negotiation result */
1326 pdata->phy.tx_pause = 0;
1327 pdata->phy.rx_pause = 0;
1328
1329 if (ad_reg & lp_reg & 0x100) {
1330 pdata->phy.tx_pause = 1;
1331 pdata->phy.rx_pause = 1;
1332 } else if (ad_reg & lp_reg & 0x80) {
1333 if (ad_reg & 0x100)
1334 pdata->phy.rx_pause = 1;
1335 else if (lp_reg & 0x100)
1336 pdata->phy.tx_pause = 1;
1337 }
1338 }
1339
1340 if (lp_reg & 0x40)
1341 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
1342 if (lp_reg & 0x20)
1343 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1344
1345 /* Half duplex is not supported */
1346 ad_reg &= lp_reg;
1347 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1348
1349 return mode;
1350}
1351
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1352static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1353{
1354 struct xgbe_phy_data *phy_data = pdata->phy_data;
1355 enum xgbe_mode mode;
1356 unsigned int ad_reg, lp_reg;
1357
1358 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1359 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
1360
1361 /* Use external PHY to determine flow control */
1362 if (pdata->phy.pause_autoneg)
1363 xgbe_phy_phydev_flowctrl(pdata);
1364
1365 /* Compare Advertisement and Link Partner register 2 */
1366 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1367 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1368 if (lp_reg & 0x80)
1369 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
1370 if (lp_reg & 0x20)
1371 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
1372
1373 ad_reg &= lp_reg;
1374 if (ad_reg & 0x80) {
1375 switch (phy_data->port_mode) {
1376 case XGBE_PORT_MODE_BACKPLANE:
1377 mode = XGBE_MODE_KR;
1378 break;
1379 default:
1380 mode = XGBE_MODE_SFI;
1381 break;
1382 }
1383 } else if (ad_reg & 0x20) {
1384 switch (phy_data->port_mode) {
1385 case XGBE_PORT_MODE_BACKPLANE:
1386 mode = XGBE_MODE_KX_1000;
1387 break;
1388 case XGBE_PORT_MODE_1000BASE_X:
1389 mode = XGBE_MODE_X;
1390 break;
1391 case XGBE_PORT_MODE_SFP:
1392 switch (phy_data->sfp_base) {
1393 case XGBE_SFP_BASE_1000_T:
1394 if (phy_data->phydev &&
1395 (phy_data->phydev->speed == SPEED_100))
1396 mode = XGBE_MODE_SGMII_100;
1397 else
1398 mode = XGBE_MODE_SGMII_1000;
1399 break;
1400 case XGBE_SFP_BASE_1000_SX:
1401 case XGBE_SFP_BASE_1000_LX:
1402 case XGBE_SFP_BASE_1000_CX:
1403 default:
1404 mode = XGBE_MODE_X;
1405 break;
1406 }
1407 break;
1408 default:
1409 if (phy_data->phydev &&
1410 (phy_data->phydev->speed == SPEED_100))
1411 mode = XGBE_MODE_SGMII_100;
1412 else
1413 mode = XGBE_MODE_SGMII_1000;
1414 break;
1415 }
1416 } else {
1417 mode = XGBE_MODE_UNKNOWN;
1418 }
1419
1420 /* Compare Advertisement and Link Partner register 3 */
1421 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1422 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1423 if (lp_reg & 0xc000)
1424 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1425
1426 return mode;
1427}
1428
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1429static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1430{
1431 enum xgbe_mode mode;
1432 unsigned int ad_reg, lp_reg;
1433
1434 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1435 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
1436
1437 /* Compare Advertisement and Link Partner register 1 */
1438 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1439 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1440 if (lp_reg & 0x400)
1441 pdata->phy.lp_advertising |= ADVERTISED_Pause;
1442 if (lp_reg & 0x800)
1443 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1444
1445 if (pdata->phy.pause_autoneg) {
1446 /* Set flow control based on auto-negotiation result */
1447 pdata->phy.tx_pause = 0;
1448 pdata->phy.rx_pause = 0;
1449
1450 if (ad_reg & lp_reg & 0x400) {
1451 pdata->phy.tx_pause = 1;
1452 pdata->phy.rx_pause = 1;
1453 } else if (ad_reg & lp_reg & 0x800) {
1454 if (ad_reg & 0x400)
1455 pdata->phy.rx_pause = 1;
1456 else if (lp_reg & 0x400)
1457 pdata->phy.tx_pause = 1;
1458 }
1459 }
1460
1461 /* Compare Advertisement and Link Partner register 2 */
1462 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1463 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1464 if (lp_reg & 0x80)
1465 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
1466 if (lp_reg & 0x20)
1467 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
1468
1469 ad_reg &= lp_reg;
1470 if (ad_reg & 0x80)
1471 mode = XGBE_MODE_KR;
1472 else if (ad_reg & 0x20)
1473 mode = XGBE_MODE_KX_1000;
1474 else
1475 mode = XGBE_MODE_UNKNOWN;
1476
1477 /* Compare Advertisement and Link Partner register 3 */
1478 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1479 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1480 if (lp_reg & 0xc000)
1481 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1482
1483 return mode;
1484}
1485
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1486static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1487{
1488 switch (pdata->an_mode) {
1489 case XGBE_AN_MODE_CL73:
1490 return xgbe_phy_an73_outcome(pdata);
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1491 case XGBE_AN_MODE_CL73_REDRV:
1492 return xgbe_phy_an73_redrv_outcome(pdata);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1493 case XGBE_AN_MODE_CL37:
1494 return xgbe_phy_an37_outcome(pdata);
1495 case XGBE_AN_MODE_CL37_SGMII:
1496 return xgbe_phy_an37_sgmii_outcome(pdata);
1497 default:
1498 return XGBE_MODE_UNKNOWN;
1499 }
1500}
1501
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1502static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata)
1503{
1504 struct xgbe_phy_data *phy_data = pdata->phy_data;
1505 unsigned int advertising;
1506
1507 /* Without a re-driver, just return current advertising */
1508 if (!phy_data->redrv)
1509 return pdata->phy.advertising;
1510
1511 /* With the KR re-driver we need to advertise a single speed */
1512 advertising = pdata->phy.advertising;
1513 advertising &= ~ADVERTISED_1000baseKX_Full;
1514 advertising &= ~ADVERTISED_10000baseKR_Full;
1515
1516 switch (phy_data->port_mode) {
1517 case XGBE_PORT_MODE_BACKPLANE:
1518 advertising |= ADVERTISED_10000baseKR_Full;
1519 break;
1520 case XGBE_PORT_MODE_BACKPLANE_2500:
1521 advertising |= ADVERTISED_1000baseKX_Full;
1522 break;
1523 case XGBE_PORT_MODE_1000BASE_T:
1524 case XGBE_PORT_MODE_1000BASE_X:
1525 case XGBE_PORT_MODE_NBASE_T:
1526 advertising |= ADVERTISED_1000baseKX_Full;
1527 break;
1528 case XGBE_PORT_MODE_10GBASE_T:
1529 if (phy_data->phydev &&
1530 (phy_data->phydev->speed == SPEED_10000))
1531 advertising |= ADVERTISED_10000baseKR_Full;
1532 else
1533 advertising |= ADVERTISED_1000baseKX_Full;
1534 break;
1535 case XGBE_PORT_MODE_10GBASE_R:
1536 advertising |= ADVERTISED_10000baseKR_Full;
1537 break;
1538 case XGBE_PORT_MODE_SFP:
1539 switch (phy_data->sfp_base) {
1540 case XGBE_SFP_BASE_1000_T:
1541 case XGBE_SFP_BASE_1000_SX:
1542 case XGBE_SFP_BASE_1000_LX:
1543 case XGBE_SFP_BASE_1000_CX:
1544 advertising |= ADVERTISED_1000baseKX_Full;
1545 break;
1546 default:
1547 advertising |= ADVERTISED_10000baseKR_Full;
1548 break;
1549 }
1550 break;
1551 default:
1552 advertising |= ADVERTISED_10000baseKR_Full;
1553 break;
1554 }
1555
1556 return advertising;
1557}
1558
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1559static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1560{
1561 struct xgbe_phy_data *phy_data = pdata->phy_data;
1562 int ret;
1563
1564 ret = xgbe_phy_find_phy_device(pdata);
1565 if (ret)
1566 return ret;
1567
1568 if (!phy_data->phydev)
1569 return 0;
1570
1571 phy_data->phydev->autoneg = pdata->phy.autoneg;
1572 phy_data->phydev->advertising = phy_data->phydev->supported &
1573 pdata->phy.advertising;
1574
1575 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1576 phy_data->phydev->speed = pdata->phy.speed;
1577 phy_data->phydev->duplex = pdata->phy.duplex;
1578 }
1579
1580 ret = phy_start_aneg(phy_data->phydev);
1581
1582 return ret;
1583}
1584
1585static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1586{
1587 switch (phy_data->sfp_base) {
1588 case XGBE_SFP_BASE_1000_T:
1589 return XGBE_AN_MODE_CL37_SGMII;
1590 case XGBE_SFP_BASE_1000_SX:
1591 case XGBE_SFP_BASE_1000_LX:
1592 case XGBE_SFP_BASE_1000_CX:
1593 return XGBE_AN_MODE_CL37;
1594 default:
1595 return XGBE_AN_MODE_NONE;
1596 }
1597}
1598
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1599static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1600{
1601 struct xgbe_phy_data *phy_data = pdata->phy_data;
1602
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1603 /* A KR re-driver will always require CL73 AN */
1604 if (phy_data->redrv)
1605 return XGBE_AN_MODE_CL73_REDRV;
1606
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1607 switch (phy_data->port_mode) {
1608 case XGBE_PORT_MODE_BACKPLANE:
1609 return XGBE_AN_MODE_CL73;
1610 case XGBE_PORT_MODE_BACKPLANE_2500:
1611 return XGBE_AN_MODE_NONE;
1612 case XGBE_PORT_MODE_1000BASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]1613 return XGBE_AN_MODE_CL37_SGMII;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1614 case XGBE_PORT_MODE_1000BASE_X:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]1615 return XGBE_AN_MODE_CL37;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1616 case XGBE_PORT_MODE_NBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]1617 return XGBE_AN_MODE_CL37_SGMII;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1618 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]1619 return XGBE_AN_MODE_CL73;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1620 case XGBE_PORT_MODE_10GBASE_R:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1621 return XGBE_AN_MODE_NONE;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1622 case XGBE_PORT_MODE_SFP:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1623 return xgbe_phy_an_sfp_mode(phy_data);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1624 default:
1625 return XGBE_AN_MODE_NONE;
1626 }
1627}
1628
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1629static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1630 enum xgbe_phy_redrv_mode mode)
1631{
1632 struct xgbe_phy_data *phy_data = pdata->phy_data;
1633 u16 redrv_reg, redrv_val;
1634
1635 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1636 redrv_val = (u16)mode;
1637
1638 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1639 redrv_reg, redrv_val);
1640}
1641
1642static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1643 enum xgbe_phy_redrv_mode mode)
1644{
1645 struct xgbe_phy_data *phy_data = pdata->phy_data;
1646 unsigned int redrv_reg;
1647 int ret;
1648
1649 /* Calculate the register to write */
1650 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1651
1652 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1653
1654 return ret;
1655}
1656
1657static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1658{
1659 struct xgbe_phy_data *phy_data = pdata->phy_data;
1660 enum xgbe_phy_redrv_mode mode;
1661 int ret;
1662
1663 if (!phy_data->redrv)
1664 return;
1665
1666 mode = XGBE_PHY_REDRV_MODE_CX;
1667 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1668 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1669 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1670 mode = XGBE_PHY_REDRV_MODE_SR;
1671
1672 ret = xgbe_phy_get_comm_ownership(pdata);
1673 if (ret)
1674 return;
1675
1676 if (phy_data->redrv_if)
1677 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1678 else
1679 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1680
1681 xgbe_phy_put_comm_ownership(pdata);
1682}
1683
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1684static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
1685{
1686 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1687 return;
1688
1689 /* Log if a previous command did not complete */
1690 netif_dbg(pdata, link, pdata->netdev,
1691 "firmware mailbox not ready for command\n");
1692}
1693
1694static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
1695{
1696 unsigned int wait;
1697
1698 /* Wait for command to complete */
1699 wait = XGBE_RATECHANGE_COUNT;
1700 while (wait--) {
1701 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1702 return;
1703
1704 usleep_range(1000, 2000);
1705 }
1706
1707 netif_dbg(pdata, link, pdata->netdev,
1708 "firmware mailbox command did not complete\n");
1709}
1710
1711static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1712{
1713 unsigned int s0;
1714
1715 xgbe_phy_start_ratechange(pdata);
1716
1717 /* Receiver Reset Cycle */
1718 s0 = 0;
1719 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
1720 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1721
1722 /* Call FW to make the change */
1723 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1724 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1725 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1726
1727 xgbe_phy_complete_ratechange(pdata);
1728
1729 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1730}
1731
1732static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1733{
1734 struct xgbe_phy_data *phy_data = pdata->phy_data;
1735
1736 xgbe_phy_start_ratechange(pdata);
1737
1738 /* Call FW to make the change */
1739 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
1740 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1741 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1742
1743 xgbe_phy_complete_ratechange(pdata);
1744
1745 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
1746
1747 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
1748}
1749
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1750static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
1751{
1752 struct xgbe_phy_data *phy_data = pdata->phy_data;
1753 unsigned int s0;
1754
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1755 xgbe_phy_set_redrv_mode(pdata);
1756
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1757 xgbe_phy_start_ratechange(pdata);
1758
1759 /* 10G/SFI */
1760 s0 = 0;
1761 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
1762 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
1763 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1764 } else {
1765 if (phy_data->sfp_cable_len <= 1)
1766 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1767 else if (phy_data->sfp_cable_len <= 3)
1768 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1769 else
1770 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1771 }
1772
1773 /* Call FW to make the change */
1774 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1775 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1776 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1777
1778 xgbe_phy_complete_ratechange(pdata);
1779
1780 phy_data->cur_mode = XGBE_MODE_SFI;
1781
1782 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
1783}
1784
1785static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
1786{
1787 struct xgbe_phy_data *phy_data = pdata->phy_data;
1788 unsigned int s0;
1789
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1790 xgbe_phy_set_redrv_mode(pdata);
1791
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1792 xgbe_phy_start_ratechange(pdata);
1793
1794 /* 1G/X */
1795 s0 = 0;
1796 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1797 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1798
1799 /* Call FW to make the change */
1800 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1801 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1802 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1803
1804 xgbe_phy_complete_ratechange(pdata);
1805
1806 phy_data->cur_mode = XGBE_MODE_X;
1807
1808 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
1809}
1810
1811static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
1812{
1813 struct xgbe_phy_data *phy_data = pdata->phy_data;
1814 unsigned int s0;
1815
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1816 xgbe_phy_set_redrv_mode(pdata);
1817
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1818 xgbe_phy_start_ratechange(pdata);
1819
1820 /* 1G/SGMII */
1821 s0 = 0;
1822 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1823 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1824
1825 /* Call FW to make the change */
1826 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1827 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1828 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1829
1830 xgbe_phy_complete_ratechange(pdata);
1831
1832 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
1833
1834 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
1835}
1836
1837static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
1838{
1839 struct xgbe_phy_data *phy_data = pdata->phy_data;
1840 unsigned int s0;
1841
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1842 xgbe_phy_set_redrv_mode(pdata);
1843
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1844 xgbe_phy_start_ratechange(pdata);
1845
1846 /* 1G/SGMII */
1847 s0 = 0;
1848 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1849 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1850
1851 /* Call FW to make the change */
1852 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1853 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1854 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1855
1856 xgbe_phy_complete_ratechange(pdata);
1857
1858 phy_data->cur_mode = XGBE_MODE_SGMII_100;
1859
1860 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
1861}
1862
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1863static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
1864{
1865 struct xgbe_phy_data *phy_data = pdata->phy_data;
1866 unsigned int s0;
1867
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1868 xgbe_phy_set_redrv_mode(pdata);
1869
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1870 xgbe_phy_start_ratechange(pdata);
1871
1872 /* 10G/KR */
1873 s0 = 0;
1874 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
1875 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1876
1877 /* Call FW to make the change */
1878 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1879 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1880 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1881
1882 xgbe_phy_complete_ratechange(pdata);
1883
1884 phy_data->cur_mode = XGBE_MODE_KR;
1885
1886 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
1887}
1888
1889static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
1890{
1891 struct xgbe_phy_data *phy_data = pdata->phy_data;
1892 unsigned int s0;
1893
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1894 xgbe_phy_set_redrv_mode(pdata);
1895
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1896 xgbe_phy_start_ratechange(pdata);
1897
1898 /* 2.5G/KX */
1899 s0 = 0;
1900 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
1901 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1902
1903 /* Call FW to make the change */
1904 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1905 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1906 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1907
1908 xgbe_phy_complete_ratechange(pdata);
1909
1910 phy_data->cur_mode = XGBE_MODE_KX_2500;
1911
1912 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
1913}
1914
1915static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
1916{
1917 struct xgbe_phy_data *phy_data = pdata->phy_data;
1918 unsigned int s0;
1919
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]1920 xgbe_phy_set_redrv_mode(pdata);
1921
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1922 xgbe_phy_start_ratechange(pdata);
1923
1924 /* 1G/KX */
1925 s0 = 0;
1926 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1927 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1928
1929 /* Call FW to make the change */
1930 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1931 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1932 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1933
1934 xgbe_phy_complete_ratechange(pdata);
1935
1936 phy_data->cur_mode = XGBE_MODE_KX_1000;
1937
1938 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
1939}
1940
1941static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
1942{
1943 struct xgbe_phy_data *phy_data = pdata->phy_data;
1944
1945 return phy_data->cur_mode;
1946}
1947
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]1948static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
1949{
1950 struct xgbe_phy_data *phy_data = pdata->phy_data;
1951
1952 /* No switching if not 10GBase-T */
1953 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
1954 return xgbe_phy_cur_mode(pdata);
1955
1956 switch (xgbe_phy_cur_mode(pdata)) {
1957 case XGBE_MODE_SGMII_100:
1958 case XGBE_MODE_SGMII_1000:
1959 return XGBE_MODE_KR;
1960 case XGBE_MODE_KR:
1961 default:
1962 return XGBE_MODE_SGMII_1000;
1963 }
1964}
1965
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1966static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
1967{
1968 return XGBE_MODE_KX_2500;
1969}
1970
1971static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
1972{
1973 /* If we are in KR switch to KX, and vice-versa */
1974 switch (xgbe_phy_cur_mode(pdata)) {
1975 case XGBE_MODE_KX_1000:
1976 return XGBE_MODE_KR;
1977 case XGBE_MODE_KR:
1978 default:
1979 return XGBE_MODE_KX_1000;
1980 }
1981}
1982
1983static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
1984{
1985 struct xgbe_phy_data *phy_data = pdata->phy_data;
1986
1987 switch (phy_data->port_mode) {
1988 case XGBE_PORT_MODE_BACKPLANE:
1989 return xgbe_phy_switch_bp_mode(pdata);
1990 case XGBE_PORT_MODE_BACKPLANE_2500:
1991 return xgbe_phy_switch_bp_2500_mode(pdata);
1992 case XGBE_PORT_MODE_1000BASE_T:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1993 case XGBE_PORT_MODE_NBASE_T:
1994 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]1995 return xgbe_phy_switch_baset_mode(pdata);
1996 case XGBE_PORT_MODE_1000BASE_X:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]1997 case XGBE_PORT_MODE_10GBASE_R:
1998 case XGBE_PORT_MODE_SFP:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]1999 /* No switching, so just return current mode */
2000 return xgbe_phy_cur_mode(pdata);
2001 default:
2002 return XGBE_MODE_UNKNOWN;
2003 }
2004}
2005
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2006static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2007 int speed)
2008{
2009 switch (speed) {
2010 case SPEED_1000:
2011 return XGBE_MODE_X;
2012 case SPEED_10000:
2013 return XGBE_MODE_KR;
2014 default:
2015 return XGBE_MODE_UNKNOWN;
2016 }
2017}
2018
2019static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2020 int speed)
2021{
2022 switch (speed) {
2023 case SPEED_100:
2024 return XGBE_MODE_SGMII_100;
2025 case SPEED_1000:
2026 return XGBE_MODE_SGMII_1000;
2027 case SPEED_10000:
2028 return XGBE_MODE_KR;
2029 default:
2030 return XGBE_MODE_UNKNOWN;
2031 }
2032}
2033
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2034static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2035 int speed)
2036{
2037 switch (speed) {
2038 case SPEED_100:
2039 return XGBE_MODE_SGMII_100;
2040 case SPEED_1000:
2041 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2042 return XGBE_MODE_SGMII_1000;
2043 else
2044 return XGBE_MODE_X;
2045 case SPEED_10000:
2046 case SPEED_UNKNOWN:
2047 return XGBE_MODE_SFI;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2048 default:
2049 return XGBE_MODE_UNKNOWN;
2050 }
2051}
2052
2053static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2054{
2055 switch (speed) {
2056 case SPEED_2500:
2057 return XGBE_MODE_KX_2500;
2058 default:
2059 return XGBE_MODE_UNKNOWN;
2060 }
2061}
2062
2063static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2064{
2065 switch (speed) {
2066 case SPEED_1000:
2067 return XGBE_MODE_KX_1000;
2068 case SPEED_10000:
2069 return XGBE_MODE_KR;
2070 default:
2071 return XGBE_MODE_UNKNOWN;
2072 }
2073}
2074
2075static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2076 int speed)
2077{
2078 struct xgbe_phy_data *phy_data = pdata->phy_data;
2079
2080 switch (phy_data->port_mode) {
2081 case XGBE_PORT_MODE_BACKPLANE:
2082 return xgbe_phy_get_bp_mode(speed);
2083 case XGBE_PORT_MODE_BACKPLANE_2500:
2084 return xgbe_phy_get_bp_2500_mode(speed);
2085 case XGBE_PORT_MODE_1000BASE_T:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2086 case XGBE_PORT_MODE_NBASE_T:
2087 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2088 return xgbe_phy_get_baset_mode(phy_data, speed);
2089 case XGBE_PORT_MODE_1000BASE_X:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2090 case XGBE_PORT_MODE_10GBASE_R:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2091 return xgbe_phy_get_basex_mode(phy_data, speed);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2092 case XGBE_PORT_MODE_SFP:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2093 return xgbe_phy_get_sfp_mode(phy_data, speed);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2094 default:
2095 return XGBE_MODE_UNKNOWN;
2096 }
2097}
2098
2099static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2100{
2101 switch (mode) {
2102 case XGBE_MODE_KX_1000:
2103 xgbe_phy_kx_1000_mode(pdata);
2104 break;
2105 case XGBE_MODE_KX_2500:
2106 xgbe_phy_kx_2500_mode(pdata);
2107 break;
2108 case XGBE_MODE_KR:
2109 xgbe_phy_kr_mode(pdata);
2110 break;
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2111 case XGBE_MODE_SGMII_100:
2112 xgbe_phy_sgmii_100_mode(pdata);
2113 break;
2114 case XGBE_MODE_SGMII_1000:
2115 xgbe_phy_sgmii_1000_mode(pdata);
2116 break;
2117 case XGBE_MODE_X:
2118 xgbe_phy_x_mode(pdata);
2119 break;
2120 case XGBE_MODE_SFI:
2121 xgbe_phy_sfi_mode(pdata);
2122 break;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2123 default:
2124 break;
2125 }
2126}
2127
2128static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2129 enum xgbe_mode mode, u32 advert)
2130{
2131 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2132 if (pdata->phy.advertising & advert)
2133 return true;
2134 } else {
2135 enum xgbe_mode cur_mode;
2136
2137 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2138 if (cur_mode == mode)
2139 return true;
2140 }
2141
2142 return false;
2143}
2144
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2145static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2146 enum xgbe_mode mode)
2147{
2148 switch (mode) {
2149 case XGBE_MODE_X:
2150 return xgbe_phy_check_mode(pdata, mode,
2151 ADVERTISED_1000baseT_Full);
2152 case XGBE_MODE_KR:
2153 return xgbe_phy_check_mode(pdata, mode,
2154 ADVERTISED_10000baseT_Full);
2155 default:
2156 return false;
2157 }
2158}
2159
2160static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2161 enum xgbe_mode mode)
2162{
2163 switch (mode) {
2164 case XGBE_MODE_SGMII_100:
2165 return xgbe_phy_check_mode(pdata, mode,
2166 ADVERTISED_100baseT_Full);
2167 case XGBE_MODE_SGMII_1000:
2168 return xgbe_phy_check_mode(pdata, mode,
2169 ADVERTISED_1000baseT_Full);
2170 case XGBE_MODE_KR:
2171 return xgbe_phy_check_mode(pdata, mode,
2172 ADVERTISED_10000baseT_Full);
2173 default:
2174 return false;
2175 }
2176}
2177
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2178static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2179 enum xgbe_mode mode)
2180{
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2182
2183 switch (mode) {
2184 case XGBE_MODE_X:
2185 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2186 return false;
2187 return xgbe_phy_check_mode(pdata, mode,
2188 ADVERTISED_1000baseT_Full);
2189 case XGBE_MODE_SGMII_100:
2190 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2191 return false;
2192 return xgbe_phy_check_mode(pdata, mode,
2193 ADVERTISED_100baseT_Full);
2194 case XGBE_MODE_SGMII_1000:
2195 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2196 return false;
2197 return xgbe_phy_check_mode(pdata, mode,
2198 ADVERTISED_1000baseT_Full);
2199 case XGBE_MODE_SFI:
2200 return xgbe_phy_check_mode(pdata, mode,
2201 ADVERTISED_10000baseT_Full);
2202 default:
2203 return false;
2204 }
2205}
2206
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2207static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2208 enum xgbe_mode mode)
2209{
2210 switch (mode) {
2211 case XGBE_MODE_KX_2500:
2212 return xgbe_phy_check_mode(pdata, mode,
2213 ADVERTISED_2500baseX_Full);
2214 default:
2215 return false;
2216 }
2217}
2218
2219static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2220 enum xgbe_mode mode)
2221{
2222 switch (mode) {
2223 case XGBE_MODE_KX_1000:
2224 return xgbe_phy_check_mode(pdata, mode,
2225 ADVERTISED_1000baseKX_Full);
2226 case XGBE_MODE_KR:
2227 return xgbe_phy_check_mode(pdata, mode,
2228 ADVERTISED_10000baseKR_Full);
2229 default:
2230 return false;
2231 }
2232}
2233
2234static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2235{
2236 struct xgbe_phy_data *phy_data = pdata->phy_data;
2237
2238 switch (phy_data->port_mode) {
2239 case XGBE_PORT_MODE_BACKPLANE:
2240 return xgbe_phy_use_bp_mode(pdata, mode);
2241 case XGBE_PORT_MODE_BACKPLANE_2500:
2242 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2243 case XGBE_PORT_MODE_1000BASE_T:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2244 case XGBE_PORT_MODE_NBASE_T:
2245 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2246 return xgbe_phy_use_baset_mode(pdata, mode);
2247 case XGBE_PORT_MODE_1000BASE_X:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2248 case XGBE_PORT_MODE_10GBASE_R:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2249 return xgbe_phy_use_basex_mode(pdata, mode);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2250 case XGBE_PORT_MODE_SFP:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2251 return xgbe_phy_use_sfp_mode(pdata, mode);
2252 default:
2253 return false;
2254 }
2255}
2256
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2257static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2258 int speed)
2259{
2260 switch (speed) {
2261 case SPEED_1000:
2262 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2263 case SPEED_10000:
2264 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2265 default:
2266 return false;
2267 }
2268}
2269
2270static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2271 int speed)
2272{
2273 switch (speed) {
2274 case SPEED_100:
2275 case SPEED_1000:
2276 return true;
2277 case SPEED_10000:
2278 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2279 default:
2280 return false;
2281 }
2282}
2283
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2284static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2285 int speed)
2286{
2287 switch (speed) {
2288 case SPEED_100:
2289 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2290 case SPEED_1000:
2291 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2292 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2293 case SPEED_10000:
2294 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2295 default:
2296 return false;
2297 }
2298}
2299
2300static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2301{
2302 switch (speed) {
2303 case SPEED_2500:
2304 return true;
2305 default:
2306 return false;
2307 }
2308}
2309
2310static bool xgbe_phy_valid_speed_bp_mode(int speed)
2311{
2312 switch (speed) {
2313 case SPEED_1000:
2314 case SPEED_10000:
2315 return true;
2316 default:
2317 return false;
2318 }
2319}
2320
2321static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2322{
2323 struct xgbe_phy_data *phy_data = pdata->phy_data;
2324
2325 switch (phy_data->port_mode) {
2326 case XGBE_PORT_MODE_BACKPLANE:
2327 return xgbe_phy_valid_speed_bp_mode(speed);
2328 case XGBE_PORT_MODE_BACKPLANE_2500:
2329 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2330 case XGBE_PORT_MODE_1000BASE_T:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2331 case XGBE_PORT_MODE_NBASE_T:
2332 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2333 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2334 case XGBE_PORT_MODE_1000BASE_X:
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2335 case XGBE_PORT_MODE_10GBASE_R:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2336 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2337 case XGBE_PORT_MODE_SFP:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2338 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2339 default:
2340 return false;
2341 }
2342}
2343
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2344static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2345{
2346 struct xgbe_phy_data *phy_data = pdata->phy_data;
Lendacky, Thomas8c5385c2016-11-14 16:39:16 -0600[diff] [blame]2347 unsigned int reg;
2348 int ret;
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2349
2350 *an_restart = 0;
2351
2352 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2353 /* Check SFP signals */
2354 xgbe_phy_sfp_detect(pdata);
2355
2356 if (phy_data->sfp_changed) {
2357 *an_restart = 1;
2358 return 0;
2359 }
2360
2361 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2362 return 0;
2363 }
2364
2365 if (phy_data->phydev) {
2366 /* Check external PHY */
2367 ret = phy_read_status(phy_data->phydev);
2368 if (ret < 0)
2369 return 0;
2370
2371 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2372 !phy_aneg_done(phy_data->phydev))
2373 return 0;
2374
2375 if (!phy_data->phydev->link)
2376 return 0;
2377 }
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2378
2379 /* Link status is latched low, so read once to clear
2380 * and then read again to get current state
2381 */
2382 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2383 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2384 if (reg & MDIO_STAT1_LSTATUS)
2385 return 1;
2386
2387 /* No link, attempt a receiver reset cycle */
2388 if (phy_data->rrc_count++) {
2389 phy_data->rrc_count = 0;
2390 xgbe_phy_rrc(pdata);
2391 }
2392
2393 return 0;
2394}
2395
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2396static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2397{
2398 struct xgbe_phy_data *phy_data = pdata->phy_data;
2399 unsigned int reg;
2400
2401 reg = XP_IOREAD(pdata, XP_PROP_3);
2402
2403 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2404 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
2405
2406 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
2407
2408 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
2409 GPIO_RX_LOS);
2410 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
2411 GPIO_TX_FAULT);
2412 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
2413 GPIO_MOD_ABS);
2414 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
2415 GPIO_RATE_SELECT);
2416
2417 if (netif_msg_probe(pdata)) {
2418 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2419 phy_data->sfp_gpio_address);
2420 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2421 phy_data->sfp_gpio_mask);
2422 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2423 phy_data->sfp_gpio_rx_los);
2424 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2425 phy_data->sfp_gpio_tx_fault);
2426 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2427 phy_data->sfp_gpio_mod_absent);
2428 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2429 phy_data->sfp_gpio_rate_select);
2430 }
2431}
2432
2433static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2434{
2435 struct xgbe_phy_data *phy_data = pdata->phy_data;
2436 unsigned int reg, mux_addr_hi, mux_addr_lo;
2437
2438 reg = XP_IOREAD(pdata, XP_PROP_4);
2439
2440 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
2441 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
2442 if (mux_addr_lo == XGBE_SFP_DIRECT)
2443 return;
2444
2445 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2446 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2447 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
2448
2449 if (netif_msg_probe(pdata)) {
2450 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2451 phy_data->sfp_mux_address);
2452 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2453 phy_data->sfp_mux_channel);
2454 }
2455}
2456
2457static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2458{
2459 xgbe_phy_sfp_comm_setup(pdata);
2460 xgbe_phy_sfp_gpio_setup(pdata);
2461}
2462
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2463static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2464{
2465 struct xgbe_phy_data *phy_data = pdata->phy_data;
2466 unsigned int ret;
2467
2468 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2469 if (ret)
2470 return ret;
2471
2472 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2473
2474 return ret;
2475}
2476
2477static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2478{
2479 struct xgbe_phy_data *phy_data = pdata->phy_data;
2480 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2481 int ret;
2482
2483 /* Read the output port registers */
2484 gpio_reg = 2;
2485 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2486 &gpio_reg, sizeof(gpio_reg),
2487 gpio_ports, sizeof(gpio_ports));
2488 if (ret)
2489 return ret;
2490
2491 /* Prepare to write the GPIO data */
2492 gpio_data[0] = 2;
2493 gpio_data[1] = gpio_ports[0];
2494 gpio_data[2] = gpio_ports[1];
2495
2496 /* Set the GPIO pin */
2497 if (phy_data->mdio_reset_gpio < 8)
2498 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2499 else
2500 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2501
2502 /* Write the output port registers */
2503 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2504 gpio_data, sizeof(gpio_data));
2505 if (ret)
2506 return ret;
2507
2508 /* Clear the GPIO pin */
2509 if (phy_data->mdio_reset_gpio < 8)
2510 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2511 else
2512 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2513
2514 /* Write the output port registers */
2515 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2516 gpio_data, sizeof(gpio_data));
2517
2518 return ret;
2519}
2520
2521static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2522{
2523 struct xgbe_phy_data *phy_data = pdata->phy_data;
2524 int ret;
2525
2526 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2527 return 0;
2528
2529 ret = xgbe_phy_get_comm_ownership(pdata);
2530 if (ret)
2531 return ret;
2532
2533 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2534 ret = xgbe_phy_i2c_mdio_reset(pdata);
2535 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2536 ret = xgbe_phy_int_mdio_reset(pdata);
2537
2538 xgbe_phy_put_comm_ownership(pdata);
2539
2540 return ret;
2541}
2542
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]2543static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2544{
2545 if (!phy_data->redrv)
2546 return false;
2547
2548 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2549 return true;
2550
2551 switch (phy_data->redrv_model) {
2552 case XGBE_PHY_REDRV_MODEL_4223:
2553 if (phy_data->redrv_lane > 3)
2554 return true;
2555 break;
2556 case XGBE_PHY_REDRV_MODEL_4227:
2557 if (phy_data->redrv_lane > 1)
2558 return true;
2559 break;
2560 default:
2561 return true;
2562 }
2563
2564 return false;
2565}
2566
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2567static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2568{
2569 struct xgbe_phy_data *phy_data = pdata->phy_data;
2570 unsigned int reg;
2571
2572 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2573 return 0;
2574
2575 reg = XP_IOREAD(pdata, XP_PROP_3);
2576 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
2577 switch (phy_data->mdio_reset) {
2578 case XGBE_MDIO_RESET_NONE:
2579 case XGBE_MDIO_RESET_I2C_GPIO:
2580 case XGBE_MDIO_RESET_INT_GPIO:
2581 break;
2582 default:
2583 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2584 phy_data->mdio_reset);
2585 return -EINVAL;
2586 }
2587
2588 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2589 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2590 XP_GET_BITS(reg, XP_PROP_3,
2591 MDIO_RESET_I2C_ADDR);
2592 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2593 MDIO_RESET_I2C_GPIO);
2594 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2595 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2596 MDIO_RESET_INT_GPIO);
2597 }
2598
2599 return 0;
2600}
2601
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2602static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2603{
2604 struct xgbe_phy_data *phy_data = pdata->phy_data;
2605
2606 switch (phy_data->port_mode) {
2607 case XGBE_PORT_MODE_BACKPLANE:
2608 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2609 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2610 return false;
2611 break;
2612 case XGBE_PORT_MODE_BACKPLANE_2500:
2613 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2614 return false;
2615 break;
2616 case XGBE_PORT_MODE_1000BASE_T:
2617 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2618 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2619 return false;
2620 break;
2621 case XGBE_PORT_MODE_1000BASE_X:
2622 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2623 return false;
2624 break;
2625 case XGBE_PORT_MODE_NBASE_T:
2626 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2627 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2628 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2629 return false;
2630 break;
2631 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2632 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2633 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2634 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2635 return false;
2636 break;
2637 case XGBE_PORT_MODE_10GBASE_R:
2638 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2639 return false;
2640 break;
2641 case XGBE_PORT_MODE_SFP:
2642 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2643 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2644 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2645 return false;
2646 break;
2647 default:
2648 break;
2649 }
2650
2651 return true;
2652}
2653
2654static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2655{
2656 struct xgbe_phy_data *phy_data = pdata->phy_data;
2657
2658 switch (phy_data->port_mode) {
2659 case XGBE_PORT_MODE_BACKPLANE:
2660 case XGBE_PORT_MODE_BACKPLANE_2500:
2661 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2662 return false;
2663 break;
2664 case XGBE_PORT_MODE_1000BASE_T:
2665 case XGBE_PORT_MODE_1000BASE_X:
2666 case XGBE_PORT_MODE_NBASE_T:
2667 case XGBE_PORT_MODE_10GBASE_T:
2668 case XGBE_PORT_MODE_10GBASE_R:
2669 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2670 return false;
2671 break;
2672 case XGBE_PORT_MODE_SFP:
2673 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2674 return false;
2675 break;
2676 default:
2677 break;
2678 }
2679
2680 return true;
2681}
2682
2683static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2684{
2685 unsigned int reg;
2686
2687 reg = XP_IOREAD(pdata, XP_PROP_0);
2688 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
2689 return false;
2690 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
2691 return false;
2692
2693 return true;
2694}
2695
2696static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2697{
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2698 struct xgbe_phy_data *phy_data = pdata->phy_data;
2699
2700 /* If we have an external PHY, free it */
2701 xgbe_phy_free_phy_device(pdata);
2702
2703 /* Reset SFP data */
2704 xgbe_phy_sfp_reset(phy_data);
2705 xgbe_phy_sfp_mod_absent(pdata);
2706
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2707 /* Power off the PHY */
2708 xgbe_phy_power_off(pdata);
Lendacky, Thomas5ab1dcd2016-11-10 17:10:36 -0600[diff] [blame]2709
2710 /* Stop the I2C controller */
2711 pdata->i2c_if.i2c_stop(pdata);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2712}
2713
2714static int xgbe_phy_start(struct xgbe_prv_data *pdata)
2715{
2716 struct xgbe_phy_data *phy_data = pdata->phy_data;
Lendacky, Thomas5ab1dcd2016-11-10 17:10:36 -0600[diff] [blame]2717 int ret;
2718
2719 /* Start the I2C controller */
2720 ret = pdata->i2c_if.i2c_start(pdata);
2721 if (ret)
2722 return ret;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2723
2724 /* Start in highest supported mode */
2725 xgbe_phy_set_mode(pdata, phy_data->start_mode);
2726
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2727 /* After starting the I2C controller, we can check for an SFP */
2728 switch (phy_data->port_mode) {
2729 case XGBE_PORT_MODE_SFP:
2730 xgbe_phy_sfp_detect(pdata);
2731 break;
2732 default:
2733 break;
2734 }
2735
2736 /* If we have an external PHY, start it */
2737 ret = xgbe_phy_find_phy_device(pdata);
2738 if (ret)
2739 goto err_i2c;
2740
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2741 return 0;
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2742
2743err_i2c:
2744 pdata->i2c_if.i2c_stop(pdata);
2745
2746 return ret;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2747}
2748
2749static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
2750{
2751 struct xgbe_phy_data *phy_data = pdata->phy_data;
2752 enum xgbe_mode cur_mode;
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2753 int ret;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2754
2755 /* Reset by power cycling the PHY */
2756 cur_mode = phy_data->cur_mode;
2757 xgbe_phy_power_off(pdata);
2758 xgbe_phy_set_mode(pdata, cur_mode);
2759
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2760 if (!phy_data->phydev)
2761 return 0;
2762
2763 /* Reset the external PHY */
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2764 ret = xgbe_phy_mdio_reset(pdata);
2765 if (ret)
2766 return ret;
2767
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2768 return phy_init_hw(phy_data->phydev);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2769}
2770
2771static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
2772{
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2773 struct xgbe_phy_data *phy_data = pdata->phy_data;
2774
2775 /* Unregister for driving external PHYs */
2776 mdiobus_unregister(phy_data->mii);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2777}
2778
2779static int xgbe_phy_init(struct xgbe_prv_data *pdata)
2780{
2781 struct xgbe_phy_data *phy_data;
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2782 struct mii_bus *mii;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2783 unsigned int reg;
Lendacky, Thomas5ab1dcd2016-11-10 17:10:36 -0600[diff] [blame]2784 int ret;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2785
2786 /* Check if enabled */
2787 if (!xgbe_phy_port_enabled(pdata)) {
2788 dev_info(pdata->dev, "device is not enabled\n");
2789 return -ENODEV;
2790 }
2791
Lendacky, Thomas5ab1dcd2016-11-10 17:10:36 -0600[diff] [blame]2792 /* Initialize the I2C controller */
2793 ret = pdata->i2c_if.i2c_init(pdata);
2794 if (ret)
2795 return ret;
2796
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2797 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
2798 if (!phy_data)
2799 return -ENOMEM;
2800 pdata->phy_data = phy_data;
2801
2802 reg = XP_IOREAD(pdata, XP_PROP_0);
2803 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2804 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2805 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2806 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2807 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2808 if (netif_msg_probe(pdata)) {
2809 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
2810 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
2811 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
2812 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2813 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2814 }
2815
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]2816 reg = XP_IOREAD(pdata, XP_PROP_4);
2817 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2818 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2819 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2820 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2821 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2822 if (phy_data->redrv && netif_msg_probe(pdata)) {
2823 dev_dbg(pdata->dev, "redrv present\n");
2824 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
2825 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
2826 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
2827 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
2828 }
2829
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2830 /* Validate the connection requested */
2831 if (xgbe_phy_conn_type_mismatch(pdata)) {
2832 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
2833 phy_data->port_mode, phy_data->conn_type);
2834 }
2835
2836 /* Validate the mode requested */
2837 if (xgbe_phy_port_mode_mismatch(pdata)) {
2838 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
2839 phy_data->port_mode, phy_data->port_speeds);
2840 return -EINVAL;
2841 }
2842
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2843 /* Check for and validate MDIO reset support */
2844 ret = xgbe_phy_mdio_reset_setup(pdata);
2845 if (ret)
2846 return ret;
2847
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]2848 /* Validate the re-driver information */
2849 if (xgbe_phy_redrv_error(phy_data)) {
2850 dev_err(pdata->dev, "phy re-driver settings error\n");
2851 return -EINVAL;
2852 }
2853 pdata->kr_redrv = phy_data->redrv;
2854
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2855 /* Indicate current mode is unknown */
2856 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2857
2858 /* Initialize supported features */
2859 pdata->phy.supported = 0;
2860
2861 switch (phy_data->port_mode) {
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2862 /* Backplane support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2863 case XGBE_PORT_MODE_BACKPLANE:
2864 pdata->phy.supported |= SUPPORTED_Autoneg;
2865 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2866 pdata->phy.supported |= SUPPORTED_Backplane;
2867 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2868 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2869 phy_data->start_mode = XGBE_MODE_KX_1000;
2870 }
2871 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
2872 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2873 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2874 pdata->phy.supported |=
2875 SUPPORTED_10000baseR_FEC;
2876 phy_data->start_mode = XGBE_MODE_KR;
2877 }
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2878
2879 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2880 break;
2881 case XGBE_PORT_MODE_BACKPLANE_2500:
2882 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2883 pdata->phy.supported |= SUPPORTED_Backplane;
2884 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2885 phy_data->start_mode = XGBE_MODE_KX_2500;
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2886
2887 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2888 break;
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2889
2890 /* MDIO 1GBase-T support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2891 case XGBE_PORT_MODE_1000BASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2892 pdata->phy.supported |= SUPPORTED_Autoneg;
2893 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2894 pdata->phy.supported |= SUPPORTED_TP;
2895 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2896 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2897 phy_data->start_mode = XGBE_MODE_SGMII_100;
2898 }
2899 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2900 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2901 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2902 }
2903
2904 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
2905 break;
2906
2907 /* MDIO Base-X support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2908 case XGBE_PORT_MODE_1000BASE_X:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2909 pdata->phy.supported |= SUPPORTED_Autoneg;
2910 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2911 pdata->phy.supported |= SUPPORTED_FIBRE;
2912 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2913 phy_data->start_mode = XGBE_MODE_X;
2914
2915 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
2916 break;
2917
2918 /* MDIO NBase-T support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2919 case XGBE_PORT_MODE_NBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2920 pdata->phy.supported |= SUPPORTED_Autoneg;
2921 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2922 pdata->phy.supported |= SUPPORTED_TP;
2923 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2924 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2925 phy_data->start_mode = XGBE_MODE_SGMII_100;
2926 }
2927 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2928 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2929 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2930 }
2931 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
2932 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2933 phy_data->start_mode = XGBE_MODE_KX_2500;
2934 }
2935
2936 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
2937 break;
2938
2939 /* 10GBase-T support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2940 case XGBE_PORT_MODE_10GBASE_T:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2941 pdata->phy.supported |= SUPPORTED_Autoneg;
2942 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2943 pdata->phy.supported |= SUPPORTED_TP;
2944 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2945 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2946 phy_data->start_mode = XGBE_MODE_SGMII_100;
2947 }
2948 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2949 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2950 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2951 }
2952 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
2953 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2954 phy_data->start_mode = XGBE_MODE_KR;
2955 }
2956
2957 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
2958 break;
2959
2960 /* 10GBase-R support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2961 case XGBE_PORT_MODE_10GBASE_R:
Lendacky, Thomas732f2ab2016-11-10 17:11:14 -0600[diff] [blame]2962 pdata->phy.supported |= SUPPORTED_Autoneg;
2963 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2964 pdata->phy.supported |= SUPPORTED_TP;
2965 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2966 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2967 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2968 phy_data->start_mode = XGBE_MODE_SFI;
2969
2970 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
2971 break;
2972
2973 /* SFP support */
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2974 case XGBE_PORT_MODE_SFP:
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]2975 pdata->phy.supported |= SUPPORTED_Autoneg;
2976 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2977 pdata->phy.supported |= SUPPORTED_TP;
2978 pdata->phy.supported |= SUPPORTED_FIBRE;
2979 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
2980 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2981 phy_data->start_mode = XGBE_MODE_SGMII_100;
2982 }
2983 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
2984 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2985 phy_data->start_mode = XGBE_MODE_SGMII_1000;
2986 }
2987 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
2988 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2989 phy_data->start_mode = XGBE_MODE_SFI;
2990 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2991 pdata->phy.supported |=
2992 SUPPORTED_10000baseR_FEC;
2993 }
2994
2995 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
2996
2997 xgbe_phy_sfp_setup(pdata);
2998 break;
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]2999 default:
3000 return -EINVAL;
3001 }
3002
3003 if (netif_msg_probe(pdata))
3004 dev_dbg(pdata->dev, "phy supported=%#x\n",
3005 pdata->phy.supported);
3006
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]3007 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3008 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3009 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3010 phy_data->phydev_mode);
3011 if (ret) {
3012 dev_err(pdata->dev,
3013 "mdio port/clause not compatible (%d/%u)\n",
3014 phy_data->mdio_addr, phy_data->phydev_mode);
3015 return -EINVAL;
3016 }
3017 }
3018
3019 if (phy_data->redrv && !phy_data->redrv_if) {
3020 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3021 XGBE_MDIO_MODE_CL22);
3022 if (ret) {
3023 dev_err(pdata->dev,
3024 "redriver mdio port not compatible (%u)\n",
3025 phy_data->redrv_addr);
3026 return -EINVAL;
3027 }
3028 }
3029
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]3030 /* Register for driving external PHYs */
3031 mii = devm_mdiobus_alloc(pdata->dev);
3032 if (!mii) {
3033 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3034 return -ENOMEM;
3035 }
3036
3037 mii->priv = pdata;
3038 mii->name = "amd-xgbe-mii";
3039 mii->read = xgbe_phy_mii_read;
3040 mii->write = xgbe_phy_mii_write;
3041 mii->parent = pdata->dev;
3042 mii->phy_mask = ~0;
3043 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3044 ret = mdiobus_register(mii);
3045 if (ret) {
3046 dev_err(pdata->dev, "mdiobus_register failed\n");
3047 return ret;
3048 }
3049 phy_data->mii = mii;
3050
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]3051 return 0;
3052}
3053
3054void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3055{
3056 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3057
3058 phy_impl->init = xgbe_phy_init;
3059 phy_impl->exit = xgbe_phy_exit;
3060
3061 phy_impl->reset = xgbe_phy_reset;
3062 phy_impl->start = xgbe_phy_start;
3063 phy_impl->stop = xgbe_phy_stop;
3064
3065 phy_impl->link_status = xgbe_phy_link_status;
3066
3067 phy_impl->valid_speed = xgbe_phy_valid_speed;
3068
3069 phy_impl->use_mode = xgbe_phy_use_mode;
3070 phy_impl->set_mode = xgbe_phy_set_mode;
3071 phy_impl->get_mode = xgbe_phy_get_mode;
3072 phy_impl->switch_mode = xgbe_phy_switch_mode;
3073 phy_impl->cur_mode = xgbe_phy_cur_mode;
3074
3075 phy_impl->an_mode = xgbe_phy_an_mode;
3076
Lendacky, Thomasabf0a1c2016-11-10 17:10:58 -0600[diff] [blame]3077 phy_impl->an_config = xgbe_phy_an_config;
3078
Lendacky, Thomasd7445d12016-11-10 17:11:41 -0600[diff] [blame]3079 phy_impl->an_advertising = xgbe_phy_an_advertising;
3080
Lendacky, Thomas47f164d2016-11-10 17:09:55 -0600[diff] [blame]3081 phy_impl->an_outcome = xgbe_phy_an_outcome;
3082}