blob: e0c93cc80e4b128db873d0fa93b7c6a6831049f8 [file] [log] [blame]
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03001/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
Wey-Yi Guy4e318262011-12-27 11:21:32 -08008 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
Wey-Yi Guy4e318262011-12-27 11:21:32 -080033 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030034 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -080063#include <linux/pci.h>
64#include <linux/pci-aspm.h>
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070065#include <linux/interrupt.h>
Emmanuel Grumbach87e56662011-08-25 23:10:50 -070066#include <linux/debugfs.h>
Emmanuel Grumbachcf614292012-01-08 16:33:58 +020067#include <linux/sched.h>
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -070068#include <linux/bitops.h>
69#include <linux/gfp.h>
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070070
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030071#include "iwl-trans.h"
Johannes Bergc17d0682011-09-15 11:46:42 -070072#include "iwl-trans-pcie-int.h"
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070073#include "iwl-csr.h"
74#include "iwl-prph.h"
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070075#include "iwl-eeprom.h"
Emmanuel Grumbach7a10e3e42011-09-06 09:31:21 -070076#include "iwl-agn-hw.h"
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030077
Johannes Berg0439bb62012-03-05 11:24:45 -080078#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
79
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -080080#define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -070081 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -080082 (~(1<<(trans_pcie)->cmd_queue)))
83
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -070084static int iwl_trans_rx_alloc(struct iwl_trans *trans)
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030085{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -070086 struct iwl_trans_pcie *trans_pcie =
87 IWL_TRANS_GET_PCIE_TRANS(trans);
88 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020089 struct device *dev = trans->dev;
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030090
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -070091 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030092
93 spin_lock_init(&rxq->lock);
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030094
95 if (WARN_ON(rxq->bd || rxq->rb_stts))
96 return -EINVAL;
97
98 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
Djalal Harouni84c816d2011-12-21 01:21:47 +010099 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
100 &rxq->bd_dma, GFP_KERNEL);
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300101 if (!rxq->bd)
102 goto err_bd;
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300103
104 /*Allocate the driver's pointer to receive buffer status */
Djalal Harouni84c816d2011-12-21 01:21:47 +0100105 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
106 &rxq->rb_stts_dma, GFP_KERNEL);
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300107 if (!rxq->rb_stts)
108 goto err_rb_stts;
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300109
110 return 0;
111
112err_rb_stts:
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300113 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
114 rxq->bd, rxq->bd_dma);
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300115 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
116 rxq->bd = NULL;
117err_bd:
118 return -ENOMEM;
119}
120
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700121static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300122{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700123 struct iwl_trans_pcie *trans_pcie =
124 IWL_TRANS_GET_PCIE_TRANS(trans);
125 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300126 int i;
127
128 /* Fill the rx_used queue with _all_ of the Rx buffers */
129 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
130 /* In the reset function, these buffers may have been allocated
131 * to an SKB, so we need to unmap and free potential storage */
132 if (rxq->pool[i].page != NULL) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200133 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
Johannes Bergb2cf4102012-04-09 17:46:51 -0700134 PAGE_SIZE << trans_pcie->rx_page_order,
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300135 DMA_FROM_DEVICE);
Emmanuel Grumbach790428b2011-08-25 23:11:05 -0700136 __free_pages(rxq->pool[i].page,
Johannes Bergb2cf4102012-04-09 17:46:51 -0700137 trans_pcie->rx_page_order);
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300138 rxq->pool[i].page = NULL;
139 }
140 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
141 }
142}
143
Emmanuel Grumbachfd656932011-08-25 23:11:19 -0700144static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700145 struct iwl_rx_queue *rxq)
146{
Johannes Bergb2cf4102012-04-09 17:46:51 -0700147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700148 u32 rb_size;
149 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
Johannes Bergc17d0682011-09-15 11:46:42 -0700150 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700151
Johannes Bergb2cf4102012-04-09 17:46:51 -0700152 if (trans_pcie->rx_buf_size_8k)
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
154 else
155 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156
157 /* Stop Rx DMA */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200158 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700159
160 /* Reset driver's Rx queue write index */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700162
163 /* Tell device where to find RBD circular buffer in DRAM */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700165 (u32)(rxq->bd_dma >> 8));
166
167 /* Tell device where in DRAM to update its Rx status */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200168 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700169 rxq->rb_stts_dma >> 4);
170
171 /* Enable Rx DMA
172 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
173 * the credit mechanism in 5000 HW RX FIFO
174 * Direct rx interrupts to hosts
175 * Rx buffer size 4 or 8k
176 * RB timeout 0x10
177 * 256 RBDs
178 */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200179 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700180 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
181 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
182 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700183 rb_size|
184 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
185 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
186
187 /* Set interrupt coalescing timer to default (2048 usecs) */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200188 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700189}
190
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700191static int iwl_rx_init(struct iwl_trans *trans)
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300192{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700193 struct iwl_trans_pcie *trans_pcie =
194 IWL_TRANS_GET_PCIE_TRANS(trans);
195 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
196
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300197 int i, err;
198 unsigned long flags;
199
200 if (!rxq->bd) {
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700201 err = iwl_trans_rx_alloc(trans);
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300202 if (err)
203 return err;
204 }
205
206 spin_lock_irqsave(&rxq->lock, flags);
207 INIT_LIST_HEAD(&rxq->rx_free);
208 INIT_LIST_HEAD(&rxq->rx_used);
209
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700210 iwl_trans_rxq_free_rx_bufs(trans);
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300211
212 for (i = 0; i < RX_QUEUE_SIZE; i++)
213 rxq->queue[i] = NULL;
214
215 /* Set us so that we have processed and used all buffers, but have
216 * not restocked the Rx queue with fresh buffers */
217 rxq->read = rxq->write = 0;
218 rxq->write_actual = 0;
219 rxq->free_count = 0;
220 spin_unlock_irqrestore(&rxq->lock, flags);
221
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700222 iwlagn_rx_replenish(trans);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700223
Emmanuel Grumbachfd656932011-08-25 23:11:19 -0700224 iwl_trans_rx_hw_init(trans, rxq);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700225
Johannes Berg7b114882012-02-05 13:55:11 -0800226 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700227 rxq->need_update = 1;
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700228 iwl_rx_queue_update_write_ptr(trans, rxq);
Johannes Berg7b114882012-02-05 13:55:11 -0800229 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700230
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300231 return 0;
232}
233
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700234static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300235{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700236 struct iwl_trans_pcie *trans_pcie =
237 IWL_TRANS_GET_PCIE_TRANS(trans);
238 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
239
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300240 unsigned long flags;
241
242 /*if rxq->bd is NULL, it means that nothing has been allocated,
243 * exit now */
244 if (!rxq->bd) {
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700245 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300246 return;
247 }
248
249 spin_lock_irqsave(&rxq->lock, flags);
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700250 iwl_trans_rxq_free_rx_bufs(trans);
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300251 spin_unlock_irqrestore(&rxq->lock, flags);
252
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200253 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300254 rxq->bd, rxq->bd_dma);
255 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
256 rxq->bd = NULL;
257
258 if (rxq->rb_stts)
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200259 dma_free_coherent(trans->dev,
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300260 sizeof(struct iwl_rb_status),
261 rxq->rb_stts, rxq->rb_stts_dma);
262 else
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700263 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
Emmanuel Grumbacha0f6b0a2011-06-21 14:25:45 +0300264 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
265 rxq->rb_stts = NULL;
266}
267
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700268static int iwl_trans_rx_stop(struct iwl_trans *trans)
Emmanuel Grumbachc2c52e82011-07-08 08:46:11 -0700269{
270
271 /* stop Rx DMA */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200272 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
273 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
Emmanuel Grumbachc2c52e82011-07-08 08:46:11 -0700274 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
275}
276
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700277static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700278 struct iwl_dma_ptr *ptr, size_t size)
279{
280 if (WARN_ON(ptr->addr))
281 return -EINVAL;
282
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200283 ptr->addr = dma_alloc_coherent(trans->dev, size,
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700284 &ptr->dma, GFP_KERNEL);
285 if (!ptr->addr)
286 return -ENOMEM;
287 ptr->size = size;
288 return 0;
289}
290
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700291static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700292 struct iwl_dma_ptr *ptr)
293{
294 if (unlikely(!ptr->addr))
295 return;
296
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200297 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700298 memset(ptr, 0, sizeof(*ptr));
299}
300
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700301static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
302{
303 struct iwl_tx_queue *txq = (void *)data;
304 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
305 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
306
307 spin_lock(&txq->lock);
308 /* check if triggered erroneously */
309 if (txq->q.read_ptr == txq->q.write_ptr) {
310 spin_unlock(&txq->lock);
311 return;
312 }
313 spin_unlock(&txq->lock);
314
315
316 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
317 jiffies_to_msecs(trans_pcie->wd_timeout));
318 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
319 txq->q.read_ptr, txq->q.write_ptr);
320 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
321 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
322 & (TFD_QUEUE_SIZE_MAX - 1),
323 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
324
325 iwl_op_mode_nic_error(trans->op_mode);
326}
327
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700328static int iwl_trans_txq_alloc(struct iwl_trans *trans,
329 struct iwl_tx_queue *txq, int slots_num,
330 u32 txq_id)
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700331{
Emmanuel Grumbachab9e2122011-08-25 23:11:10 -0700332 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700333 int i;
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800334 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700335
Johannes Bergbf8440e2012-03-19 17:12:06 +0100336 if (WARN_ON(txq->entries || txq->tfds))
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700337 return -EINVAL;
338
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700339 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
340 (unsigned long)txq);
341 txq->trans_pcie = trans_pcie;
342
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700343 txq->q.n_window = slots_num;
344
Johannes Bergbf8440e2012-03-19 17:12:06 +0100345 txq->entries = kcalloc(slots_num,
346 sizeof(struct iwl_pcie_tx_queue_entry),
347 GFP_KERNEL);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700348
Johannes Bergbf8440e2012-03-19 17:12:06 +0100349 if (!txq->entries)
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700350 goto error;
351
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800352 if (txq_id == trans_pcie->cmd_queue)
Emmanuel Grumbachdfa2bdb2011-08-25 23:11:23 -0700353 for (i = 0; i < slots_num; i++) {
Johannes Bergbf8440e2012-03-19 17:12:06 +0100354 txq->entries[i].cmd =
355 kmalloc(sizeof(struct iwl_device_cmd),
356 GFP_KERNEL);
357 if (!txq->entries[i].cmd)
Emmanuel Grumbachdfa2bdb2011-08-25 23:11:23 -0700358 goto error;
359 }
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700360
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700361 /* Circular buffer of transmit frame descriptors (TFDs),
362 * shared with device */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200363 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700364 &txq->q.dma_addr, GFP_KERNEL);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700365 if (!txq->tfds) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700366 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700367 goto error;
368 }
369 txq->q.id = txq_id;
370
371 return 0;
372error:
Johannes Bergbf8440e2012-03-19 17:12:06 +0100373 if (txq->entries && txq_id == trans_pcie->cmd_queue)
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700374 for (i = 0; i < slots_num; i++)
Johannes Bergbf8440e2012-03-19 17:12:06 +0100375 kfree(txq->entries[i].cmd);
376 kfree(txq->entries);
377 txq->entries = NULL;
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700378
379 return -ENOMEM;
380
381}
382
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700383static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
Johannes Berg9eae88f2012-03-15 13:26:52 -0700384 int slots_num, u32 txq_id)
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700385{
386 int ret;
387
388 txq->need_update = 0;
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700389
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700390 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
391 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
392 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
393
394 /* Initialize queue's high/low-water marks, and head/tail indexes */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700395 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700396 txq_id);
397 if (ret)
398 return ret;
399
Johannes Berg015c15e2012-03-05 11:24:24 -0800400 spin_lock_init(&txq->lock);
401
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700402 /*
403 * Tell nic where to find circular buffer of Tx Frame Descriptors for
404 * given Tx queue, and enable the DMA channel used for that queue.
405 * Circular buffer (TFD queue in DRAM) physical base address */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200406 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700407 txq->q.dma_addr >> 8);
408
409 return 0;
410}
411
412/**
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700413 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
414 */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700415static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700416{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700417 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
418 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700419 struct iwl_queue *q = &txq->q;
Emmanuel Grumbach39644e92011-09-15 11:46:29 -0700420 enum dma_data_direction dma_dir;
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700421
422 if (!q->n_bd)
423 return;
424
Emmanuel Grumbach39644e92011-09-15 11:46:29 -0700425 /* In the command queue, all the TBs are mapped as BIDI
426 * so unmap them as such.
427 */
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800428 if (txq_id == trans_pcie->cmd_queue)
Emmanuel Grumbach39644e92011-09-15 11:46:29 -0700429 dma_dir = DMA_BIDIRECTIONAL;
Johannes Berg015c15e2012-03-05 11:24:24 -0800430 else
Emmanuel Grumbach39644e92011-09-15 11:46:29 -0700431 dma_dir = DMA_TO_DEVICE;
432
Johannes Berg015c15e2012-03-05 11:24:24 -0800433 spin_lock_bh(&txq->lock);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700434 while (q->write_ptr != q->read_ptr) {
435 /* The read_ptr needs to bound by q->n_window */
Emmanuel Grumbach39644e92011-09-15 11:46:29 -0700436 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
437 dma_dir);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700438 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
439 }
Johannes Berg015c15e2012-03-05 11:24:24 -0800440 spin_unlock_bh(&txq->lock);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700441}
442
443/**
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700444 * iwl_tx_queue_free - Deallocate DMA queue.
445 * @txq: Transmit queue to deallocate.
446 *
447 * Empty queue by removing and destroying all BD's.
448 * Free all buffers.
449 * 0-fill, but do not free "txq" descriptor structure.
450 */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700451static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700452{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
454 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200455 struct device *dev = trans->dev;
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700456 int i;
457 if (WARN_ON(!txq))
458 return;
459
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700460 iwl_tx_queue_unmap(trans, txq_id);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700461
462 /* De-alloc array of command/tx buffers */
Emmanuel Grumbachdfa2bdb2011-08-25 23:11:23 -0700463
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800464 if (txq_id == trans_pcie->cmd_queue)
Emmanuel Grumbachdfa2bdb2011-08-25 23:11:23 -0700465 for (i = 0; i < txq->q.n_window; i++)
Johannes Bergbf8440e2012-03-19 17:12:06 +0100466 kfree(txq->entries[i].cmd);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700467
468 /* De-alloc circular buffer of TFDs */
469 if (txq->q.n_bd) {
Emmanuel Grumbachab9e2122011-08-25 23:11:10 -0700470 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700471 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
472 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
473 }
474
Johannes Bergbf8440e2012-03-19 17:12:06 +0100475 kfree(txq->entries);
476 txq->entries = NULL;
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700477
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700478 del_timer_sync(&txq->stuck_timer);
479
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700480 /* 0-fill queue descriptor structure */
481 memset(txq, 0, sizeof(*txq));
482}
483
484/**
485 * iwl_trans_tx_free - Free TXQ Context
486 *
487 * Destroy all TX DMA queues and structures
488 */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700489static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700490{
491 int txq_id;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700493
494 /* Tx queues */
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700495 if (trans_pcie->txq) {
Emmanuel Grumbachd6189122011-08-25 23:10:39 -0700496 for (txq_id = 0;
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700497 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700498 iwl_tx_queue_free(trans, txq_id);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700499 }
500
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700501 kfree(trans_pcie->txq);
502 trans_pcie->txq = NULL;
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700503
Emmanuel Grumbach9d6b2cb2011-08-25 23:11:12 -0700504 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700505
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700506 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
Emmanuel Grumbach1359ca42011-07-08 08:46:10 -0700507}
508
509/**
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700510 * iwl_trans_tx_alloc - allocate TX context
511 * Allocate all Tx DMA structures and initialize them
512 *
513 * @param priv
514 * @return error code
515 */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700516static int iwl_trans_tx_alloc(struct iwl_trans *trans)
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700517{
518 int ret;
519 int txq_id, slots_num;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700520 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700521
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700522 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
Emmanuel Grumbachab9e2122011-08-25 23:11:10 -0700523 sizeof(struct iwlagn_scd_bc_tbl);
524
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700525 /*It is not allowed to alloc twice, so warn when this happens.
526 * We cannot rely on the previous allocation, so free and fail */
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700527 if (WARN_ON(trans_pcie->txq)) {
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700528 ret = -EINVAL;
529 goto error;
530 }
531
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700532 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
Emmanuel Grumbachab9e2122011-08-25 23:11:10 -0700533 scd_bc_tbls_size);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700534 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700535 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700536 goto error;
537 }
538
539 /* Alloc keep-warm buffer */
Emmanuel Grumbach9d6b2cb2011-08-25 23:11:12 -0700540 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700541 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700542 IWL_ERR(trans, "Keep Warm allocation failed\n");
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700543 goto error;
544 }
545
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700546 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
Emmanuel Grumbach7f90dce2011-09-22 15:14:53 -0700547 sizeof(struct iwl_tx_queue), GFP_KERNEL);
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700548 if (!trans_pcie->txq) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700549 IWL_ERR(trans, "Not enough memory for txq\n");
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700550 ret = ENOMEM;
551 goto error;
552 }
553
554 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700555 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
Wey-Yi Guy1745e4402012-03-09 11:13:40 -0800556 txq_id++) {
Wey-Yi Guy9ba19472012-03-09 10:12:42 -0800557 slots_num = (txq_id == trans_pcie->cmd_queue) ?
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700558 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700559 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
560 slots_num, txq_id);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700561 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700562 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700563 goto error;
564 }
565 }
566
567 return 0;
568
569error:
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -0700570 iwl_trans_pcie_tx_free(trans);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700571
572 return ret;
573}
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700574static int iwl_tx_init(struct iwl_trans *trans)
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700575{
576 int ret;
577 int txq_id, slots_num;
578 unsigned long flags;
579 bool alloc = false;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700580 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700581
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700582 if (!trans_pcie->txq) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700583 ret = iwl_trans_tx_alloc(trans);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700584 if (ret)
585 goto error;
586 alloc = true;
587 }
588
Johannes Berg7b114882012-02-05 13:55:11 -0800589 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700590
591 /* Turn off all Tx DMA fifos */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200592 iwl_write_prph(trans, SCD_TXFACT, 0);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700593
594 /* Tell NIC where to find the "keep warm" buffer */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200595 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
Emmanuel Grumbach83ed9012011-08-25 23:11:14 -0700596 trans_pcie->kw.dma >> 4);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700597
Johannes Berg7b114882012-02-05 13:55:11 -0800598 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700599
600 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700601 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
Wey-Yi Guy1745e4402012-03-09 11:13:40 -0800602 txq_id++) {
Wey-Yi Guy9ba19472012-03-09 10:12:42 -0800603 slots_num = (txq_id == trans_pcie->cmd_queue) ?
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700604 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700605 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
606 slots_num, txq_id);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700607 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700608 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700609 goto error;
610 }
611 }
612
613 return 0;
614error:
615 /*Upon error, free only if we allocated something */
616 if (alloc)
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -0700617 iwl_trans_pcie_tx_free(trans);
Emmanuel Grumbach02aca582011-06-28 08:58:41 -0700618 return ret;
619}
620
Emmanuel Grumbach3e10cae2011-09-06 09:31:18 -0700621static void iwl_set_pwr_vmain(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300622{
623/*
624 * (for documentation purposes)
625 * to set power to V_AUX, do:
626
627 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200628 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300629 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
630 ~APMG_PS_CTRL_MSK_PWR_SRC);
631 */
632
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200633 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300634 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
635 ~APMG_PS_CTRL_MSK_PWR_SRC);
636}
637
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200638/* PCI registers */
639#define PCI_CFG_RETRY_TIMEOUT 0x041
640#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
641#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
642
643static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
644{
645 int pos;
646 u16 pci_lnk_ctl;
647 struct iwl_trans_pcie *trans_pcie =
648 IWL_TRANS_GET_PCIE_TRANS(trans);
649
650 struct pci_dev *pci_dev = trans_pcie->pci_dev;
651
652 pos = pci_pcie_cap(pci_dev);
653 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
654 return pci_lnk_ctl;
655}
656
657static void iwl_apm_config(struct iwl_trans *trans)
658{
659 /*
660 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
661 * Check if BIOS (or OS) enabled L1-ASPM on this device.
662 * If so (likely), disable L0S, so device moves directly L0->L1;
663 * costs negligible amount of power savings.
664 * If not (unlikely), enable L0S, so there is at least some
665 * power savings, even without L1.
666 */
667 u16 lctl = iwl_pciexp_link_ctrl(trans);
668
669 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
670 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
671 /* L1-ASPM enabled; disable(!) L0S */
672 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
673 dev_printk(KERN_INFO, trans->dev,
674 "L1 Enabled; Disabling L0S\n");
675 } else {
676 /* L1-ASPM disabled; enable(!) L0S */
677 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
678 dev_printk(KERN_INFO, trans->dev,
679 "L1 Disabled; Enabling L0S\n");
680 }
Emmanuel Grumbachf6d0e9b2012-01-08 21:19:45 +0200681 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200682}
683
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200684/*
685 * Start up NIC's basic functionality after it has been reset
686 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
687 * NOTE: This does not load uCode nor start the embedded processor
688 */
689static int iwl_apm_init(struct iwl_trans *trans)
690{
Don Fry83626402012-03-07 09:52:37 -0800691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200692 int ret = 0;
693 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
694
695 /*
696 * Use "set_bit" below rather than "write", to preserve any hardware
697 * bits already set by default after reset.
698 */
699
700 /* Disable L0S exit timer (platform NMI Work/Around) */
701 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
702 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
703
704 /*
705 * Disable L0s without affecting L1;
706 * don't wait for ICH L0s (ICH bug W/A)
707 */
708 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
709 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
710
711 /* Set FH wait threshold to maximum (HW error during stress W/A) */
712 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
713
714 /*
715 * Enable HAP INTA (interrupt from management bus) to
716 * wake device's PCI Express link L1a -> L0s
717 */
718 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
719 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
720
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200721 iwl_apm_config(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200722
723 /* Configure analog phase-lock-loop before activating to D0A */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700724 if (trans->cfg->base_params->pll_cfg_val)
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200725 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700726 trans->cfg->base_params->pll_cfg_val);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200727
728 /*
729 * Set "initialization complete" bit to move adapter from
730 * D0U* --> D0A* (powered-up active) state.
731 */
732 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
733
734 /*
735 * Wait for clock stabilization; once stabilized, access to
736 * device-internal resources is supported, e.g. iwl_write_prph()
737 * and accesses to uCode SRAM.
738 */
739 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
740 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
741 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
742 if (ret < 0) {
743 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
744 goto out;
745 }
746
747 /*
748 * Enable DMA clock and wait for it to stabilize.
749 *
750 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
751 * do not disable clocks. This preserves any hardware bits already
752 * set by default in "CLK_CTRL_REG" after reset.
753 */
754 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
755 udelay(20);
756
757 /* Disable L1-Active */
758 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
759 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
760
Don Fry83626402012-03-07 09:52:37 -0800761 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200762
763out:
764 return ret;
765}
766
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200767static int iwl_apm_stop_master(struct iwl_trans *trans)
768{
769 int ret = 0;
770
771 /* stop device's busmaster DMA activity */
772 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
773
774 ret = iwl_poll_bit(trans, CSR_RESET,
775 CSR_RESET_REG_FLAG_MASTER_DISABLED,
776 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
777 if (ret)
778 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
779
780 IWL_DEBUG_INFO(trans, "stop master\n");
781
782 return ret;
783}
784
785static void iwl_apm_stop(struct iwl_trans *trans)
786{
Don Fry83626402012-03-07 09:52:37 -0800787 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200788 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
789
Don Fry83626402012-03-07 09:52:37 -0800790 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200791
792 /* Stop device's DMA activity */
793 iwl_apm_stop_master(trans);
794
795 /* Reset the entire device */
796 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
797
798 udelay(10);
799
800 /*
801 * Clear "initialization complete" bit to move adapter from
802 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
803 */
804 iwl_clear_bit(trans, CSR_GP_CNTRL,
805 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
806}
807
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700808static int iwl_nic_init(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300809{
Johannes Berg7b114882012-02-05 13:55:11 -0800810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300811 unsigned long flags;
812
813 /* nic_init */
Johannes Berg7b114882012-02-05 13:55:11 -0800814 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200815 iwl_apm_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300816
817 /* Set interrupt coalescing calibration timer to default (512 usecs) */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200818 iwl_write8(trans, CSR_INT_COALESCING,
Emmanuel Grumbach83ed9012011-08-25 23:11:14 -0700819 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300820
Johannes Berg7b114882012-02-05 13:55:11 -0800821 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300822
Emmanuel Grumbach3e10cae2011-09-06 09:31:18 -0700823 iwl_set_pwr_vmain(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300824
Johannes Bergecdb9752012-03-06 13:31:03 -0800825 iwl_op_mode_nic_config(trans->op_mode);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300826
Gregory Greenmana5916972012-01-10 19:22:56 +0200827#ifndef CONFIG_IWLWIFI_IDI
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300828 /* Allocate the RX queue, or reset if it is already allocated */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700829 iwl_rx_init(trans);
Gregory Greenmana5916972012-01-10 19:22:56 +0200830#endif
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300831
832 /* Allocate or reset and init all Tx and Command queues */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700833 if (iwl_tx_init(trans))
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300834 return -ENOMEM;
835
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700836 if (trans->cfg->base_params->shadow_reg_enable) {
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300837 /* enable shadow regs in HW */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200838 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300839 0x800FFFFF);
840 }
841
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300842 return 0;
843}
844
845#define HW_READY_TIMEOUT (50)
846
847/* Note: returns poll_bit return value, which is >= 0 if success */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700848static int iwl_set_hw_ready(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300849{
850 int ret;
851
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200852 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300853 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
854
855 /* See if we got it */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200856 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300857 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
858 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
859 HW_READY_TIMEOUT);
860
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700861 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300862 return ret;
863}
864
865/* Note: returns standard 0/-ERROR code */
Emmanuel Grumbachebb76782012-01-08 13:24:57 +0200866static int iwl_prepare_card_hw(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300867{
868 int ret;
869
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700870 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300871
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700872 ret = iwl_set_hw_ready(trans);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +0200873 /* If the card is ready, exit 0 */
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300874 if (ret >= 0)
875 return 0;
876
877 /* If HW is not ready, prepare the conditions to check again */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200878 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300879 CSR_HW_IF_CONFIG_REG_PREPARE);
880
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200881 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300882 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
883 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
884
885 if (ret < 0)
886 return ret;
887
888 /* HW should be ready by now, check again. */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700889 ret = iwl_set_hw_ready(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300890 if (ret >= 0)
891 return 0;
892 return ret;
893}
894
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200895/*
896 * ucode
897 */
David Spinadel6dfa8d02012-03-10 13:00:14 -0800898static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
899 const struct fw_desc *section)
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200900{
Johannes Berg13df1aa2012-03-06 13:31:00 -0800901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
David Spinadel6dfa8d02012-03-10 13:00:14 -0800902 dma_addr_t phy_addr = section->p_addr;
903 u32 byte_cnt = section->len;
904 u32 dst_addr = section->offset;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200905 int ret;
906
Johannes Berg13df1aa2012-03-06 13:31:00 -0800907 trans_pcie->ucode_write_complete = false;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200908
909 iwl_write_direct32(trans,
910 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
911 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
912
913 iwl_write_direct32(trans,
914 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
915
916 iwl_write_direct32(trans,
917 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
918 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
919
920 iwl_write_direct32(trans,
921 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
922 (iwl_get_dma_hi_addr(phy_addr)
923 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
924
925 iwl_write_direct32(trans,
926 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
927 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
928 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
929 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
930
931 iwl_write_direct32(trans,
932 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
933 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
934 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
935 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
936
David Spinadel6dfa8d02012-03-10 13:00:14 -0800937 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
938 section_num);
Johannes Berg13df1aa2012-03-06 13:31:00 -0800939 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
940 trans_pcie->ucode_write_complete, 5 * HZ);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200941 if (!ret) {
David Spinadel6dfa8d02012-03-10 13:00:14 -0800942 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
943 section_num);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200944 return -ETIMEDOUT;
945 }
946
947 return 0;
948}
949
Johannes Berg0692fe42012-03-06 13:30:37 -0800950static int iwl_load_given_ucode(struct iwl_trans *trans,
951 const struct fw_img *image)
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200952{
953 int ret = 0;
David Spinadel6dfa8d02012-03-10 13:00:14 -0800954 int i;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200955
David Spinadel6dfa8d02012-03-10 13:00:14 -0800956 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
957 if (!image->sec[i].p_addr)
958 break;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200959
David Spinadel6dfa8d02012-03-10 13:00:14 -0800960 ret = iwl_load_section(trans, i, &image->sec[i]);
961 if (ret)
962 return ret;
963 }
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200964
965 /* Remove all resets to allow NIC to operate */
966 iwl_write32(trans, CSR_RESET, 0);
967
968 return 0;
969}
970
Johannes Berg0692fe42012-03-06 13:30:37 -0800971static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
972 const struct fw_img *fw)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300973{
974 int ret;
Johannes Bergc9eec952012-03-06 13:30:43 -0800975 bool hw_rfkill;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300976
Johannes Berg496bab32012-03-06 13:30:45 -0800977 /* This may fail if AMT took ownership of the device */
978 if (iwl_prepare_card_hw(trans)) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700979 IWL_WARN(trans, "Exit HW not ready\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300980 return -EIO;
981 }
982
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +0200983 iwl_enable_rfkill_int(trans);
984
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300985 /* If platform's RF_KILL switch is NOT set to KILL */
Emmanuel Grumbach8d425512012-03-28 11:00:58 +0200986 hw_rfkill = iwl_is_rfkill_set(trans);
Johannes Bergc9eec952012-03-06 13:30:43 -0800987 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +0200988 if (hw_rfkill)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300989 return -ERFKILL;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300990
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200991 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300992
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700993 ret = iwl_nic_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300994 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700995 IWL_ERR(trans, "Unable to init nic\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300996 return ret;
997 }
998
999 /* make sure rfkill handshake bits are cleared */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001000 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1001 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001002 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1003
1004 /* clear (again), then enable host interrupts */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001005 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001006 iwl_enable_interrupts(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001007
1008 /* really make sure rfkill handshake bits are cleared */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001009 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1010 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001011
Emmanuel Grumbachcf614292012-01-08 16:33:58 +02001012 /* Load the given image to the HW */
Johannes Berg9441b85d2012-03-07 09:52:22 -08001013 return iwl_load_given_ucode(trans, fw);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +03001014}
1015
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001016/*
1017 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
Johannes Berg7b114882012-02-05 13:55:11 -08001018 * must be called under the irq lock and with MAC access
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001019 */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001020static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001021{
Johannes Berg7b114882012-02-05 13:55:11 -08001022 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1023 IWL_TRANS_GET_PCIE_TRANS(trans);
1024
1025 lockdep_assert_held(&trans_pcie->irq_lock);
1026
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001027 iwl_write_prph(trans, SCD_TXFACT, mask);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001028}
1029
Emmanuel Grumbached6a3802012-01-02 16:10:08 +02001030static void iwl_tx_start(struct iwl_trans *trans)
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001031{
Johannes Berg9eae88f2012-03-15 13:26:52 -07001032 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001033 u32 a;
1034 unsigned long flags;
1035 int i, chan;
1036 u32 reg_val;
1037
Johannes Berg7b114882012-02-05 13:55:11 -08001038 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001039
Emmanuel Grumbach83ed9012011-08-25 23:11:14 -07001040 trans_pcie->scd_base_addr =
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001041 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
Emmanuel Grumbach105183b2011-08-25 23:11:02 -07001042 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001043 /* reset conext data memory */
Emmanuel Grumbach105183b2011-08-25 23:11:02 -07001044 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001045 a += 4)
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001046 iwl_write_targ_mem(trans, a, 0);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001047 /* reset tx status memory */
Emmanuel Grumbach105183b2011-08-25 23:11:02 -07001048 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001049 a += 4)
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001050 iwl_write_targ_mem(trans, a, 0);
Emmanuel Grumbach105183b2011-08-25 23:11:02 -07001051 for (; a < trans_pcie->scd_base_addr +
Wey-Yi Guy1745e4402012-03-09 11:13:40 -08001052 SCD_TRANS_TBL_OFFSET_QUEUE(
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001053 trans->cfg->base_params->num_of_queues);
Emmanuel Grumbachd6189122011-08-25 23:10:39 -07001054 a += 4)
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001055 iwl_write_targ_mem(trans, a, 0);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001056
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001057 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
Emmanuel Grumbach105183b2011-08-25 23:11:02 -07001058 trans_pcie->scd_bc_tbls.dma >> 10);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001059
1060 /* Enable DMA channel */
1061 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001062 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001063 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1064 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1065
1066 /* Update FH chicken bits */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001067 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1068 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001069 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1070
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001071 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001072 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001073 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001074
1075 /* initiate the queues */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001076 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001077 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1078 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1079 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001080 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001081 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001082 SCD_CONTEXT_QUEUE_OFFSET(i) +
1083 sizeof(u32),
1084 ((SCD_WIN_SIZE <<
1085 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1086 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1087 ((SCD_FRAME_LIMIT <<
1088 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1089 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1090 }
1091
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001092 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001093 IWL_MASK(0, trans->cfg->base_params->num_of_queues));
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001094
1095 /* Activate all Tx DMA/FIFO channels */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001096 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001097
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001098 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001099
Johannes Berg9eae88f2012-03-15 13:26:52 -07001100 /* make sure all queue are not stopped/used */
1101 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1102 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001103
Johannes Berg9eae88f2012-03-15 13:26:52 -07001104 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1105 int fifo = trans_pcie->setup_q_to_fifo[i];
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001106
Johannes Berg9eae88f2012-03-15 13:26:52 -07001107 set_bit(i, trans_pcie->queue_used);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001108
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001109 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
Johannes Berg9eae88f2012-03-15 13:26:52 -07001110 fifo, true);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001111 }
1112
Johannes Berg7b114882012-02-05 13:55:11 -08001113 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001114
1115 /* Enable L1-Active */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001116 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +03001117 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1118}
1119
Emmanuel Grumbached6a3802012-01-02 16:10:08 +02001120static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1121{
1122 iwl_reset_ict(trans);
1123 iwl_tx_start(trans);
1124}
1125
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001126/**
1127 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1128 */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001129static int iwl_trans_tx_stop(struct iwl_trans *trans)
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001130{
Stanislaw Gruszkac2945f32012-03-07 09:52:27 -08001131 int ch, txq_id, ret;
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001132 unsigned long flags;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001133 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001134
1135 /* Turn off all Tx DMA fifos */
Johannes Berg7b114882012-02-05 13:55:11 -08001136 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001137
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001138 iwl_trans_txq_set_sched(trans, 0);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001139
1140 /* Stop each Tx DMA channel, and wait for it to be idle */
Wey-Yi Guy02f6f652011-07-08 08:46:15 -07001141 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001142 iwl_write_direct32(trans,
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001143 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
Stanislaw Gruszkac2945f32012-03-07 09:52:27 -08001144 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001145 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
Stanislaw Gruszkac2945f32012-03-07 09:52:27 -08001146 1000);
1147 if (ret < 0)
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001148 IWL_ERR(trans, "Failing on timeout while stopping"
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001149 " DMA channel %d [0x%08x]", ch,
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001150 iwl_read_direct32(trans,
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001151 FH_TSSR_TX_STATUS_REG));
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001152 }
Johannes Berg7b114882012-02-05 13:55:11 -08001153 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001154
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001155 if (!trans_pcie->txq) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001156 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001157 return 0;
1158 }
1159
1160 /* Unmap DMA from host system and free skb's */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001161 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
Wey-Yi Guy1745e4402012-03-09 11:13:40 -08001162 txq_id++)
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001163 iwl_tx_queue_unmap(trans, txq_id);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -07001164
1165 return 0;
1166}
1167
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001168static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001169{
1170 unsigned long flags;
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001171 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001172
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001173 /* tell the device to stop sending interrupts */
Johannes Berg7b114882012-02-05 13:55:11 -08001174 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001175 iwl_disable_interrupts(trans);
Johannes Berg7b114882012-02-05 13:55:11 -08001176 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001177
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001178 /* device going down, Stop using ICT table */
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001179 iwl_disable_ict(trans);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001180
1181 /*
1182 * If a HW restart happens during firmware loading,
1183 * then the firmware loading might call this function
1184 * and later it might be called again due to the
1185 * restart. So don't process again if the device is
1186 * already dead.
1187 */
Don Fry83626402012-03-07 09:52:37 -08001188 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001189 iwl_trans_tx_stop(trans);
Gregory Greenmana5916972012-01-10 19:22:56 +02001190#ifndef CONFIG_IWLWIFI_IDI
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001191 iwl_trans_rx_stop(trans);
Gregory Greenmana5916972012-01-10 19:22:56 +02001192#endif
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001193 /* Power-down device's busmaster DMA clocks */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001194 iwl_write_prph(trans, APMG_CLK_DIS_REG,
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001195 APMG_CLK_VAL_DMA_CLK_RQT);
1196 udelay(5);
1197 }
1198
1199 /* Make sure (redundant) we've released our request to stay awake */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001200 iwl_clear_bit(trans, CSR_GP_CNTRL,
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001201 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001202
1203 /* Stop the device, and put it in low power state */
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001204 iwl_apm_stop(trans);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001205
1206 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1207 * Clean again the interrupt here
1208 */
Johannes Berg7b114882012-02-05 13:55:11 -08001209 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001210 iwl_disable_interrupts(trans);
Johannes Berg7b114882012-02-05 13:55:11 -08001211 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001212
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001213 iwl_enable_rfkill_int(trans);
1214
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001215 /* wait to make sure we flush pending tasklet*/
Johannes Berg75595532012-03-06 13:31:01 -08001216 synchronize_irq(trans_pcie->irq);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001217 tasklet_kill(&trans_pcie->irq_tasklet);
1218
Johannes Berg1ee158d2012-02-17 10:07:44 -08001219 cancel_work_sync(&trans_pcie->rx_replenish);
1220
Emmanuel Grumbach43e58852011-11-09 16:50:50 -08001221 /* stop and reset the on-board processor */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001222 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
Don Fry74fda972012-03-20 16:36:54 -07001223
1224 /* clear all status bits */
1225 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1226 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1227 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
Don Fry01d651d2012-03-23 08:34:31 -07001228 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +03001229}
1230
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08001231static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1232{
1233 /* let the ucode operate on its own */
1234 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1235 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1236
1237 iwl_disable_interrupts(trans);
1238 iwl_clear_bit(trans, CSR_GP_CNTRL,
1239 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1240}
1241
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001242static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001243 struct iwl_device_cmd *dev_cmd, int txq_id)
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001244{
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1246 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
Emmanuel Grumbach132f98c2011-09-20 15:37:24 -07001247 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001248 struct iwl_cmd_meta *out_meta;
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001249 struct iwl_tx_queue *txq;
1250 struct iwl_queue *q;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001251 dma_addr_t phys_addr = 0;
1252 dma_addr_t txcmd_phys;
1253 dma_addr_t scratch_phys;
1254 u16 len, firstlen, secondlen;
1255 u8 wait_write_ptr = 0;
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001256 __le16 fc = hdr->frame_control;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001257 u8 hdr_len = ieee80211_hdrlen(fc);
Emmanuel Grumbach631b84c2011-12-07 09:30:21 +02001258 u16 __maybe_unused wifi_seq;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001259
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001260 txq = &trans_pcie->txq[txq_id];
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001261 q = &txq->q;
1262
Johannes Berg9eae88f2012-03-15 13:26:52 -07001263 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1264 WARN_ON_ONCE(1);
1265 return -EINVAL;
1266 }
Johannes Berg015c15e2012-03-05 11:24:24 -08001267
Johannes Berg9eae88f2012-03-15 13:26:52 -07001268 spin_lock(&txq->lock);
Emmanuel Grumbach631b84c2011-12-07 09:30:21 +02001269
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001270 /* Set up driver data for this TFD */
Johannes Bergbf8440e2012-03-19 17:12:06 +01001271 txq->entries[q->write_ptr].skb = skb;
1272 txq->entries[q->write_ptr].cmd = dev_cmd;
Emmanuel Grumbachdfa2bdb2011-08-25 23:11:23 -07001273
1274 dev_cmd->hdr.cmd = REPLY_TX;
1275 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1276 INDEX_TO_SEQ(q->write_ptr)));
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001277
1278 /* Set up first empty entry in queue's array of Tx/cmd buffers */
Johannes Bergbf8440e2012-03-19 17:12:06 +01001279 out_meta = &txq->entries[q->write_ptr].meta;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001280
1281 /*
1282 * Use the first empty entry in this queue's command buffer array
1283 * to contain the Tx command and MAC header concatenated together
1284 * (payload data will be in another buffer).
1285 * Size of this varies, due to varying MAC header length.
1286 * If end is not dword aligned, we'll have 2 extra bytes at the end
1287 * of the MAC header (device reads on dword boundaries).
1288 * We'll tell device about this padding later.
1289 */
1290 len = sizeof(struct iwl_tx_cmd) +
1291 sizeof(struct iwl_cmd_header) + hdr_len;
1292 firstlen = (len + 3) & ~3;
1293
1294 /* Tell NIC about any 2-byte padding after MAC header */
1295 if (firstlen != len)
1296 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1297
1298 /* Physical address of this Tx command's header (not MAC header!),
1299 * within command buffer array. */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001300 txcmd_phys = dma_map_single(trans->dev,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001301 &dev_cmd->hdr, firstlen,
1302 DMA_BIDIRECTIONAL);
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001303 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
Johannes Berg015c15e2012-03-05 11:24:24 -08001304 goto out_err;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001305 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1306 dma_unmap_len_set(out_meta, len, firstlen);
1307
1308 if (!ieee80211_has_morefrags(fc)) {
1309 txq->need_update = 1;
1310 } else {
1311 wait_write_ptr = 1;
1312 txq->need_update = 0;
1313 }
1314
1315 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1316 * if any (802.11 null frames have no payload). */
1317 secondlen = skb->len - hdr_len;
1318 if (secondlen > 0) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001319 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001320 secondlen, DMA_TO_DEVICE);
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001321 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1322 dma_unmap_single(trans->dev,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001323 dma_unmap_addr(out_meta, mapping),
1324 dma_unmap_len(out_meta, len),
1325 DMA_BIDIRECTIONAL);
Johannes Berg015c15e2012-03-05 11:24:24 -08001326 goto out_err;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001327 }
1328 }
1329
1330 /* Attach buffers to TFD */
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001331 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001332 if (secondlen > 0)
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001333 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001334 secondlen, 0);
1335
1336 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1337 offsetof(struct iwl_tx_cmd, scratch);
1338
1339 /* take back ownership of DMA buffer to enable update */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001340 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001341 DMA_BIDIRECTIONAL);
1342 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1343 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1344
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001345 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001346 le16_to_cpu(dev_cmd->hdr.sequence));
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001347 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001348
1349 /* Set up entry for this TFD in Tx byte-count array */
Emmanuel Grumbach96f1f052011-12-16 07:53:18 -08001350 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001351
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001352 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001353 DMA_BIDIRECTIONAL);
1354
Johannes Berg6c1011e2012-03-06 13:30:48 -08001355 trace_iwlwifi_dev_tx(trans->dev,
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001356 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1357 sizeof(struct iwl_tfd),
1358 &dev_cmd->hdr, firstlen,
1359 skb->data + hdr_len, secondlen);
1360
Johannes Berg7c5ba4a2012-04-09 17:46:54 -07001361 /* start timer if queue currently empty */
1362 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1363 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1364
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001365 /* Tell device the write index *just past* this latest filled TFD */
1366 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001367 iwl_txq_update_write_ptr(trans, txq);
1368
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001369 /*
1370 * At this point the frame is "transmitted" successfully
1371 * and we will get a TX status notification eventually,
1372 * regardless of the value of ret. "ret" only indicates
1373 * whether or not we should update the write pointer.
1374 */
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001375 if (iwl_queue_space(q) < q->high_mark) {
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001376 if (wait_write_ptr) {
1377 txq->need_update = 1;
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -07001378 iwl_txq_update_write_ptr(trans, txq);
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001379 } else {
Johannes Bergbada9912012-03-07 09:52:39 -08001380 iwl_stop_queue(trans, txq);
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001381 }
1382 }
Johannes Berg015c15e2012-03-05 11:24:24 -08001383 spin_unlock(&txq->lock);
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001384 return 0;
Johannes Berg015c15e2012-03-05 11:24:24 -08001385 out_err:
1386 spin_unlock(&txq->lock);
1387 return -1;
Emmanuel Grumbach47c1b492011-07-03 11:22:15 +03001388}
1389
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001390static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
Emmanuel Grumbacha27367d2011-07-04 09:06:44 +03001391{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001392 struct iwl_trans_pcie *trans_pcie =
1393 IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach34c1b7b2011-07-04 08:58:19 +03001394 int err;
Johannes Bergc9eec952012-03-06 13:30:43 -08001395 bool hw_rfkill;
Emmanuel Grumbach34c1b7b2011-07-04 08:58:19 +03001396
Emmanuel Grumbach0c325762011-08-25 23:10:53 -07001397 trans_pcie->inta_mask = CSR_INI_SET_MASK;
Emmanuel Grumbach1e89cbac2011-07-20 17:51:22 -07001398
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001399 if (!trans_pcie->irq_requested) {
1400 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1401 iwl_irq_tasklet, (unsigned long)trans);
Emmanuel Grumbach0c325762011-08-25 23:10:53 -07001402
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001403 iwl_alloc_isr_ict(trans);
Emmanuel Grumbach34c1b7b2011-07-04 08:58:19 +03001404
Johannes Berg75595532012-03-06 13:31:01 -08001405 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001406 DRV_NAME, trans);
1407 if (err) {
1408 IWL_ERR(trans, "Error allocating IRQ %d\n",
Johannes Berg75595532012-03-06 13:31:01 -08001409 trans_pcie->irq);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001410 goto error;
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001411 }
1412
1413 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1414 trans_pcie->irq_requested = true;
Emmanuel Grumbach34c1b7b2011-07-04 08:58:19 +03001415 }
1416
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001417 err = iwl_prepare_card_hw(trans);
1418 if (err) {
1419 IWL_ERR(trans, "Error while preparing HW: %d", err);
Johannes Bergf057ac42012-01-29 18:36:01 -08001420 goto err_free_irq;
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001421 }
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +02001422
1423 iwl_apm_init(trans);
1424
Emmanuel Grumbach226c02c2012-03-28 10:33:09 +02001425 /* From now on, the op_mode will be kept updated about RF kill state */
1426 iwl_enable_rfkill_int(trans);
1427
Emmanuel Grumbach8d425512012-03-28 11:00:58 +02001428 hw_rfkill = iwl_is_rfkill_set(trans);
Johannes Bergc9eec952012-03-06 13:30:43 -08001429 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
Emmanuel Grumbachd48e2072012-01-08 13:48:21 +02001430
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001431 return err;
1432
Johannes Bergf057ac42012-01-29 18:36:01 -08001433err_free_irq:
Johannes Berg75595532012-03-06 13:31:01 -08001434 free_irq(trans_pcie->irq, trans);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +02001435error:
1436 iwl_free_isr_ict(trans);
1437 tasklet_kill(&trans_pcie->irq_tasklet);
1438 return err;
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03001439}
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001440
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001441static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1442 bool op_mode_leaving)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001443{
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +02001444 bool hw_rfkill;
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001445 unsigned long flags;
1446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +02001447
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001448 iwl_apm_stop(trans);
1449
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001450 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1451 iwl_disable_interrupts(trans);
1452 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1453
Emmanuel Grumbach1df06bd2012-01-09 16:35:08 +02001454 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1455
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001456 if (!op_mode_leaving) {
1457 /*
1458 * Even if we stop the HW, we still want the RF kill
1459 * interrupt
1460 */
1461 iwl_enable_rfkill_int(trans);
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +02001462
Emmanuel Grumbach218733c2012-03-31 08:28:38 -07001463 /*
1464 * Check again since the RF kill state may have changed while
1465 * all the interrupts were disabled, in this case we couldn't
1466 * receive the RF kill interrupt and update the state in the
1467 * op_mode.
1468 */
1469 hw_rfkill = iwl_is_rfkill_set(trans);
1470 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1471 }
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001472}
1473
Johannes Berg9eae88f2012-03-15 13:26:52 -07001474static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1475 struct sk_buff_head *skbs)
Emmanuel Grumbach464021f2011-08-25 23:11:26 -07001476{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001477 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1478 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001479 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1480 int tfd_num = ssn & (txq->q.n_bd - 1);
Emmanuel Grumbach464021f2011-08-25 23:11:26 -07001481 int freed = 0;
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001482
Johannes Berg015c15e2012-03-05 11:24:24 -08001483 spin_lock(&txq->lock);
1484
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001485 if (txq->q.read_ptr != tfd_num) {
Johannes Berg9eae88f2012-03-15 13:26:52 -07001486 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1487 txq_id, txq->q.read_ptr, tfd_num, ssn);
Emmanuel Grumbach464021f2011-08-25 23:11:26 -07001488 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
Johannes Berge755f882012-03-07 09:52:16 -08001489 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
Johannes Bergbada9912012-03-07 09:52:39 -08001490 iwl_wake_queue(trans, txq);
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001491 }
Johannes Berg015c15e2012-03-05 11:24:24 -08001492
1493 spin_unlock(&txq->lock);
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001494}
1495
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001496static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1497{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001498 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001499}
1500
1501static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1502{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001503 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001504}
1505
1506static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1507{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001508 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001509}
1510
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001511static void iwl_trans_pcie_configure(struct iwl_trans *trans,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001512 const struct iwl_trans_config *trans_cfg)
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001513{
1514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1515
1516 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
Johannes Bergd663ee72012-03-10 13:00:07 -08001517 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1518 trans_pcie->n_no_reclaim_cmds = 0;
1519 else
1520 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1521 if (trans_pcie->n_no_reclaim_cmds)
1522 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1523 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
Johannes Berg9eae88f2012-03-15 13:26:52 -07001524
1525 trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1526
1527 if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1528 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1529
1530 /* at least the command queue must be mapped */
1531 WARN_ON(!trans_pcie->n_q_to_fifo);
1532
1533 memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1534 trans_pcie->n_q_to_fifo * sizeof(u8));
Johannes Bergb2cf4102012-04-09 17:46:51 -07001535
1536 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1537 if (trans_pcie->rx_buf_size_8k)
1538 trans_pcie->rx_page_order = get_order(8 * 1024);
1539 else
1540 trans_pcie->rx_page_order = get_order(4 * 1024);
Johannes Berg7c5ba4a2012-04-09 17:46:54 -07001541
1542 trans_pcie->wd_timeout =
1543 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
Johannes Bergd9fb6462012-03-26 08:23:39 -07001544
1545 trans_pcie->command_names = trans_cfg->command_names;
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001546}
1547
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001548static void iwl_trans_pcie_free(struct iwl_trans *trans)
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001549{
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001550 struct iwl_trans_pcie *trans_pcie =
1551 IWL_TRANS_GET_PCIE_TRANS(trans);
1552
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001553 iwl_trans_pcie_tx_free(trans);
Gregory Greenmana5916972012-01-10 19:22:56 +02001554#ifndef CONFIG_IWLWIFI_IDI
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -07001555 iwl_trans_pcie_rx_free(trans);
Gregory Greenmana5916972012-01-10 19:22:56 +02001556#endif
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001557 if (trans_pcie->irq_requested == true) {
Johannes Berg75595532012-03-06 13:31:01 -08001558 free_irq(trans_pcie->irq, trans);
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001559 iwl_free_isr_ict(trans);
1560 }
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001561
1562 pci_disable_msi(trans_pcie->pci_dev);
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001563 iounmap(trans_pcie->hw_base);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001564 pci_release_regions(trans_pcie->pci_dev);
1565 pci_disable_device(trans_pcie->pci_dev);
1566
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001567 kfree(trans);
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001568}
1569
Don Fry47107e82012-03-15 13:27:06 -07001570static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1571{
1572 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1573
1574 if (state)
Don Fry01d651d2012-03-23 08:34:31 -07001575 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
Don Fry47107e82012-03-15 13:27:06 -07001576 else
Don Fry01d651d2012-03-23 08:34:31 -07001577 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
Don Fry47107e82012-03-15 13:27:06 -07001578}
1579
Johannes Bergc01a4042011-09-15 11:46:45 -07001580#ifdef CONFIG_PM_SLEEP
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001581static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1582{
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001583 return 0;
1584}
1585
1586static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1587{
Johannes Bergc9eec952012-03-06 13:30:43 -08001588 bool hw_rfkill;
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001589
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +02001590 iwl_enable_rfkill_int(trans);
1591
Emmanuel Grumbach8d425512012-03-28 11:00:58 +02001592 hw_rfkill = iwl_is_rfkill_set(trans);
Emmanuel Grumbach7120d982012-02-09 16:08:15 +02001593 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001594
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +02001595 if (!hw_rfkill)
1596 iwl_enable_interrupts(trans);
1597
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001598 return 0;
1599}
Johannes Bergc01a4042011-09-15 11:46:45 -07001600#endif /* CONFIG_PM_SLEEP */
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001601
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001602#define IWL_FLUSH_WAIT_MS 2000
1603
1604static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1605{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001606 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001607 struct iwl_tx_queue *txq;
1608 struct iwl_queue *q;
1609 int cnt;
1610 unsigned long now = jiffies;
1611 int ret = 0;
1612
1613 /* waiting for all the tx frames complete might take a while */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001614 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
Wey-Yi Guy9ba19472012-03-09 10:12:42 -08001615 if (cnt == trans_pcie->cmd_queue)
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001616 continue;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001617 txq = &trans_pcie->txq[cnt];
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001618 q = &txq->q;
1619 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1620 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1621 msleep(1);
1622
1623 if (q->read_ptr != q->write_ptr) {
1624 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1625 ret = -ETIMEDOUT;
1626 break;
1627 }
1628 }
1629 return ret;
1630}
1631
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001632static const char *get_fh_string(int cmd)
1633{
Johannes Bergd9fb6462012-03-26 08:23:39 -07001634#define IWL_CMD(x) case x: return #x
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001635 switch (cmd) {
1636 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1637 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1638 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1639 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1640 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1641 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1642 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1643 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1644 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1645 default:
1646 return "UNKNOWN";
1647 }
Johannes Bergd9fb6462012-03-26 08:23:39 -07001648#undef IWL_CMD
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001649}
1650
1651int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1652{
1653 int i;
1654#ifdef CONFIG_IWLWIFI_DEBUG
1655 int pos = 0;
1656 size_t bufsz = 0;
1657#endif
1658 static const u32 fh_tbl[] = {
1659 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1660 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1661 FH_RSCSR_CHNL0_WPTR,
1662 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1663 FH_MEM_RSSR_SHARED_CTRL_REG,
1664 FH_MEM_RSSR_RX_STATUS_REG,
1665 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1666 FH_TSSR_TX_STATUS_REG,
1667 FH_TSSR_TX_ERROR_REG
1668 };
1669#ifdef CONFIG_IWLWIFI_DEBUG
1670 if (display) {
1671 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1672 *buf = kmalloc(bufsz, GFP_KERNEL);
1673 if (!*buf)
1674 return -ENOMEM;
1675 pos += scnprintf(*buf + pos, bufsz - pos,
1676 "FH register values:\n");
1677 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1678 pos += scnprintf(*buf + pos, bufsz - pos,
1679 " %34s: 0X%08x\n",
1680 get_fh_string(fh_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001681 iwl_read_direct32(trans, fh_tbl[i]));
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001682 }
1683 return pos;
1684 }
1685#endif
1686 IWL_ERR(trans, "FH register values:\n");
1687 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1688 IWL_ERR(trans, " %34s: 0X%08x\n",
1689 get_fh_string(fh_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001690 iwl_read_direct32(trans, fh_tbl[i]));
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001691 }
1692 return 0;
1693}
1694
1695static const char *get_csr_string(int cmd)
1696{
Johannes Bergd9fb6462012-03-26 08:23:39 -07001697#define IWL_CMD(x) case x: return #x
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001698 switch (cmd) {
1699 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1700 IWL_CMD(CSR_INT_COALESCING);
1701 IWL_CMD(CSR_INT);
1702 IWL_CMD(CSR_INT_MASK);
1703 IWL_CMD(CSR_FH_INT_STATUS);
1704 IWL_CMD(CSR_GPIO_IN);
1705 IWL_CMD(CSR_RESET);
1706 IWL_CMD(CSR_GP_CNTRL);
1707 IWL_CMD(CSR_HW_REV);
1708 IWL_CMD(CSR_EEPROM_REG);
1709 IWL_CMD(CSR_EEPROM_GP);
1710 IWL_CMD(CSR_OTP_GP_REG);
1711 IWL_CMD(CSR_GIO_REG);
1712 IWL_CMD(CSR_GP_UCODE_REG);
1713 IWL_CMD(CSR_GP_DRIVER_REG);
1714 IWL_CMD(CSR_UCODE_DRV_GP1);
1715 IWL_CMD(CSR_UCODE_DRV_GP2);
1716 IWL_CMD(CSR_LED_REG);
1717 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1718 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1719 IWL_CMD(CSR_ANA_PLL_CFG);
1720 IWL_CMD(CSR_HW_REV_WA_REG);
1721 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1722 default:
1723 return "UNKNOWN";
1724 }
Johannes Bergd9fb6462012-03-26 08:23:39 -07001725#undef IWL_CMD
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001726}
1727
1728void iwl_dump_csr(struct iwl_trans *trans)
1729{
1730 int i;
1731 static const u32 csr_tbl[] = {
1732 CSR_HW_IF_CONFIG_REG,
1733 CSR_INT_COALESCING,
1734 CSR_INT,
1735 CSR_INT_MASK,
1736 CSR_FH_INT_STATUS,
1737 CSR_GPIO_IN,
1738 CSR_RESET,
1739 CSR_GP_CNTRL,
1740 CSR_HW_REV,
1741 CSR_EEPROM_REG,
1742 CSR_EEPROM_GP,
1743 CSR_OTP_GP_REG,
1744 CSR_GIO_REG,
1745 CSR_GP_UCODE_REG,
1746 CSR_GP_DRIVER_REG,
1747 CSR_UCODE_DRV_GP1,
1748 CSR_UCODE_DRV_GP2,
1749 CSR_LED_REG,
1750 CSR_DRAM_INT_TBL_REG,
1751 CSR_GIO_CHICKEN_BITS,
1752 CSR_ANA_PLL_CFG,
1753 CSR_HW_REV_WA_REG,
1754 CSR_DBG_HPET_MEM_REG
1755 };
1756 IWL_ERR(trans, "CSR values:\n");
1757 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1758 "CSR_INT_PERIODIC_REG)\n");
1759 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1760 IWL_ERR(trans, " %25s: 0X%08x\n",
1761 get_csr_string(csr_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001762 iwl_read32(trans, csr_tbl[i]));
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001763 }
1764}
1765
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001766#ifdef CONFIG_IWLWIFI_DEBUGFS
1767/* create and remove of files */
1768#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001769 if (!debugfs_create_file(#name, mode, parent, trans, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001770 &iwl_dbgfs_##name##_ops)) \
1771 return -ENOMEM; \
1772} while (0)
1773
1774/* file operation */
1775#define DEBUGFS_READ_FUNC(name) \
1776static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1777 char __user *user_buf, \
1778 size_t count, loff_t *ppos);
1779
1780#define DEBUGFS_WRITE_FUNC(name) \
1781static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1782 const char __user *user_buf, \
1783 size_t count, loff_t *ppos);
1784
1785
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001786#define DEBUGFS_READ_FILE_OPS(name) \
1787 DEBUGFS_READ_FUNC(name); \
1788static const struct file_operations iwl_dbgfs_##name##_ops = { \
1789 .read = iwl_dbgfs_##name##_read, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001790 .open = simple_open, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001791 .llseek = generic_file_llseek, \
1792};
1793
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001794#define DEBUGFS_WRITE_FILE_OPS(name) \
1795 DEBUGFS_WRITE_FUNC(name); \
1796static const struct file_operations iwl_dbgfs_##name##_ops = { \
1797 .write = iwl_dbgfs_##name##_write, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001798 .open = simple_open, \
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001799 .llseek = generic_file_llseek, \
1800};
1801
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001802#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1803 DEBUGFS_READ_FUNC(name); \
1804 DEBUGFS_WRITE_FUNC(name); \
1805static const struct file_operations iwl_dbgfs_##name##_ops = { \
1806 .write = iwl_dbgfs_##name##_write, \
1807 .read = iwl_dbgfs_##name##_read, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001808 .open = simple_open, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001809 .llseek = generic_file_llseek, \
1810};
1811
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001812static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1813 char __user *user_buf,
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001814 size_t count, loff_t *ppos)
1815{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001816 struct iwl_trans *trans = file->private_data;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001817 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001818 struct iwl_tx_queue *txq;
1819 struct iwl_queue *q;
1820 char *buf;
1821 int pos = 0;
1822 int cnt;
1823 int ret;
Wey-Yi Guy1745e4402012-03-09 11:13:40 -08001824 size_t bufsz;
1825
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001826 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001827
Johannes Bergf9e75442012-03-30 09:37:39 +02001828 if (!trans_pcie->txq)
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001829 return -EAGAIN;
Johannes Bergf9e75442012-03-30 09:37:39 +02001830
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001831 buf = kzalloc(bufsz, GFP_KERNEL);
1832 if (!buf)
1833 return -ENOMEM;
1834
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001835 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001836 txq = &trans_pcie->txq[cnt];
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001837 q = &txq->q;
1838 pos += scnprintf(buf + pos, bufsz - pos,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001839 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001840 cnt, q->read_ptr, q->write_ptr,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001841 !!test_bit(cnt, trans_pcie->queue_used),
1842 !!test_bit(cnt, trans_pcie->queue_stopped));
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001843 }
1844 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1845 kfree(buf);
1846 return ret;
1847}
1848
1849static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1850 char __user *user_buf,
1851 size_t count, loff_t *ppos) {
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001852 struct iwl_trans *trans = file->private_data;
1853 struct iwl_trans_pcie *trans_pcie =
1854 IWL_TRANS_GET_PCIE_TRANS(trans);
1855 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001856 char buf[256];
1857 int pos = 0;
1858 const size_t bufsz = sizeof(buf);
1859
1860 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1861 rxq->read);
1862 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1863 rxq->write);
1864 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1865 rxq->free_count);
1866 if (rxq->rb_stts) {
1867 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1868 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1869 } else {
1870 pos += scnprintf(buf + pos, bufsz - pos,
1871 "closed_rb_num: Not Allocated\n");
1872 }
1873 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1874}
1875
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001876static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1877 char __user *user_buf,
1878 size_t count, loff_t *ppos) {
1879
1880 struct iwl_trans *trans = file->private_data;
1881 struct iwl_trans_pcie *trans_pcie =
1882 IWL_TRANS_GET_PCIE_TRANS(trans);
1883 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1884
1885 int pos = 0;
1886 char *buf;
1887 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1888 ssize_t ret;
1889
1890 buf = kzalloc(bufsz, GFP_KERNEL);
Johannes Bergf9e75442012-03-30 09:37:39 +02001891 if (!buf)
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001892 return -ENOMEM;
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001893
1894 pos += scnprintf(buf + pos, bufsz - pos,
1895 "Interrupt Statistics Report:\n");
1896
1897 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1898 isr_stats->hw);
1899 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1900 isr_stats->sw);
1901 if (isr_stats->sw || isr_stats->hw) {
1902 pos += scnprintf(buf + pos, bufsz - pos,
1903 "\tLast Restarting Code: 0x%X\n",
1904 isr_stats->err_code);
1905 }
1906#ifdef CONFIG_IWLWIFI_DEBUG
1907 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1908 isr_stats->sch);
1909 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1910 isr_stats->alive);
1911#endif
1912 pos += scnprintf(buf + pos, bufsz - pos,
1913 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1914
1915 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1916 isr_stats->ctkill);
1917
1918 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1919 isr_stats->wakeup);
1920
1921 pos += scnprintf(buf + pos, bufsz - pos,
1922 "Rx command responses:\t\t %u\n", isr_stats->rx);
1923
1924 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1925 isr_stats->tx);
1926
1927 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1928 isr_stats->unhandled);
1929
1930 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1931 kfree(buf);
1932 return ret;
1933}
1934
1935static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1936 const char __user *user_buf,
1937 size_t count, loff_t *ppos)
1938{
1939 struct iwl_trans *trans = file->private_data;
1940 struct iwl_trans_pcie *trans_pcie =
1941 IWL_TRANS_GET_PCIE_TRANS(trans);
1942 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1943
1944 char buf[8];
1945 int buf_size;
1946 u32 reset_flag;
1947
1948 memset(buf, 0, sizeof(buf));
1949 buf_size = min(count, sizeof(buf) - 1);
1950 if (copy_from_user(buf, user_buf, buf_size))
1951 return -EFAULT;
1952 if (sscanf(buf, "%x", &reset_flag) != 1)
1953 return -EFAULT;
1954 if (reset_flag == 0)
1955 memset(isr_stats, 0, sizeof(*isr_stats));
1956
1957 return count;
1958}
1959
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001960static ssize_t iwl_dbgfs_csr_write(struct file *file,
1961 const char __user *user_buf,
1962 size_t count, loff_t *ppos)
1963{
1964 struct iwl_trans *trans = file->private_data;
1965 char buf[8];
1966 int buf_size;
1967 int csr;
1968
1969 memset(buf, 0, sizeof(buf));
1970 buf_size = min(count, sizeof(buf) - 1);
1971 if (copy_from_user(buf, user_buf, buf_size))
1972 return -EFAULT;
1973 if (sscanf(buf, "%d", &csr) != 1)
1974 return -EFAULT;
1975
1976 iwl_dump_csr(trans);
1977
1978 return count;
1979}
1980
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001981static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1982 char __user *user_buf,
1983 size_t count, loff_t *ppos)
1984{
1985 struct iwl_trans *trans = file->private_data;
1986 char *buf;
1987 int pos = 0;
1988 ssize_t ret = -EFAULT;
1989
1990 ret = pos = iwl_dump_fh(trans, &buf, true);
1991 if (buf) {
1992 ret = simple_read_from_buffer(user_buf,
1993 count, ppos, buf, pos);
1994 kfree(buf);
1995 }
1996
1997 return ret;
1998}
1999
Johannes Berg48dffd32012-04-09 17:46:57 -07002000static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2001 const char __user *user_buf,
2002 size_t count, loff_t *ppos)
2003{
2004 struct iwl_trans *trans = file->private_data;
2005
2006 if (!trans->op_mode)
2007 return -EAGAIN;
2008
2009 iwl_op_mode_nic_error(trans->op_mode);
2010
2011 return count;
2012}
2013
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07002014DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002015DEBUGFS_READ_FILE_OPS(fh_reg);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002016DEBUGFS_READ_FILE_OPS(rx_queue);
2017DEBUGFS_READ_FILE_OPS(tx_queue);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002018DEBUGFS_WRITE_FILE_OPS(csr);
Johannes Berg48dffd32012-04-09 17:46:57 -07002019DEBUGFS_WRITE_FILE_OPS(fw_restart);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002020
2021/*
2022 * Create the debugfs files and directories
2023 *
2024 */
2025static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2026 struct dentry *dir)
2027{
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002028 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2029 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07002030 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07002031 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2032 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
Johannes Berg48dffd32012-04-09 17:46:57 -07002033 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002034 return 0;
2035}
2036#else
2037static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2038 struct dentry *dir)
2039{ return 0; }
2040
2041#endif /*CONFIG_IWLWIFI_DEBUGFS */
2042
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002043const struct iwl_trans_ops trans_ops_pcie = {
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02002044 .start_hw = iwl_trans_pcie_start_hw,
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02002045 .stop_hw = iwl_trans_pcie_stop_hw,
Emmanuel Grumbached6a3802012-01-02 16:10:08 +02002046 .fw_alive = iwl_trans_pcie_fw_alive,
Emmanuel Grumbachcf614292012-01-08 16:33:58 +02002047 .start_fw = iwl_trans_pcie_start_fw,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002048 .stop_device = iwl_trans_pcie_stop_device,
2049
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08002050 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2051
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002052 .send_cmd = iwl_trans_pcie_send_cmd,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002053
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002054 .tx = iwl_trans_pcie_tx,
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07002055 .reclaim = iwl_trans_pcie_reclaim,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002056
Emmanuel Grumbach7f01d562011-08-25 23:11:27 -07002057 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
Emmanuel Grumbachc91bd122011-08-25 23:11:28 -07002058 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002059
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002060 .free = iwl_trans_pcie_free,
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07002061
2062 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07002063
2064 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2065
Johannes Bergc01a4042011-09-15 11:46:45 -07002066#ifdef CONFIG_PM_SLEEP
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07002067 .suspend = iwl_trans_pcie_suspend,
2068 .resume = iwl_trans_pcie_resume,
Johannes Bergc01a4042011-09-15 11:46:45 -07002069#endif
Emmanuel Grumbach03905492012-01-03 13:48:07 +02002070 .write8 = iwl_trans_pcie_write8,
2071 .write32 = iwl_trans_pcie_write32,
2072 .read32 = iwl_trans_pcie_read32,
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08002073 .configure = iwl_trans_pcie_configure,
Don Fry47107e82012-03-15 13:27:06 -07002074 .set_pmi = iwl_trans_pcie_set_pmi,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07002075};
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002076
Emmanuel Grumbach87ce05a2012-03-26 09:03:18 -07002077struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07002078 const struct pci_device_id *ent,
2079 const struct iwl_cfg *cfg)
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002080{
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002081 struct iwl_trans_pcie *trans_pcie;
2082 struct iwl_trans *trans;
2083 u16 pci_cmd;
2084 int err;
2085
2086 trans = kzalloc(sizeof(struct iwl_trans) +
2087 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2088
2089 if (WARN_ON(!trans))
2090 return NULL;
2091
2092 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2093
2094 trans->ops = &trans_ops_pcie;
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07002095 trans->cfg = cfg;
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002096 trans_pcie->trans = trans;
Johannes Berg7b114882012-02-05 13:55:11 -08002097 spin_lock_init(&trans_pcie->irq_lock);
Johannes Berg13df1aa2012-03-06 13:31:00 -08002098 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002099
2100 /* W/A - seems to solve weird behavior. We need to remove this if we
2101 * don't want to stay in L1 all the time. This wastes a lot of power */
2102 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2103 PCIE_LINK_STATE_CLKPM);
2104
2105 if (pci_enable_device(pdev)) {
2106 err = -ENODEV;
2107 goto out_no_pci;
2108 }
2109
2110 pci_set_master(pdev);
2111
2112 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2113 if (!err)
2114 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2115 if (err) {
2116 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2117 if (!err)
2118 err = pci_set_consistent_dma_mask(pdev,
2119 DMA_BIT_MASK(32));
2120 /* both attempts failed: */
2121 if (err) {
2122 dev_printk(KERN_ERR, &pdev->dev,
2123 "No suitable DMA available.\n");
2124 goto out_pci_disable_device;
2125 }
2126 }
2127
2128 err = pci_request_regions(pdev, DRV_NAME);
2129 if (err) {
2130 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2131 goto out_pci_disable_device;
2132 }
2133
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08002134 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002135 if (!trans_pcie->hw_base) {
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08002136 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002137 err = -ENODEV;
2138 goto out_pci_release_regions;
2139 }
2140
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002141 dev_printk(KERN_INFO, &pdev->dev,
2142 "pci_resource_len = 0x%08llx\n",
2143 (unsigned long long) pci_resource_len(pdev, 0));
2144 dev_printk(KERN_INFO, &pdev->dev,
2145 "pci_resource_base = %p\n", trans_pcie->hw_base);
2146
2147 dev_printk(KERN_INFO, &pdev->dev,
2148 "HW Revision ID = 0x%X\n", pdev->revision);
2149
2150 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2151 * PCI Tx retries from interfering with C3 CPU state */
2152 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2153
2154 err = pci_enable_msi(pdev);
2155 if (err)
2156 dev_printk(KERN_ERR, &pdev->dev,
2157 "pci_enable_msi failed(0X%x)", err);
2158
2159 trans->dev = &pdev->dev;
Johannes Berg75595532012-03-06 13:31:01 -08002160 trans_pcie->irq = pdev->irq;
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002161 trans_pcie->pci_dev = pdev;
Emmanuel Grumbach08079a42012-01-09 16:23:00 +02002162 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
Emmanuel Grumbach99673ee2012-01-08 21:19:45 +02002163 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
Emmanuel Grumbach9ca85962012-01-08 21:19:45 +02002164 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2165 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002166
2167 /* TODO: Move this away, not needed if not MSI */
2168 /* enable rfkill interrupt: hw bug w/a */
2169 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2170 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2171 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2172 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2173 }
2174
Meenakshi Venkataraman69a10b22012-03-10 13:00:09 -08002175 /* Initialize the wait queue for commands */
2176 init_waitqueue_head(&trans->wait_command_queue);
2177
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08002178 return trans;
2179
2180out_pci_release_regions:
2181 pci_release_regions(pdev);
2182out_pci_disable_device:
2183 pci_disable_device(pdev);
2184out_no_pci:
2185 kfree(trans);
2186 return NULL;
2187}
2188