blob: 1e528dbb7323f16a3237607694c9f0fa78b4f2e4 [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080021 serial0 = &auart0;
22 serial1 = &auart1;
Shawn Guoce4c6f92012-05-04 14:32:35 +080023 };
24
Shawn Guo2954ff32012-05-04 21:33:42 +080025 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010026 #address-cells = <0>;
27 #size-cells = <0>;
28
29 cpu {
30 compatible = "arm,arm926ej-s";
31 device_type = "cpu";
Shawn Guo2954ff32012-05-04 21:33:42 +080032 };
33 };
34
35 apb@80000000 {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x80000000 0x80000>;
40 ranges;
41
42 apbh@80000000 {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 reg = <0x80000000 0x40000>;
47 ranges;
48
49 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +080050 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +080051 interrupt-controller;
52 #interrupt-cells = <1>;
53 reg = <0x80000000 0x2000>;
54 };
55
Shawn Guof30fb032013-02-25 21:56:56 +080056 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080057 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -030058 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +080059 interrupts = <0 14 20 0
60 13 13 13 13>;
61 interrupt-names = "empty", "ssp0", "ssp1", "empty",
62 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
63 #dma-cells = <1>;
64 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +080065 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +080066 };
67
68 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030069 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080070 status = "disabled";
71 };
72
Marek Vasuta217c462012-06-09 01:21:55 +020073 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +080074 compatible = "fsl,imx23-gpmi-nand";
75 #address-cells = <1>;
76 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -030077 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080078 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +080079 interrupts = <56>;
80 interrupt-names = "bch";
Shawn Guo53f94432012-08-22 21:36:30 +080081 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +080082 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +080083 dmas = <&dma_apbh 4>;
84 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +080085 status = "disabled";
86 };
87
88 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030089 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +080090 interrupts = <15>;
Shawn Guo53f94432012-08-22 21:36:30 +080091 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +080092 dmas = <&dma_apbh 1>;
93 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +080094 status = "disabled";
95 };
96
97 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030098 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080099 status = "disabled";
100 };
101
102 pinctrl@80018000 {
103 #address-cells = <1>;
104 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800105 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300106 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800107
Shawn Guoce4c6f92012-05-04 14:32:35 +0800108 gpio0: gpio@0 {
109 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
110 interrupts = <16>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116
117 gpio1: gpio@1 {
118 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
119 interrupts = <17>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio2: gpio@2 {
127 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
128 interrupts = <18>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
Shawn Guo2954ff32012-05-04 21:33:42 +0800135 duart_pins_a: duart@0 {
136 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800137 fsl,pinmux-ids = <
138 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
139 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
140 >;
Shawn Guo2954ff32012-05-04 21:33:42 +0800141 fsl,drive-strength = <0>;
142 fsl,voltage = <1>;
143 fsl,pull-up = <0>;
144 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800145
Shawn Guoa4508392012-06-28 11:45:00 +0800146 auart0_pins_a: auart0@0 {
147 reg = <0>;
148 fsl,pinmux-ids = <
149 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
150 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
151 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
152 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
153 >;
154 fsl,drive-strength = <0>;
155 fsl,voltage = <1>;
156 fsl,pull-up = <0>;
157 };
158
Fabio Estevam98916a22012-07-30 16:33:44 -0300159 auart0_2pins_a: auart0-2pins@0 {
160 reg = <0>;
161 fsl,pinmux-ids = <
162 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
163 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
164 >;
165 fsl,drive-strength = <0>;
166 fsl,voltage = <1>;
167 fsl,pull-up = <0>;
168 };
169
Huang Shijieb9f25f82012-07-03 12:58:13 +0800170 gpmi_pins_a: gpmi-nand@0 {
171 reg = <0>;
172 fsl,pinmux-ids = <
173 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
174 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
175 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
176 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
177 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
178 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
179 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
180 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
181 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
182 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
183 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
184 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
185 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
186 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
187 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
188 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
189 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
190 >;
191 fsl,drive-strength = <0>;
192 fsl,voltage = <1>;
193 fsl,pull-up = <0>;
194 };
195
196 gpmi_pins_fixup: gpmi-pins-fixup {
197 fsl,pinmux-ids = <
198 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
199 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
200 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
201 >;
202 fsl,drive-strength = <2>;
203 };
204
Shawn Guo72beaba2012-06-28 11:44:59 +0800205 mmc0_4bit_pins_a: mmc0-4bit@0 {
206 reg = <0>;
207 fsl,pinmux-ids = <
208 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
209 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
210 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
211 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
212 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
Shawn Guo72beaba2012-06-28 11:44:59 +0800213 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
214 >;
215 fsl,drive-strength = <1>;
216 fsl,voltage = <1>;
217 fsl,pull-up = <1>;
218 };
219
Shawn Guobe1ce302012-05-06 16:29:36 +0800220 mmc0_8bit_pins_a: mmc0-8bit@0 {
221 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800222 fsl,pinmux-ids = <
223 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
224 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
225 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
226 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
227 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
228 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
229 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
230 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
231 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
232 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
233 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
234 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800235 fsl,drive-strength = <1>;
236 fsl,voltage = <1>;
237 fsl,pull-up = <1>;
238 };
239
240 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800241 fsl,pinmux-ids = <
242 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
243 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
244 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800245 fsl,pull-up = <0>;
246 };
Shawn Guo52f71762012-06-28 11:45:06 +0800247
248 pwm2_pins_a: pwm2@0 {
249 reg = <0>;
250 fsl,pinmux-ids = <
251 0x11c0 /* MX23_PAD_PWM2__PWM2 */
252 >;
253 fsl,drive-strength = <0>;
254 fsl,voltage = <1>;
255 fsl,pull-up = <0>;
256 };
Shawn Guoa915ee422012-06-28 11:45:07 +0800257
258 lcdif_24bit_pins_a: lcdif-24bit@0 {
259 reg = <0>;
260 fsl,pinmux-ids = <
261 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
262 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
263 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
264 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
265 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
266 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
267 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
268 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
269 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
270 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
271 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
272 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
273 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
274 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
275 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
276 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
277 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
278 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
279 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
280 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
281 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
282 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
283 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
284 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
285 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
286 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
287 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
288 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
289 >;
290 fsl,drive-strength = <0>;
291 fsl,voltage = <1>;
292 fsl,pull-up = <0>;
293 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500294
295 spi2_pins_a: spi2@0 {
296 reg = <0>;
297 fsl,pinmux-ids = <
298 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
299 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
300 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
301 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
302 >;
303 fsl,drive-strength = <1>;
304 fsl,voltage = <1>;
305 fsl,pull-up = <1>;
306 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800307 };
308
309 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800310 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800311 reg = <0x8001c000 2000>;
312 status = "disabled";
313 };
314
315 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300316 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800317 status = "disabled";
318 };
319
Shawn Guof30fb032013-02-25 21:56:56 +0800320 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800321 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300322 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800323 interrupts = <7 5 9 26
324 19 0 25 23
325 60 58 9 0
326 0 0 0 0>;
327 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
328 "saif0", "empty", "auart0-rx", "auart0-tx",
329 "auart1-rx", "auart1-tx", "saif1", "empty",
330 "empty", "empty", "empty", "empty";
331 #dma-cells = <1>;
332 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800333 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800334 };
335
336 dcp@80028000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300337 reg = <0x80028000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800338 status = "disabled";
339 };
340
341 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300342 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800343 status = "disabled";
344 };
345
346 ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800347 compatible = "fsl,ocotp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300348 reg = <0x8002c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800349 status = "disabled";
350 };
351
352 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300353 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800354 status = "disabled";
355 };
356
357 lcdif@80030000 {
Shawn Guoa915ee422012-06-28 11:45:07 +0800358 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800359 reg = <0x80030000 2000>;
Shawn Guoa915ee422012-06-28 11:45:07 +0800360 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800361 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800362 status = "disabled";
363 };
364
365 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300366 reg = <0x80034000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800367 interrupts = <2>;
Shawn Guo53f94432012-08-22 21:36:30 +0800368 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800369 dmas = <&dma_apbh 2>;
370 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800371 status = "disabled";
372 };
373
374 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300375 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800376 status = "disabled";
377 };
378 };
379
380 apbx@80040000 {
381 compatible = "simple-bus";
382 #address-cells = <1>;
383 #size-cells = <1>;
384 reg = <0x80040000 0x40000>;
385 ranges;
386
Shawn Guo53f94432012-08-22 21:36:30 +0800387 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800388 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300389 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800390 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800391 };
392
393 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300394 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800395 dmas = <&dma_apbx 4>;
396 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800397 status = "disabled";
398 };
399
400 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300401 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800402 status = "disabled";
403 };
404
405 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300406 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800407 dmas = <&dma_apbx 10>;
408 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800409 status = "disabled";
410 };
411
412 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300413 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800414 dmas = <&dma_apbx 1>;
415 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800416 status = "disabled";
417 };
418
419 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300420 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800421 dmas = <&dma_apbx 0>;
422 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800423 status = "disabled";
424 };
425
426 lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000427 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300428 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000429 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800430 status = "disabled";
431 };
432
433 spdif@80054000 {
434 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800435 dmas = <&dma_apbx 2>;
436 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800437 status = "disabled";
438 };
439
440 i2c@80058000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300441 reg = <0x80058000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800442 dmas = <&dma_apbx 3>;
443 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800444 status = "disabled";
445 };
446
447 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800448 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300449 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800450 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800451 };
452
Shawn Guo52f71762012-06-28 11:45:06 +0800453 pwm: pwm@80064000 {
454 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300455 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800456 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800457 #pwm-cells = <2>;
458 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800459 status = "disabled";
460 };
461
462 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800463 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300464 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800465 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800466 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800467 };
468
469 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800470 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800471 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800472 interrupts = <24>;
Shawn Guo53f94432012-08-22 21:36:30 +0800473 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800474 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
475 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800476 status = "disabled";
477 };
478
479 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800480 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800481 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800482 interrupts = <59>;
Shawn Guo53f94432012-08-22 21:36:30 +0800483 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800484 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
485 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800486 status = "disabled";
487 };
488
489 duart: serial@80070000 {
490 compatible = "arm,pl011", "arm,primecell";
491 reg = <0x80070000 0x2000>;
492 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800493 clocks = <&clks 32>, <&clks 16>;
494 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800495 status = "disabled";
496 };
497
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300498 usbphy0: usbphy@8007c000 {
499 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800500 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300501 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800502 status = "disabled";
503 };
504 };
505 };
506
507 ahb@80080000 {
508 compatible = "simple-bus";
509 #address-cells = <1>;
510 #size-cells = <1>;
511 reg = <0x80080000 0x80000>;
512 ranges;
513
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300514 usb0: usb@80080000 {
515 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300516 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300517 interrupts = <11>;
518 fsl,usbphy = <&usbphy0>;
519 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800520 status = "disabled";
521 };
522 };
523};