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gerrit-public.fairphone.software / kernel / msm-5.4 / d0b68041bdd0e5ea6dae1210541bf124443d72ec / . / drivers / scsi / pm8001 / pm8001_hwi.c
blob: d18c2635995fd65d6c3438950969f67aea1d6330 [file] [log] [blame]
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include "pm8001_sas.h"
41 #include "pm8001_hwi.h"
42 #include "pm8001_chips.h"
43 #include "pm8001_ctl.h"
44
45/**
46 * read_main_config_table - read the configure table and save it.
47 * @pm8001_ha: our hba card information
48 */
49static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
50{
51 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
52 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
53 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
54 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
55 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
56 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
57 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
58 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
59 pm8001_ha->main_cfg_tbl.inbound_queue_offset =
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]60 pm8001_mr32(address, MAIN_IBQ_OFFSET);
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]61 pm8001_ha->main_cfg_tbl.outbound_queue_offset =
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]62 pm8001_mr32(address, MAIN_OBQ_OFFSET);
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]63 pm8001_ha->main_cfg_tbl.hda_mode_flag =
64 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
65
66 /* read analog Setting offset from the configuration table */
67 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
68 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
69
70 /* read Error Dump Offset and Length */
71 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
72 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
73 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
74 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
75 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
76 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
77 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
78 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
79}
80
81/**
82 * read_general_status_table - read the general status table and save it.
83 * @pm8001_ha: our hba card information
84 */
85static void __devinit
86read_general_status_table(struct pm8001_hba_info *pm8001_ha)
87{
88 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
89 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
90 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
91 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
92 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
93 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
94 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
95 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
96 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
97 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
98 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
99 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
100 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
101 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
102 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
103 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
104 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
105 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
106 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
107 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
108 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
109 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
110 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
111 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
112 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
113 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
114}
115
116/**
117 * read_inbnd_queue_table - read the inbound queue table and save it.
118 * @pm8001_ha: our hba card information
119 */
120static void __devinit
121read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
122{
123 int inbQ_num = 1;
124 int i;
125 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
126 for (i = 0; i < inbQ_num; i++) {
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]127 u32 offset = i * 0x20;
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]128 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
129 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
130 pm8001_ha->inbnd_q_tbl[i].pi_offset =
131 pm8001_mr32(address, (offset + 0x18));
132 }
133}
134
135/**
136 * read_outbnd_queue_table - read the outbound queue table and save it.
137 * @pm8001_ha: our hba card information
138 */
139static void __devinit
140read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
141{
142 int outbQ_num = 1;
143 int i;
144 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
145 for (i = 0; i < outbQ_num; i++) {
146 u32 offset = i * 0x24;
147 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
148 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
149 pm8001_ha->outbnd_q_tbl[i].ci_offset =
150 pm8001_mr32(address, (offset + 0x18));
151 }
152}
153
154/**
155 * init_default_table_values - init the default table.
156 * @pm8001_ha: our hba card information
157 */
158static void __devinit
159init_default_table_values(struct pm8001_hba_info *pm8001_ha)
160{
161 int qn = 1;
162 int i;
163 u32 offsetib, offsetob;
164 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
165 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
166
167 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
168 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
170 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
172 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
176 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
178
179 pm8001_ha->main_cfg_tbl.upper_event_log_addr =
180 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
181 pm8001_ha->main_cfg_tbl.lower_event_log_addr =
182 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
183 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
184 pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
185 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
186 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
187 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
188 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
189 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
190 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
191 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
192 for (i = 0; i < qn; i++) {
193 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
194 0x00000100 | (0x00000040 << 16) | (0x00<<30);
195 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
196 pm8001_ha->memoryMap.region[IB].phys_addr_hi;
197 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
198 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
199 pm8001_ha->inbnd_q_tbl[i].base_virt =
200 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
201 pm8001_ha->inbnd_q_tbl[i].total_length =
202 pm8001_ha->memoryMap.region[IB].total_len;
203 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
204 pm8001_ha->memoryMap.region[CI].phys_addr_hi;
205 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
206 pm8001_ha->memoryMap.region[CI].phys_addr_lo;
207 pm8001_ha->inbnd_q_tbl[i].ci_virt =
208 pm8001_ha->memoryMap.region[CI].virt_ptr;
209 offsetib = i * 0x20;
210 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
211 get_pci_bar_index(pm8001_mr32(addressib,
212 (offsetib + 0x14)));
213 pm8001_ha->inbnd_q_tbl[i].pi_offset =
214 pm8001_mr32(addressib, (offsetib + 0x18));
215 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
216 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
217 }
218 for (i = 0; i < qn; i++) {
219 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
220 256 | (64 << 16) | (1<<30);
221 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
222 pm8001_ha->memoryMap.region[OB].phys_addr_hi;
223 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
224 pm8001_ha->memoryMap.region[OB].phys_addr_lo;
225 pm8001_ha->outbnd_q_tbl[i].base_virt =
226 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
227 pm8001_ha->outbnd_q_tbl[i].total_length =
228 pm8001_ha->memoryMap.region[OB].total_len;
229 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
230 pm8001_ha->memoryMap.region[PI].phys_addr_hi;
231 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
232 pm8001_ha->memoryMap.region[PI].phys_addr_lo;
233 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]234 0 | (10 << 16) | (0 << 24);
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]235 pm8001_ha->outbnd_q_tbl[i].pi_virt =
236 pm8001_ha->memoryMap.region[PI].virt_ptr;
237 offsetob = i * 0x24;
238 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
239 get_pci_bar_index(pm8001_mr32(addressob,
240 offsetob + 0x14));
241 pm8001_ha->outbnd_q_tbl[i].ci_offset =
242 pm8001_mr32(addressob, (offsetob + 0x18));
243 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
244 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
245 }
246}
247
248/**
249 * update_main_config_table - update the main default table to the HBA.
250 * @pm8001_ha: our hba card information
251 */
252static void __devinit
253update_main_config_table(struct pm8001_hba_info *pm8001_ha)
254{
255 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
256 pm8001_mw32(address, 0x24,
257 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
258 pm8001_mw32(address, 0x28,
259 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
260 pm8001_mw32(address, 0x2C,
261 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
262 pm8001_mw32(address, 0x30,
263 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
264 pm8001_mw32(address, 0x34,
265 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
266 pm8001_mw32(address, 0x38,
267 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
268 pm8001_mw32(address, 0x3C,
269 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
270 pm8001_mw32(address, 0x40,
271 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
272 pm8001_mw32(address, 0x44,
273 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
274 pm8001_mw32(address, 0x48,
275 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
276 pm8001_mw32(address, 0x4C,
277 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
278 pm8001_mw32(address, 0x50,
279 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
280 pm8001_mw32(address, 0x54,
281 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
282 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
283 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
284 pm8001_mw32(address, 0x60,
285 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
286 pm8001_mw32(address, 0x64,
287 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
288 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
289 pm8001_mw32(address, 0x6C,
290 pm8001_ha->main_cfg_tbl.iop_event_log_option);
291 pm8001_mw32(address, 0x70,
292 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
293}
294
295/**
296 * update_inbnd_queue_table - update the inbound queue table to the HBA.
297 * @pm8001_ha: our hba card information
298 */
299static void __devinit
300update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
301{
302 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
303 u16 offset = number * 0x20;
304 pm8001_mw32(address, offset + 0x00,
305 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
306 pm8001_mw32(address, offset + 0x04,
307 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
308 pm8001_mw32(address, offset + 0x08,
309 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
310 pm8001_mw32(address, offset + 0x0C,
311 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
312 pm8001_mw32(address, offset + 0x10,
313 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
314}
315
316/**
317 * update_outbnd_queue_table - update the outbound queue table to the HBA.
318 * @pm8001_ha: our hba card information
319 */
320static void __devinit
321update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
322{
323 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
324 u16 offset = number * 0x24;
325 pm8001_mw32(address, offset + 0x00,
326 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
327 pm8001_mw32(address, offset + 0x04,
328 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
329 pm8001_mw32(address, offset + 0x08,
330 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
331 pm8001_mw32(address, offset + 0x0C,
332 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
333 pm8001_mw32(address, offset + 0x10,
334 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
335 pm8001_mw32(address, offset + 0x1C,
336 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
337}
338
339/**
340 * bar4_shift - function is called to shift BAR base address
341 * @pm8001_ha : our hba card infomation
342 * @shiftValue : shifting value in memory bar.
343 */
344static u32 bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
345{
346 u32 regVal;
347 u32 max_wait_count;
348
349 /* program the inbound AXI translation Lower Address */
350 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
351
352 /* confirm the setting is written */
353 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
354 do {
355 udelay(1);
356 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
357 } while ((regVal != shiftValue) && (--max_wait_count));
358
359 if (!max_wait_count) {
360 PM8001_INIT_DBG(pm8001_ha,
361 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
362 " = 0x%x\n", regVal));
363 return -1;
364 }
365 return 0;
366}
367
368/**
369 * mpi_set_phys_g3_with_ssc
370 * @pm8001_ha: our hba card information
371 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
372 */
373static void __devinit
374mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
375{
376 u32 offset;
377 u32 value;
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]378 u32 i, j;
379 u32 bit_cnt;
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]380
381#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
382#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
383#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
384#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]385#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
386#define PHY_G3_WITH_SSC_BIT_SHIFT 13
387#define SNW3_PHY_CAPABILITIES_PARITY 31
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]388
389 /*
390 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
391 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
392 */
393 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
394 return;
395 /* set SSC bit of PHY 0 - 3 */
396 for (i = 0; i < 4; i++) {
397 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
398 value = pm8001_cr32(pm8001_ha, 2, offset);
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]399 if (SSCbit) {
400 value |= 0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT;
401 value &= ~(0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT);
402 } else {
403 value |= 0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT;
404 value &= ~(0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT);
405 }
406 bit_cnt = 0;
407 for (j = 0; j < 31; j++)
408 if ((value >> j) & 0x00000001)
409 bit_cnt++;
410 if (bit_cnt % 2)
411 value &= ~(0x00000001 << SNW3_PHY_CAPABILITIES_PARITY);
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]412 else
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]413 value |= 0x00000001 << SNW3_PHY_CAPABILITIES_PARITY;
414
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]415 pm8001_cw32(pm8001_ha, 2, offset, value);
416 }
417
418 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
419 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
420 return;
421
422 /* set SSC bit of PHY 4 - 7 */
423 for (i = 4; i < 8; i++) {
424 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
425 value = pm8001_cr32(pm8001_ha, 2, offset);
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]426 if (SSCbit) {
427 value |= 0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT;
428 value &= ~(0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT);
429 } else {
430 value |= 0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT;
431 value &= ~(0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT);
432 }
433 bit_cnt = 0;
434 for (j = 0; j < 31; j++)
435 if ((value >> j) & 0x00000001)
436 bit_cnt++;
437 if (bit_cnt % 2)
438 value &= ~(0x00000001 << SNW3_PHY_CAPABILITIES_PARITY);
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]439 else
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]440 value |= 0x00000001 << SNW3_PHY_CAPABILITIES_PARITY;
441
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]442 pm8001_cw32(pm8001_ha, 2, offset, value);
443 }
444
445 /*set the shifted destination address to 0x0 to avoid error operation */
446 bar4_shift(pm8001_ha, 0x0);
447 return;
448}
449
450/**
451 * mpi_set_open_retry_interval_reg
452 * @pm8001_ha: our hba card information
453 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
454 */
455static void __devinit
456mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
457 u32 interval)
458{
459 u32 offset;
460 u32 value;
461 u32 i;
462
463#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
464#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
465#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
466#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
467#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
468
469 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
470 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
471 if (-1 == bar4_shift(pm8001_ha,
472 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
473 return;
474 for (i = 0; i < 4; i++) {
475 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
476 pm8001_cw32(pm8001_ha, 2, offset, value);
477 }
478
479 if (-1 == bar4_shift(pm8001_ha,
480 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
481 return;
482 for (i = 4; i < 8; i++) {
483 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
484 pm8001_cw32(pm8001_ha, 2, offset, value);
485 }
486 /*set the shifted destination address to 0x0 to avoid error operation */
487 bar4_shift(pm8001_ha, 0x0);
488 return;
489}
490
491/**
492 * mpi_init_check - check firmware initialization status.
493 * @pm8001_ha: our hba card information
494 */
495static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
496{
497 u32 max_wait_count;
498 u32 value;
499 u32 gst_len_mpistate;
500 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
501 table is updated */
502 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
503 /* wait until Inbound DoorBell Clear Register toggled */
504 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
505 do {
506 udelay(1);
507 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
508 value &= SPC_MSGU_CFG_TABLE_UPDATE;
509 } while ((value != 0) && (--max_wait_count));
510
511 if (!max_wait_count)
512 return -1;
513 /* check the MPI-State for initialization */
514 gst_len_mpistate =
515 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
516 GST_GSTLEN_MPIS_OFFSET);
517 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
518 return -1;
519 /* check MPI Initialization error */
520 gst_len_mpistate = gst_len_mpistate >> 16;
521 if (0x0000 != gst_len_mpistate)
522 return -1;
523 return 0;
524}
525
526/**
527 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
528 * @pm8001_ha: our hba card information
529 */
530static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
531{
532 u32 value, value1;
533 u32 max_wait_count;
534 /* check error state */
535 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
536 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
537 /* check AAP error */
538 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
539 /* error state */
540 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
541 return -1;
542 }
543
544 /* check IOP error */
545 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
546 /* error state */
547 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
548 return -1;
549 }
550
551 /* bit 4-31 of scratch pad1 should be zeros if it is not
552 in error state*/
553 if (value & SCRATCH_PAD1_STATE_MASK) {
554 /* error case */
555 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
556 return -1;
557 }
558
559 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
560 in error state */
561 if (value1 & SCRATCH_PAD2_STATE_MASK) {
562 /* error case */
563 return -1;
564 }
565
566 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
567
568 /* wait until scratch pad 1 and 2 registers in ready state */
569 do {
570 udelay(1);
571 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
572 & SCRATCH_PAD1_RDY;
573 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
574 & SCRATCH_PAD2_RDY;
575 if ((--max_wait_count) == 0)
576 return -1;
577 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
578 return 0;
579}
580
581static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
582{
583 void __iomem *base_addr;
584 u32 value;
585 u32 offset;
586 u32 pcibar;
587 u32 pcilogic;
588
589 value = pm8001_cr32(pm8001_ha, 0, 0x44);
590 offset = value & 0x03FFFFFF;
591 PM8001_INIT_DBG(pm8001_ha,
592 pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
593 pcilogic = (value & 0xFC000000) >> 26;
594 pcibar = get_pci_bar_index(pcilogic);
595 PM8001_INIT_DBG(pm8001_ha,
596 pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
597 pm8001_ha->main_cfg_tbl_addr = base_addr =
598 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
599 pm8001_ha->general_stat_tbl_addr =
600 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
601 pm8001_ha->inbnd_q_tbl_addr =
602 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
603 pm8001_ha->outbnd_q_tbl_addr =
604 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
605}
606
607/**
608 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
609 * @pm8001_ha: our hba card information
610 */
611static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
612{
613 /* check the firmware status */
614 if (-1 == check_fw_ready(pm8001_ha)) {
615 PM8001_FAIL_DBG(pm8001_ha,
616 pm8001_printk("Firmware is not ready!\n"));
617 return -EBUSY;
618 }
619
620 /* Initialize pci space address eg: mpi offset */
621 init_pci_device_addresses(pm8001_ha);
622 init_default_table_values(pm8001_ha);
623 read_main_config_table(pm8001_ha);
624 read_general_status_table(pm8001_ha);
625 read_inbnd_queue_table(pm8001_ha);
626 read_outbnd_queue_table(pm8001_ha);
627 /* update main config table ,inbound table and outbound table */
628 update_main_config_table(pm8001_ha);
629 update_inbnd_queue_table(pm8001_ha, 0);
630 update_outbnd_queue_table(pm8001_ha, 0);
631 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
632 mpi_set_open_retry_interval_reg(pm8001_ha, 7);
633 /* notify firmware update finished and check initialization status */
634 if (0 == mpi_init_check(pm8001_ha)) {
635 PM8001_INIT_DBG(pm8001_ha,
636 pm8001_printk("MPI initialize successful!\n"));
637 } else
638 return -EBUSY;
639 /*This register is a 16-bit timer with a resolution of 1us. This is the
640 timer used for interrupt delay/coalescing in the PCIe Application Layer.
641 Zero is not a valid value. A value of 1 in the register will cause the
642 interrupts to be normal. A value greater than 1 will cause coalescing
643 delays.*/
644 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
645 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
646 return 0;
647}
648
649static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
650{
651 u32 max_wait_count;
652 u32 value;
653 u32 gst_len_mpistate;
654 init_pci_device_addresses(pm8001_ha);
655 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
656 table is stop */
657 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
658
659 /* wait until Inbound DoorBell Clear Register toggled */
660 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
661 do {
662 udelay(1);
663 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
664 value &= SPC_MSGU_CFG_TABLE_RESET;
665 } while ((value != 0) && (--max_wait_count));
666
667 if (!max_wait_count) {
668 PM8001_FAIL_DBG(pm8001_ha,
669 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
670 return -1;
671 }
672
673 /* check the MPI-State for termination in progress */
674 /* wait until Inbound DoorBell Clear Register toggled */
675 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
676 do {
677 udelay(1);
678 gst_len_mpistate =
679 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
680 GST_GSTLEN_MPIS_OFFSET);
681 if (GST_MPI_STATE_UNINIT ==
682 (gst_len_mpistate & GST_MPI_STATE_MASK))
683 break;
684 } while (--max_wait_count);
685 if (!max_wait_count) {
686 PM8001_FAIL_DBG(pm8001_ha,
687 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
688 gst_len_mpistate & GST_MPI_STATE_MASK));
689 return -1;
690 }
691 return 0;
692}
693
694/**
695 * soft_reset_ready_check - Function to check FW is ready for soft reset.
696 * @pm8001_ha: our hba card information
697 */
698static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
699{
700 u32 regVal, regVal1, regVal2;
701 if (mpi_uninit_check(pm8001_ha) != 0) {
702 PM8001_FAIL_DBG(pm8001_ha,
703 pm8001_printk("MPI state is not ready\n"));
704 return -1;
705 }
706 /* read the scratch pad 2 register bit 2 */
707 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
708 & SCRATCH_PAD2_FWRDY_RST;
709 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
710 PM8001_INIT_DBG(pm8001_ha,
711 pm8001_printk("Firmware is ready for reset .\n"));
712 } else {
713 /* Trigger NMI twice via RB6 */
714 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
715 PM8001_FAIL_DBG(pm8001_ha,
716 pm8001_printk("Shift Bar4 to 0x%x failed\n",
717 RB6_ACCESS_REG));
718 return -1;
719 }
720 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
721 RB6_MAGIC_NUMBER_RST);
722 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
723 /* wait for 100 ms */
724 mdelay(100);
725 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
726 SCRATCH_PAD2_FWRDY_RST;
727 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
728 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
729 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
730 PM8001_FAIL_DBG(pm8001_ha,
731 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
732 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
733 regVal1, regVal2));
734 PM8001_FAIL_DBG(pm8001_ha,
735 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
736 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
737 PM8001_FAIL_DBG(pm8001_ha,
738 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
739 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
740 return -1;
741 }
742 }
743 return 0;
744}
745
746/**
747 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
748 * the FW register status to the originated status.
749 * @pm8001_ha: our hba card information
750 * @signature: signature in host scratch pad0 register.
751 */
752static int
753pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
754{
755 u32 regVal, toggleVal;
756 u32 max_wait_count;
757 u32 regVal1, regVal2, regVal3;
758
759 /* step1: Check FW is ready for soft reset */
760 if (soft_reset_ready_check(pm8001_ha) != 0) {
761 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
762 return -1;
763 }
764
765 /* step 2: clear NMI status register on AAP1 and IOP, write the same
766 value to clear */
767 /* map 0x60000 to BAR4(0x20), BAR2(win) */
768 if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
769 PM8001_FAIL_DBG(pm8001_ha,
770 pm8001_printk("Shift Bar4 to 0x%x failed\n",
771 MBIC_AAP1_ADDR_BASE));
772 return -1;
773 }
774 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
775 PM8001_INIT_DBG(pm8001_ha,
776 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
777 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
778 /* map 0x70000 to BAR4(0x20), BAR2(win) */
779 if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
780 PM8001_FAIL_DBG(pm8001_ha,
781 pm8001_printk("Shift Bar4 to 0x%x failed\n",
782 MBIC_IOP_ADDR_BASE));
783 return -1;
784 }
785 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
786 PM8001_INIT_DBG(pm8001_ha,
787 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
788 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
789
790 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
791 PM8001_INIT_DBG(pm8001_ha,
792 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
793 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
794
795 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
796 PM8001_INIT_DBG(pm8001_ha,
797 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
798 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
799
800 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
801 PM8001_INIT_DBG(pm8001_ha,
802 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
803 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
804
805 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
806 PM8001_INIT_DBG(pm8001_ha,
807 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
808 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
809
810 /* read the scratch pad 1 register bit 2 */
811 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
812 & SCRATCH_PAD1_RST;
813 toggleVal = regVal ^ SCRATCH_PAD1_RST;
814
815 /* set signature in host scratch pad0 register to tell SPC that the
816 host performs the soft reset */
817 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
818
819 /* read required registers for confirmming */
820 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
821 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
822 PM8001_FAIL_DBG(pm8001_ha,
823 pm8001_printk("Shift Bar4 to 0x%x failed\n",
824 GSM_ADDR_BASE));
825 return -1;
826 }
827 PM8001_INIT_DBG(pm8001_ha,
828 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
829 " Reset = 0x%x\n",
830 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
831
832 /* step 3: host read GSM Configuration and Reset register */
833 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
834 /* Put those bits to low */
835 /* GSM XCBI offset = 0x70 0000
836 0x00 Bit 13 COM_SLV_SW_RSTB 1
837 0x00 Bit 12 QSSP_SW_RSTB 1
838 0x00 Bit 11 RAAE_SW_RSTB 1
839 0x00 Bit 9 RB_1_SW_RSTB 1
840 0x00 Bit 8 SM_SW_RSTB 1
841 */
842 regVal &= ~(0x00003b00);
843 /* host write GSM Configuration and Reset register */
844 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
845 PM8001_INIT_DBG(pm8001_ha,
846 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
847 "Configuration and Reset is set to = 0x%x\n",
848 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
849
850 /* step 4: */
851 /* disable GSM - Read Address Parity Check */
852 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
855 "Enable = 0x%x\n", regVal1));
856 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
857 PM8001_INIT_DBG(pm8001_ha,
858 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
859 "is set to = 0x%x\n",
860 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
861
862 /* disable GSM - Write Address Parity Check */
863 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
864 PM8001_INIT_DBG(pm8001_ha,
865 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
866 " Enable = 0x%x\n", regVal2));
867 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
868 PM8001_INIT_DBG(pm8001_ha,
869 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
870 "Enable is set to = 0x%x\n",
871 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
872
873 /* disable GSM - Write Data Parity Check */
874 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
875 PM8001_INIT_DBG(pm8001_ha,
876 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
877 " Enable = 0x%x\n", regVal3));
878 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
879 PM8001_INIT_DBG(pm8001_ha,
880 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
881 "is set to = 0x%x\n",
882 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
883
884 /* step 5: delay 10 usec */
885 udelay(10);
886 /* step 5-b: set GPIO-0 output control to tristate anyway */
887 if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
888 PM8001_INIT_DBG(pm8001_ha,
889 pm8001_printk("Shift Bar4 to 0x%x failed\n",
890 GPIO_ADDR_BASE));
891 return -1;
892 }
893 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
894 PM8001_INIT_DBG(pm8001_ha,
895 pm8001_printk("GPIO Output Control Register:"
896 " = 0x%x\n", regVal));
897 /* set GPIO-0 output control to tri-state */
898 regVal &= 0xFFFFFFFC;
899 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
900
901 /* Step 6: Reset the IOP and AAP1 */
902 /* map 0x00000 to BAR4(0x20), BAR2(win) */
903 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
904 PM8001_FAIL_DBG(pm8001_ha,
905 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
906 SPC_TOP_LEVEL_ADDR_BASE));
907 return -1;
908 }
909 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
910 PM8001_INIT_DBG(pm8001_ha,
911 pm8001_printk("Top Register before resetting IOP/AAP1"
912 ":= 0x%x\n", regVal));
913 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
914 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
915
916 /* step 7: Reset the BDMA/OSSP */
917 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
918 PM8001_INIT_DBG(pm8001_ha,
919 pm8001_printk("Top Register before resetting BDMA/OSSP"
920 ": = 0x%x\n", regVal));
921 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
922 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
923
924 /* step 8: delay 10 usec */
925 udelay(10);
926
927 /* step 9: bring the BDMA and OSSP out of reset */
928 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
929 PM8001_INIT_DBG(pm8001_ha,
930 pm8001_printk("Top Register before bringing up BDMA/OSSP"
931 ":= 0x%x\n", regVal));
932 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
933 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
934
935 /* step 10: delay 10 usec */
936 udelay(10);
937
938 /* step 11: reads and sets the GSM Configuration and Reset Register */
939 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
940 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
941 PM8001_FAIL_DBG(pm8001_ha,
942 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
943 GSM_ADDR_BASE));
944 return -1;
945 }
946 PM8001_INIT_DBG(pm8001_ha,
947 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
948 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
949 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
950 /* Put those bits to high */
951 /* GSM XCBI offset = 0x70 0000
952 0x00 Bit 13 COM_SLV_SW_RSTB 1
953 0x00 Bit 12 QSSP_SW_RSTB 1
954 0x00 Bit 11 RAAE_SW_RSTB 1
955 0x00 Bit 9 RB_1_SW_RSTB 1
956 0x00 Bit 8 SM_SW_RSTB 1
957 */
958 regVal |= (GSM_CONFIG_RESET_VALUE);
959 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
960 PM8001_INIT_DBG(pm8001_ha,
961 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
962 " Configuration and Reset is set to = 0x%x\n",
963 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
964
965 /* step 12: Restore GSM - Read Address Parity Check */
966 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
967 /* just for debugging */
968 PM8001_INIT_DBG(pm8001_ha,
969 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
970 " = 0x%x\n", regVal));
971 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
972 PM8001_INIT_DBG(pm8001_ha,
973 pm8001_printk("GSM 0x700038 - Read Address Parity"
974 " Check Enable is set to = 0x%x\n",
975 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
976 /* Restore GSM - Write Address Parity Check */
977 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
978 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
979 PM8001_INIT_DBG(pm8001_ha,
980 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
981 " Enable is set to = 0x%x\n",
982 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
983 /* Restore GSM - Write Data Parity Check */
984 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
985 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
986 PM8001_INIT_DBG(pm8001_ha,
987 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
988 "is set to = 0x%x\n",
989 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
990
991 /* step 13: bring the IOP and AAP1 out of reset */
992 /* map 0x00000 to BAR4(0x20), BAR2(win) */
993 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
994 PM8001_FAIL_DBG(pm8001_ha,
995 pm8001_printk("Shift Bar4 to 0x%x failed\n",
996 SPC_TOP_LEVEL_ADDR_BASE));
997 return -1;
998 }
999 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1000 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1001 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1002
1003 /* step 14: delay 10 usec - Normal Mode */
1004 udelay(10);
1005 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1006 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1007 /* step 15 (Normal Mode): wait until scratch pad1 register
1008 bit 2 toggled */
1009 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1010 do {
1011 udelay(1);
1012 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1013 SCRATCH_PAD1_RST;
1014 } while ((regVal != toggleVal) && (--max_wait_count));
1015
1016 if (!max_wait_count) {
1017 regVal = pm8001_cr32(pm8001_ha, 0,
1018 MSGU_SCRATCH_PAD_1);
1019 PM8001_FAIL_DBG(pm8001_ha,
1020 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1021 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1022 toggleVal, regVal));
1023 PM8001_FAIL_DBG(pm8001_ha,
1024 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1025 pm8001_cr32(pm8001_ha, 0,
1026 MSGU_SCRATCH_PAD_0)));
1027 PM8001_FAIL_DBG(pm8001_ha,
1028 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1029 pm8001_cr32(pm8001_ha, 0,
1030 MSGU_SCRATCH_PAD_2)));
1031 PM8001_FAIL_DBG(pm8001_ha,
1032 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1033 pm8001_cr32(pm8001_ha, 0,
1034 MSGU_SCRATCH_PAD_3)));
1035 return -1;
1036 }
1037
1038 /* step 16 (Normal) - Clear ODMR and ODCR */
1039 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1040 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1041
1042 /* step 17 (Normal Mode): wait for the FW and IOP to get
1043 ready - 1 sec timeout */
1044 /* Wait for the SPC Configuration Table to be ready */
1045 if (check_fw_ready(pm8001_ha) == -1) {
1046 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1047 /* return error if MPI Configuration Table not ready */
1048 PM8001_INIT_DBG(pm8001_ha,
1049 pm8001_printk("FW not ready SCRATCH_PAD1"
1050 " = 0x%x\n", regVal));
1051 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1052 /* return error if MPI Configuration Table not ready */
1053 PM8001_INIT_DBG(pm8001_ha,
1054 pm8001_printk("FW not ready SCRATCH_PAD2"
1055 " = 0x%x\n", regVal));
1056 PM8001_INIT_DBG(pm8001_ha,
1057 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1058 pm8001_cr32(pm8001_ha, 0,
1059 MSGU_SCRATCH_PAD_0)));
1060 PM8001_INIT_DBG(pm8001_ha,
1061 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1062 pm8001_cr32(pm8001_ha, 0,
1063 MSGU_SCRATCH_PAD_3)));
1064 return -1;
1065 }
1066 }
1067
1068 PM8001_INIT_DBG(pm8001_ha,
1069 pm8001_printk("SPC soft reset Complete\n"));
1070 return 0;
1071}
1072
1073static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1074{
1075 u32 i;
1076 u32 regVal;
1077 PM8001_INIT_DBG(pm8001_ha,
1078 pm8001_printk("chip reset start\n"));
1079
1080 /* do SPC chip reset. */
1081 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1082 regVal &= ~(SPC_REG_RESET_DEVICE);
1083 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1084
1085 /* delay 10 usec */
1086 udelay(10);
1087
1088 /* bring chip reset out of reset */
1089 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1090 regVal |= SPC_REG_RESET_DEVICE;
1091 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1092
1093 /* delay 10 usec */
1094 udelay(10);
1095
1096 /* wait for 20 msec until the firmware gets reloaded */
1097 i = 20;
1098 do {
1099 mdelay(1);
1100 } while ((--i) != 0);
1101
1102 PM8001_INIT_DBG(pm8001_ha,
1103 pm8001_printk("chip reset finished\n"));
1104}
1105
1106/**
1107 * pm8001_chip_iounmap - which maped when initilized.
1108 * @pm8001_ha: our hba card information
1109 */
1110static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1111{
1112 s8 bar, logical = 0;
1113 for (bar = 0; bar < 6; bar++) {
1114 /*
1115 ** logical BARs for SPC:
1116 ** bar 0 and 1 - logical BAR0
1117 ** bar 2 and 3 - logical BAR1
1118 ** bar4 - logical BAR2
1119 ** bar5 - logical BAR3
1120 ** Skip the appropriate assignments:
1121 */
1122 if ((bar == 1) || (bar == 3))
1123 continue;
1124 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1125 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1126 logical++;
1127 }
1128 }
1129}
1130
1131/**
1132 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1133 * @pm8001_ha: our hba card information
1134 */
1135static void
1136pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1137{
1138 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1139 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1140}
1141
1142 /**
1143 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1144 * @pm8001_ha: our hba card information
1145 */
1146static void
1147pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1148{
1149 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1150}
1151
1152/**
1153 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1154 * @pm8001_ha: our hba card information
1155 */
1156static void
1157pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1158 u32 int_vec_idx)
1159{
1160 u32 msi_index;
1161 u32 value;
1162 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1163 msi_index += MSIX_TABLE_BASE;
1164 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1165 value = (1 << int_vec_idx);
1166 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1167
1168}
1169
1170/**
1171 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1172 * @pm8001_ha: our hba card information
1173 */
1174static void
1175pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1176 u32 int_vec_idx)
1177{
1178 u32 msi_index;
1179 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1180 msi_index += MSIX_TABLE_BASE;
1181 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1182
1183}
1184/**
1185 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1186 * @pm8001_ha: our hba card information
1187 */
1188static void
1189pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1190{
1191#ifdef PM8001_USE_MSIX
1192 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1193 return;
1194#endif
1195 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1196
1197}
1198
1199/**
1200 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1201 * @pm8001_ha: our hba card information
1202 */
1203static void
1204pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1205{
1206#ifdef PM8001_USE_MSIX
1207 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1208 return;
1209#endif
1210 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1211
1212}
1213
1214/**
1215 * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1216 * @circularQ: the inbound queue we want to transfer to HBA.
1217 * @messageSize: the message size of this transfer, normally it is 64 bytes
1218 * @messagePtr: the pointer to message.
1219 */
1220static u32 mpi_msg_free_get(struct inbound_queue_table *circularQ,
1221 u16 messageSize, void **messagePtr)
1222{
1223 u32 offset, consumer_index;
1224 struct mpi_msg_hdr *msgHeader;
1225 u8 bcCount = 1; /* only support single buffer */
1226
1227 /* Checks is the requested message size can be allocated in this queue*/
1228 if (messageSize > 64) {
1229 *messagePtr = NULL;
1230 return -1;
1231 }
1232
1233 /* Stores the new consumer index */
1234 consumer_index = pm8001_read_32(circularQ->ci_virt);
1235 circularQ->consumer_index = cpu_to_le32(consumer_index);
1236 if (((circularQ->producer_idx + bcCount) % 256) ==
1237 circularQ->consumer_index) {
1238 *messagePtr = NULL;
1239 return -1;
1240 }
1241 /* get memory IOMB buffer address */
1242 offset = circularQ->producer_idx * 64;
1243 /* increment to next bcCount element */
1244 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1245 /* Adds that distance to the base of the region virtual address plus
1246 the message header size*/
1247 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1248 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1249 return 0;
1250}
1251
1252/**
1253 * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1254 * to tell the fw to get this message from IOMB.
1255 * @pm8001_ha: our hba card information
1256 * @circularQ: the inbound queue we want to transfer to HBA.
1257 * @opCode: the operation code represents commands which LLDD and fw recognized.
1258 * @payload: the command payload of each operation command.
1259 */
1260static u32 mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1261 struct inbound_queue_table *circularQ,
1262 u32 opCode, void *payload)
1263{
1264 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1265 u32 responseQueue = 0;
1266 void *pMessage;
1267
1268 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1269 PM8001_IO_DBG(pm8001_ha,
1270 pm8001_printk("No free mpi buffer \n"));
1271 return -1;
1272 }
1273
1274 /*Copy to the payload*/
1275 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1276
1277 /*Build the header*/
1278 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1279 | ((responseQueue & 0x3F) << 16)
1280 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1281
1282 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1283 /*Update the PI to the firmware*/
1284 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1285 circularQ->pi_offset, circularQ->producer_idx);
1286 PM8001_IO_DBG(pm8001_ha,
1287 pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
1288 circularQ->consumer_index));
1289 return 0;
1290}
1291
1292static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha,
1293 struct outbound_queue_table *circularQ, u8 bc)
1294{
1295 u32 producer_index;
1296 /* free the circular queue buffer elements associated with the message*/
1297 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1298 /* update the CI of outbound queue */
1299 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1300 circularQ->consumer_idx);
1301 /* Update the producer index from SPC*/
1302 producer_index = pm8001_read_32(circularQ->pi_virt);
1303 circularQ->producer_index = cpu_to_le32(producer_index);
1304 PM8001_IO_DBG(pm8001_ha,
1305 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1306 circularQ->producer_index));
1307 return 0;
1308}
1309
1310/**
1311 * mpi_msg_consume- get the MPI message from outbound queue message table.
1312 * @pm8001_ha: our hba card information
1313 * @circularQ: the outbound queue table.
1314 * @messagePtr1: the message contents of this outbound message.
1315 * @pBC: the message size.
1316 */
1317static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1318 struct outbound_queue_table *circularQ,
1319 void **messagePtr1, u8 *pBC)
1320{
1321 struct mpi_msg_hdr *msgHeader;
1322 __le32 msgHeader_tmp;
1323 u32 header_tmp;
1324 do {
1325 /* If there are not-yet-delivered messages ... */
1326 if (circularQ->producer_index != circularQ->consumer_idx) {
1327 PM8001_IO_DBG(pm8001_ha,
1328 pm8001_printk("process an IOMB\n"));
1329 /*Get the pointer to the circular queue buffer element*/
1330 msgHeader = (struct mpi_msg_hdr *)
1331 (circularQ->base_virt +
1332 circularQ->consumer_idx * 64);
1333 /* read header */
1334 header_tmp = pm8001_read_32(msgHeader);
1335 msgHeader_tmp = cpu_to_le32(header_tmp);
1336 if (0 != (msgHeader_tmp & 0x80000000)) {
1337 if (OPC_OUB_SKIP_ENTRY !=
1338 (msgHeader_tmp & 0xfff)) {
1339 *messagePtr1 =
1340 ((u8 *)msgHeader) +
1341 sizeof(struct mpi_msg_hdr);
1342 *pBC = (u8)((msgHeader_tmp >> 24) &
1343 0x1f);
1344 PM8001_IO_DBG(pm8001_ha,
1345 pm8001_printk("mpi_msg_consume"
1346 ": CI=%d PI=%d msgHeader=%x\n",
1347 circularQ->consumer_idx,
1348 circularQ->producer_index,
1349 msgHeader_tmp));
1350 return MPI_IO_STATUS_SUCCESS;
1351 } else {
1352 u32 producer_index;
1353 void *pi_virt = circularQ->pi_virt;
1354 /* free the circular queue buffer
1355 elements associated with the message*/
1356 circularQ->consumer_idx =
1357 (circularQ->consumer_idx +
1358 ((msgHeader_tmp >> 24) & 0x1f))
1359 % 256;
1360 /* update the CI of outbound queue */
1361 pm8001_cw32(pm8001_ha,
1362 circularQ->ci_pci_bar,
1363 circularQ->ci_offset,
1364 circularQ->consumer_idx);
1365 /* Update the producer index from SPC */
1366 producer_index =
1367 pm8001_read_32(pi_virt);
1368 circularQ->producer_index =
1369 cpu_to_le32(producer_index);
1370 }
1371 } else
1372 return MPI_IO_STATUS_FAIL;
1373 }
1374 } while (circularQ->producer_index != circularQ->consumer_idx);
1375 /* while we don't have any more not-yet-delivered message */
1376 /* report empty */
1377 return MPI_IO_STATUS_BUSY;
1378}
1379
1380static void pm8001_work_queue(struct work_struct *work)
1381{
1382 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1383 struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q);
1384 struct pm8001_device *pm8001_dev;
1385 struct domain_device *dev;
1386
1387 switch (wq->handler) {
1388 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1389 pm8001_dev = wq->data;
1390 dev = pm8001_dev->sas_device;
1391 pm8001_I_T_nexus_reset(dev);
1392 break;
1393 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1394 pm8001_dev = wq->data;
1395 dev = pm8001_dev->sas_device;
1396 pm8001_I_T_nexus_reset(dev);
1397 break;
1398 case IO_DS_IN_ERROR:
1399 pm8001_dev = wq->data;
1400 dev = pm8001_dev->sas_device;
1401 pm8001_I_T_nexus_reset(dev);
1402 break;
1403 case IO_DS_NON_OPERATIONAL:
1404 pm8001_dev = wq->data;
1405 dev = pm8001_dev->sas_device;
1406 pm8001_I_T_nexus_reset(dev);
1407 break;
1408 }
1409 list_del(&wq->entry);
1410 kfree(wq);
1411}
1412
1413static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1414 int handler)
1415{
1416 struct pm8001_wq *wq;
1417 int ret = 0;
1418
1419 wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC);
1420 if (wq) {
1421 wq->pm8001_ha = pm8001_ha;
1422 wq->data = data;
1423 wq->handler = handler;
1424 INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue);
1425 list_add_tail(&wq->entry, &pm8001_ha->wq_list);
1426 schedule_delayed_work(&wq->work_q, 0);
1427 } else
1428 ret = -ENOMEM;
1429
1430 return ret;
1431}
1432
1433/**
1434 * mpi_ssp_completion- process the event that FW response to the SSP request.
1435 * @pm8001_ha: our hba card information
1436 * @piomb: the message contents of this outbound message.
1437 *
1438 * When FW has completed a ssp request for example a IO request, after it has
1439 * filled the SG data with the data, it will trigger this event represent
1440 * that he has finished the job,please check the coresponding buffer.
1441 * So we will tell the caller who maybe waiting the result to tell upper layer
1442 * that the task has been finished.
1443 */
1444static int
1445mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1446{
1447 struct sas_task *t;
1448 struct pm8001_ccb_info *ccb;
1449 unsigned long flags;
1450 u32 status;
1451 u32 param;
1452 u32 tag;
1453 struct ssp_completion_resp *psspPayload;
1454 struct task_status_struct *ts;
1455 struct ssp_response_iu *iu;
1456 struct pm8001_device *pm8001_dev;
1457 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1458 status = le32_to_cpu(psspPayload->status);
1459 tag = le32_to_cpu(psspPayload->tag);
1460 ccb = &pm8001_ha->ccb_info[tag];
1461 pm8001_dev = ccb->device;
1462 param = le32_to_cpu(psspPayload->param);
1463
1464 PM8001_IO_DBG(pm8001_ha, pm8001_printk("OPC_OUB_SSP_COMP\n"));
1465 t = ccb->task;
1466
1467 if (status)
1468 PM8001_FAIL_DBG(pm8001_ha,
1469 pm8001_printk("sas IO status 0x%x\n", status));
1470 if (unlikely(!t || !t->lldd_task || !t->dev))
1471 return -1;
1472 ts = &t->task_status;
1473 switch (status) {
1474 case IO_SUCCESS:
1475 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1476 ",param = %d \n", param));
1477 if (param == 0) {
1478 ts->resp = SAS_TASK_COMPLETE;
1479 ts->stat = SAM_GOOD;
1480 } else {
1481 ts->resp = SAS_TASK_COMPLETE;
1482 ts->stat = SAS_PROTO_RESPONSE;
1483 ts->residual = param;
1484 iu = &psspPayload->ssp_resp_iu;
1485 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1486 }
1487 if (pm8001_dev)
1488 pm8001_dev->running_req--;
1489 break;
1490 case IO_ABORTED:
1491 PM8001_IO_DBG(pm8001_ha,
1492 pm8001_printk("IO_ABORTED IOMB Tag \n"));
1493 ts->resp = SAS_TASK_COMPLETE;
1494 ts->stat = SAS_ABORTED_TASK;
1495 break;
1496 case IO_UNDERFLOW:
1497 /* SSP Completion with error */
1498 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1499 ",param = %d \n", param));
1500 ts->resp = SAS_TASK_COMPLETE;
1501 ts->stat = SAS_DATA_UNDERRUN;
1502 ts->residual = param;
1503 if (pm8001_dev)
1504 pm8001_dev->running_req--;
1505 break;
1506 case IO_NO_DEVICE:
1507 PM8001_IO_DBG(pm8001_ha,
1508 pm8001_printk("IO_NO_DEVICE\n"));
1509 ts->resp = SAS_TASK_UNDELIVERED;
1510 ts->stat = SAS_PHY_DOWN;
1511 break;
1512 case IO_XFER_ERROR_BREAK:
1513 PM8001_IO_DBG(pm8001_ha,
1514 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1515 ts->resp = SAS_TASK_COMPLETE;
1516 ts->stat = SAS_OPEN_REJECT;
1517 break;
1518 case IO_XFER_ERROR_PHY_NOT_READY:
1519 PM8001_IO_DBG(pm8001_ha,
1520 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1521 ts->resp = SAS_TASK_COMPLETE;
1522 ts->stat = SAS_OPEN_REJECT;
1523 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1524 break;
1525 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1526 PM8001_IO_DBG(pm8001_ha,
1527 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1528 ts->resp = SAS_TASK_COMPLETE;
1529 ts->stat = SAS_OPEN_REJECT;
1530 ts->open_rej_reason = SAS_OREJ_EPROTO;
1531 break;
1532 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1533 PM8001_IO_DBG(pm8001_ha,
1534 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1535 ts->resp = SAS_TASK_COMPLETE;
1536 ts->stat = SAS_OPEN_REJECT;
1537 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1538 break;
1539 case IO_OPEN_CNX_ERROR_BREAK:
1540 PM8001_IO_DBG(pm8001_ha,
1541 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1542 ts->resp = SAS_TASK_COMPLETE;
1543 ts->stat = SAS_OPEN_REJECT;
1544 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1545 break;
1546 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1547 PM8001_IO_DBG(pm8001_ha,
1548 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1549 ts->resp = SAS_TASK_COMPLETE;
1550 ts->stat = SAS_OPEN_REJECT;
1551 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1552 if (!t->uldd_task)
1553 pm8001_handle_event(pm8001_ha,
1554 pm8001_dev,
1555 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1556 break;
1557 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1558 PM8001_IO_DBG(pm8001_ha,
1559 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1560 ts->resp = SAS_TASK_COMPLETE;
1561 ts->stat = SAS_OPEN_REJECT;
1562 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1563 break;
1564 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1565 PM8001_IO_DBG(pm8001_ha,
1566 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1567 "NOT_SUPPORTED\n"));
1568 ts->resp = SAS_TASK_COMPLETE;
1569 ts->stat = SAS_OPEN_REJECT;
1570 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1571 break;
1572 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1573 PM8001_IO_DBG(pm8001_ha,
1574 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1575 ts->resp = SAS_TASK_UNDELIVERED;
1576 ts->stat = SAS_OPEN_REJECT;
1577 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1578 break;
1579 case IO_XFER_ERROR_NAK_RECEIVED:
1580 PM8001_IO_DBG(pm8001_ha,
1581 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1582 ts->resp = SAS_TASK_COMPLETE;
1583 ts->stat = SAS_OPEN_REJECT;
1584 break;
1585 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1586 PM8001_IO_DBG(pm8001_ha,
1587 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1588 ts->resp = SAS_TASK_COMPLETE;
1589 ts->stat = SAS_NAK_R_ERR;
1590 break;
1591 case IO_XFER_ERROR_DMA:
1592 PM8001_IO_DBG(pm8001_ha,
1593 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1594 ts->resp = SAS_TASK_COMPLETE;
1595 ts->stat = SAS_OPEN_REJECT;
1596 break;
1597 case IO_XFER_OPEN_RETRY_TIMEOUT:
1598 PM8001_IO_DBG(pm8001_ha,
1599 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1600 ts->resp = SAS_TASK_COMPLETE;
1601 ts->stat = SAS_OPEN_REJECT;
1602 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1603 break;
1604 case IO_XFER_ERROR_OFFSET_MISMATCH:
1605 PM8001_IO_DBG(pm8001_ha,
1606 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1607 ts->resp = SAS_TASK_COMPLETE;
1608 ts->stat = SAS_OPEN_REJECT;
1609 break;
1610 case IO_PORT_IN_RESET:
1611 PM8001_IO_DBG(pm8001_ha,
1612 pm8001_printk("IO_PORT_IN_RESET\n"));
1613 ts->resp = SAS_TASK_COMPLETE;
1614 ts->stat = SAS_OPEN_REJECT;
1615 break;
1616 case IO_DS_NON_OPERATIONAL:
1617 PM8001_IO_DBG(pm8001_ha,
1618 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1619 ts->resp = SAS_TASK_COMPLETE;
1620 ts->stat = SAS_OPEN_REJECT;
1621 if (!t->uldd_task)
1622 pm8001_handle_event(pm8001_ha,
1623 pm8001_dev,
1624 IO_DS_NON_OPERATIONAL);
1625 break;
1626 case IO_DS_IN_RECOVERY:
1627 PM8001_IO_DBG(pm8001_ha,
1628 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1629 ts->resp = SAS_TASK_COMPLETE;
1630 ts->stat = SAS_OPEN_REJECT;
1631 break;
1632 case IO_TM_TAG_NOT_FOUND:
1633 PM8001_IO_DBG(pm8001_ha,
1634 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1635 ts->resp = SAS_TASK_COMPLETE;
1636 ts->stat = SAS_OPEN_REJECT;
1637 break;
1638 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1639 PM8001_IO_DBG(pm8001_ha,
1640 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1641 ts->resp = SAS_TASK_COMPLETE;
1642 ts->stat = SAS_OPEN_REJECT;
1643 break;
1644 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1645 PM8001_IO_DBG(pm8001_ha,
1646 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1647 ts->resp = SAS_TASK_COMPLETE;
1648 ts->stat = SAS_OPEN_REJECT;
1649 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1650 default:
1651 PM8001_IO_DBG(pm8001_ha,
1652 pm8001_printk("Unknown status 0x%x\n", status));
1653 /* not allowed case. Therefore, return failed status */
1654 ts->resp = SAS_TASK_COMPLETE;
1655 ts->stat = SAS_OPEN_REJECT;
1656 break;
1657 }
1658 PM8001_IO_DBG(pm8001_ha,
1659 pm8001_printk("scsi_satus = %x \n ",
1660 psspPayload->ssp_resp_iu.status));
1661 spin_lock_irqsave(&t->task_state_lock, flags);
1662 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1663 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1664 t->task_state_flags |= SAS_TASK_STATE_DONE;
1665 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1666 spin_unlock_irqrestore(&t->task_state_lock, flags);
1667 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1668 " io_status 0x%x resp 0x%x "
1669 "stat 0x%x but aborted by upper layer!\n",
1670 t, status, ts->resp, ts->stat));
1671 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1672 } else {
1673 spin_unlock_irqrestore(&t->task_state_lock, flags);
1674 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1675 mb();/* in order to force CPU ordering */
1676 t->task_done(t);
1677 }
1678 return 0;
1679}
1680
1681/*See the comments for mpi_ssp_completion */
1682static int mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1683{
1684 struct sas_task *t;
1685 unsigned long flags;
1686 struct task_status_struct *ts;
1687 struct pm8001_ccb_info *ccb;
1688 struct pm8001_device *pm8001_dev;
1689 struct ssp_event_resp *psspPayload =
1690 (struct ssp_event_resp *)(piomb + 4);
1691 u32 event = le32_to_cpu(psspPayload->event);
1692 u32 tag = le32_to_cpu(psspPayload->tag);
1693 u32 port_id = le32_to_cpu(psspPayload->port_id);
1694 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1695
1696 ccb = &pm8001_ha->ccb_info[tag];
1697 t = ccb->task;
1698 pm8001_dev = ccb->device;
1699 if (event)
1700 PM8001_FAIL_DBG(pm8001_ha,
1701 pm8001_printk("sas IO status 0x%x\n", event));
1702 if (unlikely(!t || !t->lldd_task || !t->dev))
1703 return -1;
1704 ts = &t->task_status;
1705 PM8001_IO_DBG(pm8001_ha,
1706 pm8001_printk("port_id = %x,device_id = %x\n",
1707 port_id, dev_id));
1708 switch (event) {
1709 case IO_OVERFLOW:
1710 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1711 ts->resp = SAS_TASK_COMPLETE;
1712 ts->stat = SAS_DATA_OVERRUN;
1713 ts->residual = 0;
1714 if (pm8001_dev)
1715 pm8001_dev->running_req--;
1716 break;
1717 case IO_XFER_ERROR_BREAK:
1718 PM8001_IO_DBG(pm8001_ha,
1719 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1720 ts->resp = SAS_TASK_COMPLETE;
1721 ts->stat = SAS_INTERRUPTED;
1722 break;
1723 case IO_XFER_ERROR_PHY_NOT_READY:
1724 PM8001_IO_DBG(pm8001_ha,
1725 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1726 ts->resp = SAS_TASK_COMPLETE;
1727 ts->stat = SAS_OPEN_REJECT;
1728 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1729 break;
1730 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1731 PM8001_IO_DBG(pm8001_ha,
1732 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1733 "_SUPPORTED\n"));
1734 ts->resp = SAS_TASK_COMPLETE;
1735 ts->stat = SAS_OPEN_REJECT;
1736 ts->open_rej_reason = SAS_OREJ_EPROTO;
1737 break;
1738 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1739 PM8001_IO_DBG(pm8001_ha,
1740 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1741 ts->resp = SAS_TASK_COMPLETE;
1742 ts->stat = SAS_OPEN_REJECT;
1743 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1744 break;
1745 case IO_OPEN_CNX_ERROR_BREAK:
1746 PM8001_IO_DBG(pm8001_ha,
1747 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1748 ts->resp = SAS_TASK_COMPLETE;
1749 ts->stat = SAS_OPEN_REJECT;
1750 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1751 break;
1752 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1753 PM8001_IO_DBG(pm8001_ha,
1754 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1755 ts->resp = SAS_TASK_COMPLETE;
1756 ts->stat = SAS_OPEN_REJECT;
1757 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1758 if (!t->uldd_task)
1759 pm8001_handle_event(pm8001_ha,
1760 pm8001_dev,
1761 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1762 break;
1763 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1764 PM8001_IO_DBG(pm8001_ha,
1765 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1766 ts->resp = SAS_TASK_COMPLETE;
1767 ts->stat = SAS_OPEN_REJECT;
1768 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1769 break;
1770 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1771 PM8001_IO_DBG(pm8001_ha,
1772 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1773 "NOT_SUPPORTED\n"));
1774 ts->resp = SAS_TASK_COMPLETE;
1775 ts->stat = SAS_OPEN_REJECT;
1776 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1777 break;
1778 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1779 PM8001_IO_DBG(pm8001_ha,
1780 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1781 ts->resp = SAS_TASK_COMPLETE;
1782 ts->stat = SAS_OPEN_REJECT;
1783 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1784 break;
1785 case IO_XFER_ERROR_NAK_RECEIVED:
1786 PM8001_IO_DBG(pm8001_ha,
1787 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1788 ts->resp = SAS_TASK_COMPLETE;
1789 ts->stat = SAS_OPEN_REJECT;
1790 break;
1791 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1792 PM8001_IO_DBG(pm8001_ha,
1793 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1794 ts->resp = SAS_TASK_COMPLETE;
1795 ts->stat = SAS_NAK_R_ERR;
1796 break;
1797 case IO_XFER_OPEN_RETRY_TIMEOUT:
1798 PM8001_IO_DBG(pm8001_ha,
1799 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1800 ts->resp = SAS_TASK_COMPLETE;
1801 ts->stat = SAS_OPEN_REJECT;
1802 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1803 break;
1804 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1805 PM8001_IO_DBG(pm8001_ha,
1806 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1807 ts->resp = SAS_TASK_COMPLETE;
1808 ts->stat = SAS_DATA_OVERRUN;
1809 break;
1810 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1811 PM8001_IO_DBG(pm8001_ha,
1812 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1813 ts->resp = SAS_TASK_COMPLETE;
1814 ts->stat = SAS_DATA_OVERRUN;
1815 break;
1816 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1817 PM8001_IO_DBG(pm8001_ha,
1818 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1819 ts->resp = SAS_TASK_COMPLETE;
1820 ts->stat = SAS_DATA_OVERRUN;
1821 break;
1822 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1823 PM8001_IO_DBG(pm8001_ha,
1824 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1825 ts->resp = SAS_TASK_COMPLETE;
1826 ts->stat = SAS_DATA_OVERRUN;
1827 break;
1828 case IO_XFER_ERROR_OFFSET_MISMATCH:
1829 PM8001_IO_DBG(pm8001_ha,
1830 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1831 ts->resp = SAS_TASK_COMPLETE;
1832 ts->stat = SAS_DATA_OVERRUN;
1833 break;
1834 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1835 PM8001_IO_DBG(pm8001_ha,
1836 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1837 ts->resp = SAS_TASK_COMPLETE;
1838 ts->stat = SAS_DATA_OVERRUN;
1839 break;
1840 case IO_XFER_CMD_FRAME_ISSUED:
1841 PM8001_IO_DBG(pm8001_ha,
1842 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
1843 return 0;
1844 default:
1845 PM8001_IO_DBG(pm8001_ha,
1846 pm8001_printk("Unknown status 0x%x\n", event));
1847 /* not allowed case. Therefore, return failed status */
1848 ts->resp = SAS_TASK_COMPLETE;
1849 ts->stat = SAS_DATA_OVERRUN;
1850 break;
1851 }
1852 spin_lock_irqsave(&t->task_state_lock, flags);
1853 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1854 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1855 t->task_state_flags |= SAS_TASK_STATE_DONE;
1856 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1857 spin_unlock_irqrestore(&t->task_state_lock, flags);
1858 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1859 " event 0x%x resp 0x%x "
1860 "stat 0x%x but aborted by upper layer!\n",
1861 t, event, ts->resp, ts->stat));
1862 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1863 } else {
1864 spin_unlock_irqrestore(&t->task_state_lock, flags);
1865 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1866 mb();/* in order to force CPU ordering */
1867 t->task_done(t);
1868 }
1869 return 0;
1870}
1871
1872/*See the comments for mpi_ssp_completion */
1873static int
1874mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1875{
1876 struct sas_task *t;
1877 struct pm8001_ccb_info *ccb;
1878 unsigned long flags;
1879 u32 param;
1880 u32 status;
1881 u32 tag;
1882 struct sata_completion_resp *psataPayload;
1883 struct task_status_struct *ts;
1884 struct ata_task_resp *resp ;
1885 u32 *sata_resp;
1886 struct pm8001_device *pm8001_dev;
1887
1888 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1889 status = le32_to_cpu(psataPayload->status);
1890 tag = le32_to_cpu(psataPayload->tag);
1891
1892 ccb = &pm8001_ha->ccb_info[tag];
1893 param = le32_to_cpu(psataPayload->param);
1894 t = ccb->task;
1895 ts = &t->task_status;
1896 pm8001_dev = ccb->device;
1897 if (status)
1898 PM8001_FAIL_DBG(pm8001_ha,
1899 pm8001_printk("sata IO status 0x%x\n", status));
1900 if (unlikely(!t || !t->lldd_task || !t->dev))
1901 return -1;
1902
1903 switch (status) {
1904 case IO_SUCCESS:
1905 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1906 if (param == 0) {
1907 ts->resp = SAS_TASK_COMPLETE;
1908 ts->stat = SAM_GOOD;
1909 } else {
1910 u8 len;
1911 ts->resp = SAS_TASK_COMPLETE;
1912 ts->stat = SAS_PROTO_RESPONSE;
1913 ts->residual = param;
1914 PM8001_IO_DBG(pm8001_ha,
1915 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1916 param));
1917 sata_resp = &psataPayload->sata_resp[0];
1918 resp = (struct ata_task_resp *)ts->buf;
1919 if (t->ata_task.dma_xfer == 0 &&
1920 t->data_dir == PCI_DMA_FROMDEVICE) {
1921 len = sizeof(struct pio_setup_fis);
1922 PM8001_IO_DBG(pm8001_ha,
1923 pm8001_printk("PIO read len = %d\n", len));
1924 } else if (t->ata_task.use_ncq) {
1925 len = sizeof(struct set_dev_bits_fis);
1926 PM8001_IO_DBG(pm8001_ha,
1927 pm8001_printk("FPDMA len = %d\n", len));
1928 } else {
1929 len = sizeof(struct dev_to_host_fis);
1930 PM8001_IO_DBG(pm8001_ha,
1931 pm8001_printk("other len = %d\n", len));
1932 }
1933 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1934 resp->frame_len = len;
1935 memcpy(&resp->ending_fis[0], sata_resp, len);
1936 ts->buf_valid_size = sizeof(*resp);
1937 } else
1938 PM8001_IO_DBG(pm8001_ha,
1939 pm8001_printk("response to large \n"));
1940 }
1941 if (pm8001_dev)
1942 pm8001_dev->running_req--;
1943 break;
1944 case IO_ABORTED:
1945 PM8001_IO_DBG(pm8001_ha,
1946 pm8001_printk("IO_ABORTED IOMB Tag \n"));
1947 ts->resp = SAS_TASK_COMPLETE;
1948 ts->stat = SAS_ABORTED_TASK;
1949 if (pm8001_dev)
1950 pm8001_dev->running_req--;
1951 break;
1952 /* following cases are to do cases */
1953 case IO_UNDERFLOW:
1954 /* SATA Completion with error */
1955 PM8001_IO_DBG(pm8001_ha,
1956 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1957 ts->resp = SAS_TASK_COMPLETE;
1958 ts->stat = SAS_DATA_UNDERRUN;
1959 ts->residual = param;
1960 if (pm8001_dev)
1961 pm8001_dev->running_req--;
1962 break;
1963 case IO_NO_DEVICE:
1964 PM8001_IO_DBG(pm8001_ha,
1965 pm8001_printk("IO_NO_DEVICE\n"));
1966 ts->resp = SAS_TASK_UNDELIVERED;
1967 ts->stat = SAS_PHY_DOWN;
1968 break;
1969 case IO_XFER_ERROR_BREAK:
1970 PM8001_IO_DBG(pm8001_ha,
1971 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1972 ts->resp = SAS_TASK_COMPLETE;
1973 ts->stat = SAS_INTERRUPTED;
1974 break;
1975 case IO_XFER_ERROR_PHY_NOT_READY:
1976 PM8001_IO_DBG(pm8001_ha,
1977 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1978 ts->resp = SAS_TASK_COMPLETE;
1979 ts->stat = SAS_OPEN_REJECT;
1980 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1981 break;
1982 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1983 PM8001_IO_DBG(pm8001_ha,
1984 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1985 "_SUPPORTED\n"));
1986 ts->resp = SAS_TASK_COMPLETE;
1987 ts->stat = SAS_OPEN_REJECT;
1988 ts->open_rej_reason = SAS_OREJ_EPROTO;
1989 break;
1990 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1991 PM8001_IO_DBG(pm8001_ha,
1992 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1993 ts->resp = SAS_TASK_COMPLETE;
1994 ts->stat = SAS_OPEN_REJECT;
1995 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1996 break;
1997 case IO_OPEN_CNX_ERROR_BREAK:
1998 PM8001_IO_DBG(pm8001_ha,
1999 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2000 ts->resp = SAS_TASK_COMPLETE;
2001 ts->stat = SAS_OPEN_REJECT;
2002 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2003 break;
2004 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2005 PM8001_IO_DBG(pm8001_ha,
2006 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2007 ts->resp = SAS_TASK_COMPLETE;
2008 ts->stat = SAS_DEV_NO_RESPONSE;
2009 if (!t->uldd_task) {
2010 pm8001_handle_event(pm8001_ha,
2011 pm8001_dev,
2012 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2013 ts->resp = SAS_TASK_UNDELIVERED;
2014 ts->stat = SAS_QUEUE_FULL;
2015 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2016 mb();/*in order to force CPU ordering*/
2017 t->task_done(t);
2018 return 0;
2019 }
2020 break;
2021 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2022 PM8001_IO_DBG(pm8001_ha,
2023 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2024 ts->resp = SAS_TASK_UNDELIVERED;
2025 ts->stat = SAS_OPEN_REJECT;
2026 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2027 if (!t->uldd_task) {
2028 pm8001_handle_event(pm8001_ha,
2029 pm8001_dev,
2030 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2031 ts->resp = SAS_TASK_UNDELIVERED;
2032 ts->stat = SAS_QUEUE_FULL;
2033 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2034 mb();/*ditto*/
2035 t->task_done(t);
2036 return 0;
2037 }
2038 break;
2039 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2040 PM8001_IO_DBG(pm8001_ha,
2041 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2042 "NOT_SUPPORTED\n"));
2043 ts->resp = SAS_TASK_COMPLETE;
2044 ts->stat = SAS_OPEN_REJECT;
2045 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2046 break;
2047 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2048 PM8001_IO_DBG(pm8001_ha,
2049 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2050 "_BUSY\n"));
2051 ts->resp = SAS_TASK_COMPLETE;
2052 ts->stat = SAS_DEV_NO_RESPONSE;
2053 if (!t->uldd_task) {
2054 pm8001_handle_event(pm8001_ha,
2055 pm8001_dev,
2056 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2057 ts->resp = SAS_TASK_UNDELIVERED;
2058 ts->stat = SAS_QUEUE_FULL;
2059 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2060 mb();/* ditto*/
2061 t->task_done(t);
2062 return 0;
2063 }
2064 break;
2065 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2066 PM8001_IO_DBG(pm8001_ha,
2067 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2068 ts->resp = SAS_TASK_COMPLETE;
2069 ts->stat = SAS_OPEN_REJECT;
2070 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2071 break;
2072 case IO_XFER_ERROR_NAK_RECEIVED:
2073 PM8001_IO_DBG(pm8001_ha,
2074 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2075 ts->resp = SAS_TASK_COMPLETE;
2076 ts->stat = SAS_NAK_R_ERR;
2077 break;
2078 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2079 PM8001_IO_DBG(pm8001_ha,
2080 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2081 ts->resp = SAS_TASK_COMPLETE;
2082 ts->stat = SAS_NAK_R_ERR;
2083 break;
2084 case IO_XFER_ERROR_DMA:
2085 PM8001_IO_DBG(pm8001_ha,
2086 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2087 ts->resp = SAS_TASK_COMPLETE;
2088 ts->stat = SAS_ABORTED_TASK;
2089 break;
2090 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2091 PM8001_IO_DBG(pm8001_ha,
2092 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2093 ts->resp = SAS_TASK_UNDELIVERED;
2094 ts->stat = SAS_DEV_NO_RESPONSE;
2095 break;
2096 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2097 PM8001_IO_DBG(pm8001_ha,
2098 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2099 ts->resp = SAS_TASK_COMPLETE;
2100 ts->stat = SAS_DATA_UNDERRUN;
2101 break;
2102 case IO_XFER_OPEN_RETRY_TIMEOUT:
2103 PM8001_IO_DBG(pm8001_ha,
2104 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2105 ts->resp = SAS_TASK_COMPLETE;
2106 ts->stat = SAS_OPEN_TO;
2107 break;
2108 case IO_PORT_IN_RESET:
2109 PM8001_IO_DBG(pm8001_ha,
2110 pm8001_printk("IO_PORT_IN_RESET\n"));
2111 ts->resp = SAS_TASK_COMPLETE;
2112 ts->stat = SAS_DEV_NO_RESPONSE;
2113 break;
2114 case IO_DS_NON_OPERATIONAL:
2115 PM8001_IO_DBG(pm8001_ha,
2116 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2117 ts->resp = SAS_TASK_COMPLETE;
2118 ts->stat = SAS_DEV_NO_RESPONSE;
2119 if (!t->uldd_task) {
2120 pm8001_handle_event(pm8001_ha, pm8001_dev,
2121 IO_DS_NON_OPERATIONAL);
2122 ts->resp = SAS_TASK_UNDELIVERED;
2123 ts->stat = SAS_QUEUE_FULL;
2124 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2125 mb();/*ditto*/
2126 t->task_done(t);
2127 return 0;
2128 }
2129 break;
2130 case IO_DS_IN_RECOVERY:
2131 PM8001_IO_DBG(pm8001_ha,
2132 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2133 ts->resp = SAS_TASK_COMPLETE;
2134 ts->stat = SAS_DEV_NO_RESPONSE;
2135 break;
2136 case IO_DS_IN_ERROR:
2137 PM8001_IO_DBG(pm8001_ha,
2138 pm8001_printk("IO_DS_IN_ERROR\n"));
2139 ts->resp = SAS_TASK_COMPLETE;
2140 ts->stat = SAS_DEV_NO_RESPONSE;
2141 if (!t->uldd_task) {
2142 pm8001_handle_event(pm8001_ha, pm8001_dev,
2143 IO_DS_IN_ERROR);
2144 ts->resp = SAS_TASK_UNDELIVERED;
2145 ts->stat = SAS_QUEUE_FULL;
2146 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2147 mb();/*ditto*/
2148 t->task_done(t);
2149 return 0;
2150 }
2151 break;
2152 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2153 PM8001_IO_DBG(pm8001_ha,
2154 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2155 ts->resp = SAS_TASK_COMPLETE;
2156 ts->stat = SAS_OPEN_REJECT;
2157 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2158 default:
2159 PM8001_IO_DBG(pm8001_ha,
2160 pm8001_printk("Unknown status 0x%x\n", status));
2161 /* not allowed case. Therefore, return failed status */
2162 ts->resp = SAS_TASK_COMPLETE;
2163 ts->stat = SAS_DEV_NO_RESPONSE;
2164 break;
2165 }
2166 spin_lock_irqsave(&t->task_state_lock, flags);
2167 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2168 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2169 t->task_state_flags |= SAS_TASK_STATE_DONE;
2170 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2171 spin_unlock_irqrestore(&t->task_state_lock, flags);
2172 PM8001_FAIL_DBG(pm8001_ha,
2173 pm8001_printk("task 0x%p done with io_status 0x%x"
2174 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2175 t, status, ts->resp, ts->stat));
2176 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2177 } else {
2178 spin_unlock_irqrestore(&t->task_state_lock, flags);
2179 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2180 mb();/* ditto */
2181 t->task_done(t);
2182 }
2183 return 0;
2184}
2185
2186/*See the comments for mpi_ssp_completion */
2187static int mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2188{
2189 struct sas_task *t;
2190 unsigned long flags;
2191 struct task_status_struct *ts;
2192 struct pm8001_ccb_info *ccb;
2193 struct pm8001_device *pm8001_dev;
2194 struct sata_event_resp *psataPayload =
2195 (struct sata_event_resp *)(piomb + 4);
2196 u32 event = le32_to_cpu(psataPayload->event);
2197 u32 tag = le32_to_cpu(psataPayload->tag);
2198 u32 port_id = le32_to_cpu(psataPayload->port_id);
2199 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2200
2201 ccb = &pm8001_ha->ccb_info[tag];
2202 t = ccb->task;
2203 pm8001_dev = ccb->device;
2204 if (event)
2205 PM8001_FAIL_DBG(pm8001_ha,
2206 pm8001_printk("sata IO status 0x%x\n", event));
2207 if (unlikely(!t || !t->lldd_task || !t->dev))
2208 return -1;
2209 ts = &t->task_status;
2210 PM8001_IO_DBG(pm8001_ha,
2211 pm8001_printk("port_id = %x,device_id = %x\n",
2212 port_id, dev_id));
2213 switch (event) {
2214 case IO_OVERFLOW:
2215 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2216 ts->resp = SAS_TASK_COMPLETE;
2217 ts->stat = SAS_DATA_OVERRUN;
2218 ts->residual = 0;
2219 if (pm8001_dev)
2220 pm8001_dev->running_req--;
2221 break;
2222 case IO_XFER_ERROR_BREAK:
2223 PM8001_IO_DBG(pm8001_ha,
2224 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2225 ts->resp = SAS_TASK_COMPLETE;
2226 ts->stat = SAS_INTERRUPTED;
2227 break;
2228 case IO_XFER_ERROR_PHY_NOT_READY:
2229 PM8001_IO_DBG(pm8001_ha,
2230 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2231 ts->resp = SAS_TASK_COMPLETE;
2232 ts->stat = SAS_OPEN_REJECT;
2233 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2234 break;
2235 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2236 PM8001_IO_DBG(pm8001_ha,
2237 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2238 "_SUPPORTED\n"));
2239 ts->resp = SAS_TASK_COMPLETE;
2240 ts->stat = SAS_OPEN_REJECT;
2241 ts->open_rej_reason = SAS_OREJ_EPROTO;
2242 break;
2243 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2244 PM8001_IO_DBG(pm8001_ha,
2245 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2246 ts->resp = SAS_TASK_COMPLETE;
2247 ts->stat = SAS_OPEN_REJECT;
2248 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2249 break;
2250 case IO_OPEN_CNX_ERROR_BREAK:
2251 PM8001_IO_DBG(pm8001_ha,
2252 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2253 ts->resp = SAS_TASK_COMPLETE;
2254 ts->stat = SAS_OPEN_REJECT;
2255 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2256 break;
2257 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2260 ts->resp = SAS_TASK_UNDELIVERED;
2261 ts->stat = SAS_DEV_NO_RESPONSE;
2262 if (!t->uldd_task) {
2263 pm8001_handle_event(pm8001_ha,
2264 pm8001_dev,
2265 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2266 ts->resp = SAS_TASK_COMPLETE;
2267 ts->stat = SAS_QUEUE_FULL;
2268 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2269 mb();/*ditto*/
2270 t->task_done(t);
2271 return 0;
2272 }
2273 break;
2274 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2275 PM8001_IO_DBG(pm8001_ha,
2276 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2277 ts->resp = SAS_TASK_UNDELIVERED;
2278 ts->stat = SAS_OPEN_REJECT;
2279 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2280 break;
2281 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2282 PM8001_IO_DBG(pm8001_ha,
2283 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2284 "NOT_SUPPORTED\n"));
2285 ts->resp = SAS_TASK_COMPLETE;
2286 ts->stat = SAS_OPEN_REJECT;
2287 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2288 break;
2289 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2290 PM8001_IO_DBG(pm8001_ha,
2291 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2292 ts->resp = SAS_TASK_COMPLETE;
2293 ts->stat = SAS_OPEN_REJECT;
2294 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2295 break;
2296 case IO_XFER_ERROR_NAK_RECEIVED:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2299 ts->resp = SAS_TASK_COMPLETE;
2300 ts->stat = SAS_NAK_R_ERR;
2301 break;
2302 case IO_XFER_ERROR_PEER_ABORTED:
2303 PM8001_IO_DBG(pm8001_ha,
2304 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2305 ts->resp = SAS_TASK_COMPLETE;
2306 ts->stat = SAS_NAK_R_ERR;
2307 break;
2308 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2309 PM8001_IO_DBG(pm8001_ha,
2310 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2311 ts->resp = SAS_TASK_COMPLETE;
2312 ts->stat = SAS_DATA_UNDERRUN;
2313 break;
2314 case IO_XFER_OPEN_RETRY_TIMEOUT:
2315 PM8001_IO_DBG(pm8001_ha,
2316 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2317 ts->resp = SAS_TASK_COMPLETE;
2318 ts->stat = SAS_OPEN_TO;
2319 break;
2320 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2321 PM8001_IO_DBG(pm8001_ha,
2322 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2323 ts->resp = SAS_TASK_COMPLETE;
2324 ts->stat = SAS_OPEN_TO;
2325 break;
2326 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2327 PM8001_IO_DBG(pm8001_ha,
2328 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2329 ts->resp = SAS_TASK_COMPLETE;
2330 ts->stat = SAS_OPEN_TO;
2331 break;
2332 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2333 PM8001_IO_DBG(pm8001_ha,
2334 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2335 ts->resp = SAS_TASK_COMPLETE;
2336 ts->stat = SAS_OPEN_TO;
2337 break;
2338 case IO_XFER_ERROR_OFFSET_MISMATCH:
2339 PM8001_IO_DBG(pm8001_ha,
2340 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2341 ts->resp = SAS_TASK_COMPLETE;
2342 ts->stat = SAS_OPEN_TO;
2343 break;
2344 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2345 PM8001_IO_DBG(pm8001_ha,
2346 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_OPEN_TO;
2349 break;
2350 case IO_XFER_CMD_FRAME_ISSUED:
2351 PM8001_IO_DBG(pm8001_ha,
2352 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2353 break;
2354 case IO_XFER_PIO_SETUP_ERROR:
2355 PM8001_IO_DBG(pm8001_ha,
2356 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2357 ts->resp = SAS_TASK_COMPLETE;
2358 ts->stat = SAS_OPEN_TO;
2359 break;
2360 default:
2361 PM8001_IO_DBG(pm8001_ha,
2362 pm8001_printk("Unknown status 0x%x\n", event));
2363 /* not allowed case. Therefore, return failed status */
2364 ts->resp = SAS_TASK_COMPLETE;
2365 ts->stat = SAS_OPEN_TO;
2366 break;
2367 }
2368 spin_lock_irqsave(&t->task_state_lock, flags);
2369 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2370 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2371 t->task_state_flags |= SAS_TASK_STATE_DONE;
2372 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2373 spin_unlock_irqrestore(&t->task_state_lock, flags);
2374 PM8001_FAIL_DBG(pm8001_ha,
2375 pm8001_printk("task 0x%p done with io_status 0x%x"
2376 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2377 t, event, ts->resp, ts->stat));
2378 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2379 } else {
2380 spin_unlock_irqrestore(&t->task_state_lock, flags);
2381 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2382 mb();/* in order to force CPU ordering */
2383 t->task_done(t);
2384 }
2385 return 0;
2386}
2387
2388/*See the comments for mpi_ssp_completion */
2389static int
2390mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2391{
2392 u32 param;
2393 struct sas_task *t;
2394 struct pm8001_ccb_info *ccb;
2395 unsigned long flags;
2396 u32 status;
2397 u32 tag;
2398 struct smp_completion_resp *psmpPayload;
2399 struct task_status_struct *ts;
2400 struct pm8001_device *pm8001_dev;
2401
2402 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2403 status = le32_to_cpu(psmpPayload->status);
2404 tag = le32_to_cpu(psmpPayload->tag);
2405
2406 ccb = &pm8001_ha->ccb_info[tag];
2407 param = le32_to_cpu(psmpPayload->param);
2408 t = ccb->task;
2409 ts = &t->task_status;
2410 pm8001_dev = ccb->device;
2411 if (status)
2412 PM8001_FAIL_DBG(pm8001_ha,
2413 pm8001_printk("smp IO status 0x%x\n", status));
2414 if (unlikely(!t || !t->lldd_task || !t->dev))
2415 return -1;
2416
2417 switch (status) {
2418 case IO_SUCCESS:
2419 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2420 ts->resp = SAS_TASK_COMPLETE;
2421 ts->stat = SAM_GOOD;
2422 if (pm8001_dev)
2423 pm8001_dev->running_req--;
2424 break;
2425 case IO_ABORTED:
2426 PM8001_IO_DBG(pm8001_ha,
2427 pm8001_printk("IO_ABORTED IOMB\n"));
2428 ts->resp = SAS_TASK_COMPLETE;
2429 ts->stat = SAS_ABORTED_TASK;
2430 if (pm8001_dev)
2431 pm8001_dev->running_req--;
2432 break;
2433 case IO_OVERFLOW:
2434 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2435 ts->resp = SAS_TASK_COMPLETE;
2436 ts->stat = SAS_DATA_OVERRUN;
2437 ts->residual = 0;
2438 if (pm8001_dev)
2439 pm8001_dev->running_req--;
2440 break;
2441 case IO_NO_DEVICE:
2442 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2443 ts->resp = SAS_TASK_COMPLETE;
2444 ts->stat = SAS_PHY_DOWN;
2445 break;
2446 case IO_ERROR_HW_TIMEOUT:
2447 PM8001_IO_DBG(pm8001_ha,
2448 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2449 ts->resp = SAS_TASK_COMPLETE;
2450 ts->stat = SAM_BUSY;
2451 break;
2452 case IO_XFER_ERROR_BREAK:
2453 PM8001_IO_DBG(pm8001_ha,
2454 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2455 ts->resp = SAS_TASK_COMPLETE;
2456 ts->stat = SAM_BUSY;
2457 break;
2458 case IO_XFER_ERROR_PHY_NOT_READY:
2459 PM8001_IO_DBG(pm8001_ha,
2460 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2461 ts->resp = SAS_TASK_COMPLETE;
2462 ts->stat = SAM_BUSY;
2463 break;
2464 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2465 PM8001_IO_DBG(pm8001_ha,
2466 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2467 ts->resp = SAS_TASK_COMPLETE;
2468 ts->stat = SAS_OPEN_REJECT;
2469 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2470 break;
2471 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2472 PM8001_IO_DBG(pm8001_ha,
2473 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2474 ts->resp = SAS_TASK_COMPLETE;
2475 ts->stat = SAS_OPEN_REJECT;
2476 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2477 break;
2478 case IO_OPEN_CNX_ERROR_BREAK:
2479 PM8001_IO_DBG(pm8001_ha,
2480 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2481 ts->resp = SAS_TASK_COMPLETE;
2482 ts->stat = SAS_OPEN_REJECT;
2483 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2484 break;
2485 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2486 PM8001_IO_DBG(pm8001_ha,
2487 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2488 ts->resp = SAS_TASK_COMPLETE;
2489 ts->stat = SAS_OPEN_REJECT;
2490 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2491 pm8001_handle_event(pm8001_ha,
2492 pm8001_dev,
2493 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2494 break;
2495 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2496 PM8001_IO_DBG(pm8001_ha,
2497 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2498 ts->resp = SAS_TASK_COMPLETE;
2499 ts->stat = SAS_OPEN_REJECT;
2500 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2501 break;
2502 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2503 PM8001_IO_DBG(pm8001_ha,
2504 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2505 "NOT_SUPPORTED\n"));
2506 ts->resp = SAS_TASK_COMPLETE;
2507 ts->stat = SAS_OPEN_REJECT;
2508 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2509 break;
2510 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2511 PM8001_IO_DBG(pm8001_ha,
2512 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2513 ts->resp = SAS_TASK_COMPLETE;
2514 ts->stat = SAS_OPEN_REJECT;
2515 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2516 break;
2517 case IO_XFER_ERROR_RX_FRAME:
2518 PM8001_IO_DBG(pm8001_ha,
2519 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2520 ts->resp = SAS_TASK_COMPLETE;
2521 ts->stat = SAS_DEV_NO_RESPONSE;
2522 break;
2523 case IO_XFER_OPEN_RETRY_TIMEOUT:
2524 PM8001_IO_DBG(pm8001_ha,
2525 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2526 ts->resp = SAS_TASK_COMPLETE;
2527 ts->stat = SAS_OPEN_REJECT;
2528 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2529 break;
2530 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2531 PM8001_IO_DBG(pm8001_ha,
2532 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2533 ts->resp = SAS_TASK_COMPLETE;
2534 ts->stat = SAS_QUEUE_FULL;
2535 break;
2536 case IO_PORT_IN_RESET:
2537 PM8001_IO_DBG(pm8001_ha,
2538 pm8001_printk("IO_PORT_IN_RESET\n"));
2539 ts->resp = SAS_TASK_COMPLETE;
2540 ts->stat = SAS_OPEN_REJECT;
2541 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2542 break;
2543 case IO_DS_NON_OPERATIONAL:
2544 PM8001_IO_DBG(pm8001_ha,
2545 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2546 ts->resp = SAS_TASK_COMPLETE;
2547 ts->stat = SAS_DEV_NO_RESPONSE;
2548 break;
2549 case IO_DS_IN_RECOVERY:
2550 PM8001_IO_DBG(pm8001_ha,
2551 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2552 ts->resp = SAS_TASK_COMPLETE;
2553 ts->stat = SAS_OPEN_REJECT;
2554 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2555 break;
2556 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2557 PM8001_IO_DBG(pm8001_ha,
2558 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2559 ts->resp = SAS_TASK_COMPLETE;
2560 ts->stat = SAS_OPEN_REJECT;
2561 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2562 break;
2563 default:
2564 PM8001_IO_DBG(pm8001_ha,
2565 pm8001_printk("Unknown status 0x%x\n", status));
2566 ts->resp = SAS_TASK_COMPLETE;
2567 ts->stat = SAS_DEV_NO_RESPONSE;
2568 /* not allowed case. Therefore, return failed status */
2569 break;
2570 }
2571 spin_lock_irqsave(&t->task_state_lock, flags);
2572 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2573 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2574 t->task_state_flags |= SAS_TASK_STATE_DONE;
2575 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2576 spin_unlock_irqrestore(&t->task_state_lock, flags);
2577 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2578 " io_status 0x%x resp 0x%x "
2579 "stat 0x%x but aborted by upper layer!\n",
2580 t, status, ts->resp, ts->stat));
2581 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2582 } else {
2583 spin_unlock_irqrestore(&t->task_state_lock, flags);
2584 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2585 mb();/* in order to force CPU ordering */
2586 t->task_done(t);
2587 }
2588 return 0;
2589}
2590
2591static void
2592mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2593{
2594 struct set_dev_state_resp *pPayload =
2595 (struct set_dev_state_resp *)(piomb + 4);
2596 u32 tag = le32_to_cpu(pPayload->tag);
2597 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2598 struct pm8001_device *pm8001_dev = ccb->device;
2599 u32 status = le32_to_cpu(pPayload->status);
2600 u32 device_id = le32_to_cpu(pPayload->device_id);
2601 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2602 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2603 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2604 "from 0x%x to 0x%x status = 0x%x!\n",
2605 device_id, pds, nds, status));
2606 complete(pm8001_dev->setds_completion);
2607 ccb->task = NULL;
2608 ccb->ccb_tag = 0xFFFFFFFF;
2609 pm8001_ccb_free(pm8001_ha, tag);
2610}
2611
2612static void
2613mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2614{
2615 struct get_nvm_data_resp *pPayload =
2616 (struct get_nvm_data_resp *)(piomb + 4);
2617 u32 tag = le32_to_cpu(pPayload->tag);
2618 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2619 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2620 complete(pm8001_ha->nvmd_completion);
2621 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2622 if ((dlen_status & NVMD_STAT) != 0) {
2623 PM8001_FAIL_DBG(pm8001_ha,
2624 pm8001_printk("Set nvm data error!\n"));
2625 return;
2626 }
2627 ccb->task = NULL;
2628 ccb->ccb_tag = 0xFFFFFFFF;
2629 pm8001_ccb_free(pm8001_ha, tag);
2630}
2631
2632static void
2633mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2634{
2635 struct fw_control_ex *fw_control_context;
2636 struct get_nvm_data_resp *pPayload =
2637 (struct get_nvm_data_resp *)(piomb + 4);
2638 u32 tag = le32_to_cpu(pPayload->tag);
2639 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2640 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2641 u32 ir_tds_bn_dps_das_nvm =
2642 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2643 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2644 fw_control_context = ccb->fw_control_context;
2645
2646 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2647 if ((dlen_status & NVMD_STAT) != 0) {
2648 PM8001_FAIL_DBG(pm8001_ha,
2649 pm8001_printk("Get nvm data error!\n"));
2650 complete(pm8001_ha->nvmd_completion);
2651 return;
2652 }
2653
2654 if (ir_tds_bn_dps_das_nvm & IPMode) {
2655 /* indirect mode - IR bit set */
2656 PM8001_MSG_DBG(pm8001_ha,
2657 pm8001_printk("Get NVMD success, IR=1\n"));
2658 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2659 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2660 memcpy(pm8001_ha->sas_addr,
2661 ((u8 *)virt_addr + 4),
2662 SAS_ADDR_SIZE);
2663 PM8001_MSG_DBG(pm8001_ha,
2664 pm8001_printk("Get SAS address"
2665 " from VPD successfully!\n"));
2666 }
2667 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2668 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2669 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2670 ;
2671 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2672 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2673 ;
2674 } else {
2675 /* Should not be happened*/
2676 PM8001_MSG_DBG(pm8001_ha,
2677 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2678 ir_tds_bn_dps_das_nvm));
2679 }
2680 } else /* direct mode */{
2681 PM8001_MSG_DBG(pm8001_ha,
2682 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2683 (dlen_status & NVMD_LEN) >> 24));
2684 }
2685 memcpy((void *)(fw_control_context->usrAddr),
2686 (void *)(pm8001_ha->memoryMap.region[NVMD].virt_ptr),
2687 fw_control_context->len);
2688 complete(pm8001_ha->nvmd_completion);
2689 ccb->task = NULL;
2690 ccb->ccb_tag = 0xFFFFFFFF;
2691 pm8001_ccb_free(pm8001_ha, tag);
2692}
2693
2694static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2695{
2696 struct local_phy_ctl_resp *pPayload =
2697 (struct local_phy_ctl_resp *)(piomb + 4);
2698 u32 status = le32_to_cpu(pPayload->status);
2699 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2700 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2701 if (status != 0) {
2702 PM8001_MSG_DBG(pm8001_ha,
2703 pm8001_printk("%x phy execute %x phy op failed! \n",
2704 phy_id, phy_op));
2705 } else
2706 PM8001_MSG_DBG(pm8001_ha,
2707 pm8001_printk("%x phy execute %x phy op success! \n",
2708 phy_id, phy_op));
2709 return 0;
2710}
2711
2712/**
2713 * pm8001_bytes_dmaed - one of the interface function communication with libsas
2714 * @pm8001_ha: our hba card information
2715 * @i: which phy that received the event.
2716 *
2717 * when HBA driver received the identify done event or initiate FIS received
2718 * event(for SATA), it will invoke this function to notify the sas layer that
2719 * the sas toplogy has formed, please discover the the whole sas domain,
2720 * while receive a broadcast(change) primitive just tell the sas
2721 * layer to discover the changed domain rather than the whole domain.
2722 */
2723static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2724{
2725 struct pm8001_phy *phy = &pm8001_ha->phy[i];
2726 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2727 struct sas_ha_struct *sas_ha;
2728 if (!phy->phy_attached)
2729 return;
2730
2731 sas_ha = pm8001_ha->sas;
2732 if (sas_phy->phy) {
2733 struct sas_phy *sphy = sas_phy->phy;
2734 sphy->negotiated_linkrate = sas_phy->linkrate;
2735 sphy->minimum_linkrate = phy->minimum_linkrate;
2736 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2737 sphy->maximum_linkrate = phy->maximum_linkrate;
2738 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2739 }
2740
2741 if (phy->phy_type & PORT_TYPE_SAS) {
2742 struct sas_identify_frame *id;
2743 id = (struct sas_identify_frame *)phy->frame_rcvd;
2744 id->dev_type = phy->identify.device_type;
2745 id->initiator_bits = SAS_PROTOCOL_ALL;
2746 id->target_bits = phy->identify.target_port_protocols;
2747 } else if (phy->phy_type & PORT_TYPE_SATA) {
2748 /*Nothing*/
2749 }
2750 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2751
2752 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2753 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2754}
2755
2756/* Get the link rate speed */
2757static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2758{
2759 struct sas_phy *sas_phy = phy->sas_phy.phy;
2760
2761 switch (link_rate) {
2762 case PHY_SPEED_60:
2763 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2764 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2765 break;
2766 case PHY_SPEED_30:
2767 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
2768 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
2769 break;
2770 case PHY_SPEED_15:
2771 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
2772 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
2773 break;
2774 }
2775 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
2776 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
2777 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2778 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
2779 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
2780}
2781
2782/**
2783 * asd_get_attached_sas_addr -- extract/generate attached SAS address
2784 * @phy: pointer to asd_phy
2785 * @sas_addr: pointer to buffer where the SAS address is to be written
2786 *
2787 * This function extracts the SAS address from an IDENTIFY frame
2788 * received. If OOB is SATA, then a SAS address is generated from the
2789 * HA tables.
2790 *
2791 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
2792 * buffer.
2793 */
2794static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
2795 u8 *sas_addr)
2796{
2797 if (phy->sas_phy.frame_rcvd[0] == 0x34
2798 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
2799 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
2800 /* FIS device-to-host */
2801 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
2802 addr += phy->sas_phy.id;
2803 *(__be64 *)sas_addr = cpu_to_be64(addr);
2804 } else {
2805 struct sas_identify_frame *idframe =
2806 (void *) phy->sas_phy.frame_rcvd;
2807 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
2808 }
2809}
2810
2811/**
2812 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2813 * @pm8001_ha: our hba card information
2814 * @Qnum: the outbound queue message number.
2815 * @SEA: source of event to ack
2816 * @port_id: port id.
2817 * @phyId: phy id.
2818 * @param0: parameter 0.
2819 * @param1: parameter 1.
2820 */
2821static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2822 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2823{
2824 struct hw_event_ack_req payload;
2825 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2826
2827 struct inbound_queue_table *circularQ;
2828
2829 memset((u8 *)&payload, 0, sizeof(payload));
2830 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2831 payload.tag = 1;
2832 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2833 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
2834 payload.param0 = cpu_to_le32(param0);
2835 payload.param1 = cpu_to_le32(param1);
2836 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
2837}
2838
2839static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2840 u32 phyId, u32 phy_op);
2841
2842/**
2843 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2844 * @pm8001_ha: our hba card information
2845 * @piomb: IO message buffer
2846 */
2847static void
2848hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2849{
2850 struct hw_event_resp *pPayload =
2851 (struct hw_event_resp *)(piomb + 4);
2852 u32 lr_evt_status_phyid_portid =
2853 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2854 u8 link_rate =
2855 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2856 u8 phy_id =
2857 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2858 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2859 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2860 unsigned long flags;
2861 u8 deviceType = pPayload->sas_identify.dev_type;
2862
2863 PM8001_MSG_DBG(pm8001_ha,
2864 pm8001_printk("HW_EVENT_SAS_PHY_UP \n"));
2865
2866 switch (deviceType) {
2867 case SAS_PHY_UNUSED:
2868 PM8001_MSG_DBG(pm8001_ha,
2869 pm8001_printk("device type no device.\n"));
2870 break;
2871 case SAS_END_DEVICE:
2872 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2873 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
2874 PHY_NOTIFY_ENABLE_SPINUP);
2875 get_lrate_mode(phy, link_rate);
2876 break;
2877 case SAS_EDGE_EXPANDER_DEVICE:
2878 PM8001_MSG_DBG(pm8001_ha,
2879 pm8001_printk("expander device.\n"));
2880 get_lrate_mode(phy, link_rate);
2881 break;
2882 case SAS_FANOUT_EXPANDER_DEVICE:
2883 PM8001_MSG_DBG(pm8001_ha,
2884 pm8001_printk("fanout expander device.\n"));
2885 get_lrate_mode(phy, link_rate);
2886 break;
2887 default:
2888 PM8001_MSG_DBG(pm8001_ha,
2889 pm8001_printk("unkown device type(%x)\n", deviceType));
2890 break;
2891 }
2892 phy->phy_type |= PORT_TYPE_SAS;
2893 phy->identify.device_type = deviceType;
2894 phy->phy_attached = 1;
2895 if (phy->identify.device_type == SAS_END_DEV)
2896 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2897 else if (phy->identify.device_type != NO_DEVICE)
2898 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2899 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2900 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2901 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2902 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2903 sizeof(struct sas_identify_frame)-4);
2904 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2905 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2906 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2907 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2908 mdelay(200);/*delay a moment to wait disk to spinup*/
2909 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2910}
2911
2912/**
2913 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2914 * @pm8001_ha: our hba card information
2915 * @piomb: IO message buffer
2916 */
2917static void
2918hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2919{
2920 struct hw_event_resp *pPayload =
2921 (struct hw_event_resp *)(piomb + 4);
2922 u32 lr_evt_status_phyid_portid =
2923 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2924 u8 link_rate =
2925 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2926 u8 phy_id =
2927 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2928 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2929 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2930 unsigned long flags;
2931 get_lrate_mode(phy, link_rate);
2932 phy->phy_type |= PORT_TYPE_SATA;
2933 phy->phy_attached = 1;
2934 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2935 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2936 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2937 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2938 sizeof(struct dev_to_host_fis));
2939 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2940 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2941 phy->identify.device_type = SATA_DEV;
2942 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2943 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2944 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2945}
2946
2947/**
2948 * hw_event_phy_down -we should notify the libsas the phy is down.
2949 * @pm8001_ha: our hba card information
2950 * @piomb: IO message buffer
2951 */
2952static void
2953hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2954{
2955 struct hw_event_resp *pPayload =
2956 (struct hw_event_resp *)(piomb + 4);
2957 u32 lr_evt_status_phyid_portid =
2958 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2959 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2960 u8 phy_id =
2961 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2962 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2963 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2964
2965 switch (portstate) {
2966 case PORT_VALID:
2967 break;
2968 case PORT_INVALID:
2969 PM8001_MSG_DBG(pm8001_ha,
2970 pm8001_printk(" PortInvalid portID %d \n", port_id));
2971 PM8001_MSG_DBG(pm8001_ha,
2972 pm8001_printk(" Last phy Down and port invalid\n"));
2973 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2974 port_id, phy_id, 0, 0);
2975 break;
2976 case PORT_IN_RESET:
2977 PM8001_MSG_DBG(pm8001_ha,
2978 pm8001_printk(" PortInReset portID %d \n", port_id));
2979 break;
2980 case PORT_NOT_ESTABLISHED:
2981 PM8001_MSG_DBG(pm8001_ha,
2982 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2983 break;
2984 case PORT_LOSTCOMM:
2985 PM8001_MSG_DBG(pm8001_ha,
2986 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2987 PM8001_MSG_DBG(pm8001_ha,
2988 pm8001_printk(" Last phy Down and port invalid\n"));
2989 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2990 port_id, phy_id, 0, 0);
2991 break;
2992 default:
2993 PM8001_MSG_DBG(pm8001_ha,
2994 pm8001_printk(" phy Down and(default) = %x\n",
2995 portstate));
2996 break;
2997
2998 }
2999}
3000
3001/**
3002 * mpi_reg_resp -process register device ID response.
3003 * @pm8001_ha: our hba card information
3004 * @piomb: IO message buffer
3005 *
3006 * when sas layer find a device it will notify LLDD, then the driver register
3007 * the domain device to FW, this event is the return device ID which the FW
3008 * has assigned, from now,inter-communication with FW is no longer using the
3009 * SAS address, use device ID which FW assigned.
3010 */
3011static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3012{
3013 u32 status;
3014 u32 device_id;
3015 u32 htag;
3016 struct pm8001_ccb_info *ccb;
3017 struct pm8001_device *pm8001_dev;
3018 struct dev_reg_resp *registerRespPayload =
3019 (struct dev_reg_resp *)(piomb + 4);
3020
3021 htag = le32_to_cpu(registerRespPayload->tag);
3022 ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
3023 pm8001_dev = ccb->device;
3024 status = le32_to_cpu(registerRespPayload->status);
3025 device_id = le32_to_cpu(registerRespPayload->device_id);
3026 PM8001_MSG_DBG(pm8001_ha,
3027 pm8001_printk(" register device is status = %d\n", status));
3028 switch (status) {
3029 case DEVREG_SUCCESS:
3030 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3031 pm8001_dev->device_id = device_id;
3032 break;
3033 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3034 PM8001_MSG_DBG(pm8001_ha,
3035 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3036 break;
3037 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3038 PM8001_MSG_DBG(pm8001_ha,
3039 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3040 break;
3041 case DEVREG_FAILURE_INVALID_PHY_ID:
3042 PM8001_MSG_DBG(pm8001_ha,
3043 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3044 break;
3045 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3046 PM8001_MSG_DBG(pm8001_ha,
3047 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3048 break;
3049 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3050 PM8001_MSG_DBG(pm8001_ha,
3051 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3052 break;
3053 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3054 PM8001_MSG_DBG(pm8001_ha,
3055 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3056 break;
3057 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3058 PM8001_MSG_DBG(pm8001_ha,
3059 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3060 break;
3061 default:
3062 PM8001_MSG_DBG(pm8001_ha,
3063 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3064 break;
3065 }
3066 complete(pm8001_dev->dcompletion);
3067 ccb->task = NULL;
3068 ccb->ccb_tag = 0xFFFFFFFF;
3069 pm8001_ccb_free(pm8001_ha, htag);
3070 return 0;
3071}
3072
3073static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3074{
3075 u32 status;
3076 u32 device_id;
3077 struct dev_reg_resp *registerRespPayload =
3078 (struct dev_reg_resp *)(piomb + 4);
3079
3080 status = le32_to_cpu(registerRespPayload->status);
3081 device_id = le32_to_cpu(registerRespPayload->device_id);
3082 if (status != 0)
3083 PM8001_MSG_DBG(pm8001_ha,
3084 pm8001_printk(" deregister device failed ,status = %x"
3085 ", device_id = %x\n", status, device_id));
3086 return 0;
3087}
3088
3089static int
3090mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3091{
3092 u32 status;
3093 struct fw_control_ex fw_control_context;
3094 struct fw_flash_Update_resp *ppayload =
3095 (struct fw_flash_Update_resp *)(piomb + 4);
3096 u32 tag = le32_to_cpu(ppayload->tag);
3097 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3098 status = le32_to_cpu(ppayload->status);
3099 memcpy(&fw_control_context,
3100 ccb->fw_control_context,
3101 sizeof(fw_control_context));
3102 switch (status) {
3103 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3104 PM8001_MSG_DBG(pm8001_ha,
3105 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3106 break;
3107 case FLASH_UPDATE_IN_PROGRESS:
3108 PM8001_MSG_DBG(pm8001_ha,
3109 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3110 break;
3111 case FLASH_UPDATE_HDR_ERR:
3112 PM8001_MSG_DBG(pm8001_ha,
3113 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3114 break;
3115 case FLASH_UPDATE_OFFSET_ERR:
3116 PM8001_MSG_DBG(pm8001_ha,
3117 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3118 break;
3119 case FLASH_UPDATE_CRC_ERR:
3120 PM8001_MSG_DBG(pm8001_ha,
3121 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3122 break;
3123 case FLASH_UPDATE_LENGTH_ERR:
3124 PM8001_MSG_DBG(pm8001_ha,
3125 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3126 break;
3127 case FLASH_UPDATE_HW_ERR:
3128 PM8001_MSG_DBG(pm8001_ha,
3129 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3130 break;
3131 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3132 PM8001_MSG_DBG(pm8001_ha,
3133 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3134 break;
3135 case FLASH_UPDATE_DISABLED:
3136 PM8001_MSG_DBG(pm8001_ha,
3137 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3138 break;
3139 default:
3140 PM8001_MSG_DBG(pm8001_ha,
3141 pm8001_printk("No matched status = %d\n", status));
3142 break;
3143 }
3144 ccb->fw_control_context->fw_control->retcode = status;
3145 pci_free_consistent(pm8001_ha->pdev,
3146 fw_control_context.len,
3147 fw_control_context.virtAddr,
3148 fw_control_context.phys_addr);
3149 complete(pm8001_ha->nvmd_completion);
3150 ccb->task = NULL;
3151 ccb->ccb_tag = 0xFFFFFFFF;
3152 pm8001_ccb_free(pm8001_ha, tag);
3153 return 0;
3154}
3155
3156static int
3157mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3158{
3159 u32 status;
3160 int i;
3161 struct general_event_resp *pPayload =
3162 (struct general_event_resp *)(piomb + 4);
3163 status = le32_to_cpu(pPayload->status);
3164 PM8001_MSG_DBG(pm8001_ha,
3165 pm8001_printk(" status = 0x%x\n", status));
3166 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3167 PM8001_MSG_DBG(pm8001_ha,
3168 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
3169 pPayload->inb_IOMB_payload[i]));
3170 return 0;
3171}
3172
3173static int
3174mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3175{
3176 struct sas_task *t;
3177 struct pm8001_ccb_info *ccb;
3178 unsigned long flags;
3179 u32 status ;
3180 u32 tag, scp;
3181 struct task_status_struct *ts;
3182
3183 struct task_abort_resp *pPayload =
3184 (struct task_abort_resp *)(piomb + 4);
3185 ccb = &pm8001_ha->ccb_info[pPayload->tag];
3186 t = ccb->task;
3187 ts = &t->task_status;
3188
3189 if (t == NULL)
3190 return -1;
3191
3192 status = le32_to_cpu(pPayload->status);
3193 tag = le32_to_cpu(pPayload->tag);
3194 scp = le32_to_cpu(pPayload->scp);
3195 PM8001_IO_DBG(pm8001_ha,
3196 pm8001_printk(" status = 0x%x\n", status));
3197 if (status != 0)
3198 PM8001_FAIL_DBG(pm8001_ha,
3199 pm8001_printk("task abort failed tag = 0x%x,"
3200 " scp= 0x%x\n", tag, scp));
3201 switch (status) {
3202 case IO_SUCCESS:
3203 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3204 ts->resp = SAS_TASK_COMPLETE;
3205 ts->stat = SAM_GOOD;
3206 break;
3207 case IO_NOT_VALID:
3208 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3209 ts->resp = TMF_RESP_FUNC_FAILED;
3210 break;
3211 }
3212 spin_lock_irqsave(&t->task_state_lock, flags);
3213 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3214 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3215 t->task_state_flags |= SAS_TASK_STATE_DONE;
3216 spin_unlock_irqrestore(&t->task_state_lock, flags);
3217 pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3218 mb();
3219 t->task_done(t);
3220 return 0;
3221}
3222
3223/**
3224 * mpi_hw_event -The hw event has come.
3225 * @pm8001_ha: our hba card information
3226 * @piomb: IO message buffer
3227 */
3228static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3229{
3230 unsigned long flags;
3231 struct hw_event_resp *pPayload =
3232 (struct hw_event_resp *)(piomb + 4);
3233 u32 lr_evt_status_phyid_portid =
3234 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3235 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3236 u8 phy_id =
3237 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3238 u16 eventType =
3239 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3240 u8 status =
3241 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3242 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3243 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3244 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3245 PM8001_MSG_DBG(pm8001_ha,
3246 pm8001_printk("outbound queue HW event & event type : "));
3247 switch (eventType) {
3248 case HW_EVENT_PHY_START_STATUS:
3249 PM8001_MSG_DBG(pm8001_ha,
3250 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3251 " status = %x\n", status));
3252 if (status == 0) {
3253 phy->phy_state = 1;
3254 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3255 complete(phy->enable_completion);
3256 }
3257 break;
3258 case HW_EVENT_SAS_PHY_UP:
3259 PM8001_MSG_DBG(pm8001_ha,
3260 pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
3261 hw_event_sas_phy_up(pm8001_ha, piomb);
3262 break;
3263 case HW_EVENT_SATA_PHY_UP:
3264 PM8001_MSG_DBG(pm8001_ha,
3265 pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
3266 hw_event_sata_phy_up(pm8001_ha, piomb);
3267 break;
3268 case HW_EVENT_PHY_STOP_STATUS:
3269 PM8001_MSG_DBG(pm8001_ha,
3270 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3271 "status = %x\n", status));
3272 if (status == 0)
3273 phy->phy_state = 0;
3274 break;
3275 case HW_EVENT_SATA_SPINUP_HOLD:
3276 PM8001_MSG_DBG(pm8001_ha,
3277 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
3278 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3279 break;
3280 case HW_EVENT_PHY_DOWN:
3281 PM8001_MSG_DBG(pm8001_ha,
3282 pm8001_printk("HW_EVENT_PHY_DOWN \n"));
3283 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3284 phy->phy_attached = 0;
3285 phy->phy_state = 0;
3286 hw_event_phy_down(pm8001_ha, piomb);
3287 break;
3288 case HW_EVENT_PORT_INVALID:
3289 PM8001_MSG_DBG(pm8001_ha,
3290 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3291 sas_phy_disconnected(sas_phy);
3292 phy->phy_attached = 0;
3293 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3294 break;
3295 /* the broadcast change primitive received, tell the LIBSAS this event
3296 to revalidate the sas domain*/
3297 case HW_EVENT_BROADCAST_CHANGE:
3298 PM8001_MSG_DBG(pm8001_ha,
3299 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3300 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3301 port_id, phy_id, 1, 0);
3302 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3303 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3304 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3305 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3306 break;
3307 case HW_EVENT_PHY_ERROR:
3308 PM8001_MSG_DBG(pm8001_ha,
3309 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3310 sas_phy_disconnected(&phy->sas_phy);
3311 phy->phy_attached = 0;
3312 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3313 break;
3314 case HW_EVENT_BROADCAST_EXP:
3315 PM8001_MSG_DBG(pm8001_ha,
3316 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3317 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3318 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3319 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3320 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3321 break;
3322 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3323 PM8001_MSG_DBG(pm8001_ha,
3324 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3325 pm8001_hw_event_ack_req(pm8001_ha, 0,
3326 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3327 sas_phy_disconnected(sas_phy);
3328 phy->phy_attached = 0;
3329 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3330 break;
3331 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3332 PM8001_MSG_DBG(pm8001_ha,
3333 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3334 pm8001_hw_event_ack_req(pm8001_ha, 0,
3335 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3336 port_id, phy_id, 0, 0);
3337 sas_phy_disconnected(sas_phy);
3338 phy->phy_attached = 0;
3339 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3340 break;
3341 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3342 PM8001_MSG_DBG(pm8001_ha,
3343 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3344 pm8001_hw_event_ack_req(pm8001_ha, 0,
3345 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3346 port_id, phy_id, 0, 0);
3347 sas_phy_disconnected(sas_phy);
3348 phy->phy_attached = 0;
3349 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3350 break;
3351 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3352 PM8001_MSG_DBG(pm8001_ha,
3353 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3354 pm8001_hw_event_ack_req(pm8001_ha, 0,
3355 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3356 port_id, phy_id, 0, 0);
3357 sas_phy_disconnected(sas_phy);
3358 phy->phy_attached = 0;
3359 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3360 break;
3361 case HW_EVENT_MALFUNCTION:
3362 PM8001_MSG_DBG(pm8001_ha,
3363 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3364 break;
3365 case HW_EVENT_BROADCAST_SES:
3366 PM8001_MSG_DBG(pm8001_ha,
3367 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3368 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3369 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3370 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3371 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3372 break;
3373 case HW_EVENT_INBOUND_CRC_ERROR:
3374 PM8001_MSG_DBG(pm8001_ha,
3375 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3376 pm8001_hw_event_ack_req(pm8001_ha, 0,
3377 HW_EVENT_INBOUND_CRC_ERROR,
3378 port_id, phy_id, 0, 0);
3379 break;
3380 case HW_EVENT_HARD_RESET_RECEIVED:
3381 PM8001_MSG_DBG(pm8001_ha,
3382 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3383 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3384 break;
3385 case HW_EVENT_ID_FRAME_TIMEOUT:
3386 PM8001_MSG_DBG(pm8001_ha,
3387 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3388 sas_phy_disconnected(sas_phy);
3389 phy->phy_attached = 0;
3390 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3391 break;
3392 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3393 PM8001_MSG_DBG(pm8001_ha,
3394 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
3395 pm8001_hw_event_ack_req(pm8001_ha, 0,
3396 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3397 port_id, phy_id, 0, 0);
3398 sas_phy_disconnected(sas_phy);
3399 phy->phy_attached = 0;
3400 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3401 break;
3402 case HW_EVENT_PORT_RESET_TIMER_TMO:
3403 PM8001_MSG_DBG(pm8001_ha,
3404 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
3405 sas_phy_disconnected(sas_phy);
3406 phy->phy_attached = 0;
3407 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3408 break;
3409 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3410 PM8001_MSG_DBG(pm8001_ha,
3411 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
3412 sas_phy_disconnected(sas_phy);
3413 phy->phy_attached = 0;
3414 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3415 break;
3416 case HW_EVENT_PORT_RECOVER:
3417 PM8001_MSG_DBG(pm8001_ha,
3418 pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
3419 break;
3420 case HW_EVENT_PORT_RESET_COMPLETE:
3421 PM8001_MSG_DBG(pm8001_ha,
3422 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
3423 break;
3424 case EVENT_BROADCAST_ASYNCH_EVENT:
3425 PM8001_MSG_DBG(pm8001_ha,
3426 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3427 break;
3428 default:
3429 PM8001_MSG_DBG(pm8001_ha,
3430 pm8001_printk("Unknown event type = %x\n", eventType));
3431 break;
3432 }
3433 return 0;
3434}
3435
3436/**
3437 * process_one_iomb - process one outbound Queue memory block
3438 * @pm8001_ha: our hba card information
3439 * @piomb: IO message buffer
3440 */
3441static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3442{
3443 u32 pHeader = (u32)*(u32 *)piomb;
3444 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3445
3446 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:\n"));
3447
3448 switch (opc) {
3449 case OPC_OUB_ECHO:
3450 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
3451 break;
3452 case OPC_OUB_HW_EVENT:
3453 PM8001_MSG_DBG(pm8001_ha,
3454 pm8001_printk("OPC_OUB_HW_EVENT \n"));
3455 mpi_hw_event(pm8001_ha, piomb);
3456 break;
3457 case OPC_OUB_SSP_COMP:
3458 PM8001_MSG_DBG(pm8001_ha,
3459 pm8001_printk("OPC_OUB_SSP_COMP \n"));
3460 mpi_ssp_completion(pm8001_ha, piomb);
3461 break;
3462 case OPC_OUB_SMP_COMP:
3463 PM8001_MSG_DBG(pm8001_ha,
3464 pm8001_printk("OPC_OUB_SMP_COMP \n"));
3465 mpi_smp_completion(pm8001_ha, piomb);
3466 break;
3467 case OPC_OUB_LOCAL_PHY_CNTRL:
3468 PM8001_MSG_DBG(pm8001_ha,
3469 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3470 mpi_local_phy_ctl(pm8001_ha, piomb);
3471 break;
3472 case OPC_OUB_DEV_REGIST:
3473 PM8001_MSG_DBG(pm8001_ha,
3474 pm8001_printk("OPC_OUB_DEV_REGIST \n"));
3475 mpi_reg_resp(pm8001_ha, piomb);
3476 break;
3477 case OPC_OUB_DEREG_DEV:
3478 PM8001_MSG_DBG(pm8001_ha,
3479 pm8001_printk("unresgister the deviece \n"));
3480 mpi_dereg_resp(pm8001_ha, piomb);
3481 break;
3482 case OPC_OUB_GET_DEV_HANDLE:
3483 PM8001_MSG_DBG(pm8001_ha,
3484 pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
3485 break;
3486 case OPC_OUB_SATA_COMP:
3487 PM8001_MSG_DBG(pm8001_ha,
3488 pm8001_printk("OPC_OUB_SATA_COMP \n"));
3489 mpi_sata_completion(pm8001_ha, piomb);
3490 break;
3491 case OPC_OUB_SATA_EVENT:
3492 PM8001_MSG_DBG(pm8001_ha,
3493 pm8001_printk("OPC_OUB_SATA_EVENT \n"));
3494 mpi_sata_event(pm8001_ha, piomb);
3495 break;
3496 case OPC_OUB_SSP_EVENT:
3497 PM8001_MSG_DBG(pm8001_ha,
3498 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3499 mpi_ssp_event(pm8001_ha, piomb);
3500 break;
3501 case OPC_OUB_DEV_HANDLE_ARRIV:
3502 PM8001_MSG_DBG(pm8001_ha,
3503 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3504 /*This is for target*/
3505 break;
3506 case OPC_OUB_SSP_RECV_EVENT:
3507 PM8001_MSG_DBG(pm8001_ha,
3508 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3509 /*This is for target*/
3510 break;
3511 case OPC_OUB_DEV_INFO:
3512 PM8001_MSG_DBG(pm8001_ha,
3513 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3514 break;
3515 case OPC_OUB_FW_FLASH_UPDATE:
3516 PM8001_MSG_DBG(pm8001_ha,
3517 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3518 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3519 break;
3520 case OPC_OUB_GPIO_RESPONSE:
3521 PM8001_MSG_DBG(pm8001_ha,
3522 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3523 break;
3524 case OPC_OUB_GPIO_EVENT:
3525 PM8001_MSG_DBG(pm8001_ha,
3526 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3527 break;
3528 case OPC_OUB_GENERAL_EVENT:
3529 PM8001_MSG_DBG(pm8001_ha,
3530 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3531 mpi_general_event(pm8001_ha, piomb);
3532 break;
3533 case OPC_OUB_SSP_ABORT_RSP:
3534 PM8001_MSG_DBG(pm8001_ha,
3535 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3536 mpi_task_abort_resp(pm8001_ha, piomb);
3537 break;
3538 case OPC_OUB_SATA_ABORT_RSP:
3539 PM8001_MSG_DBG(pm8001_ha,
3540 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3541 mpi_task_abort_resp(pm8001_ha, piomb);
3542 break;
3543 case OPC_OUB_SAS_DIAG_MODE_START_END:
3544 PM8001_MSG_DBG(pm8001_ha,
3545 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3546 break;
3547 case OPC_OUB_SAS_DIAG_EXECUTE:
3548 PM8001_MSG_DBG(pm8001_ha,
3549 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3550 break;
3551 case OPC_OUB_GET_TIME_STAMP:
3552 PM8001_MSG_DBG(pm8001_ha,
3553 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3554 break;
3555 case OPC_OUB_SAS_HW_EVENT_ACK:
3556 PM8001_MSG_DBG(pm8001_ha,
3557 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3558 break;
3559 case OPC_OUB_PORT_CONTROL:
3560 PM8001_MSG_DBG(pm8001_ha,
3561 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3562 break;
3563 case OPC_OUB_SMP_ABORT_RSP:
3564 PM8001_MSG_DBG(pm8001_ha,
3565 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3566 mpi_task_abort_resp(pm8001_ha, piomb);
3567 break;
3568 case OPC_OUB_GET_NVMD_DATA:
3569 PM8001_MSG_DBG(pm8001_ha,
3570 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3571 mpi_get_nvmd_resp(pm8001_ha, piomb);
3572 break;
3573 case OPC_OUB_SET_NVMD_DATA:
3574 PM8001_MSG_DBG(pm8001_ha,
3575 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3576 mpi_set_nvmd_resp(pm8001_ha, piomb);
3577 break;
3578 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3579 PM8001_MSG_DBG(pm8001_ha,
3580 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3581 break;
3582 case OPC_OUB_SET_DEVICE_STATE:
3583 PM8001_MSG_DBG(pm8001_ha,
3584 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3585 mpi_set_dev_state_resp(pm8001_ha, piomb);
3586 break;
3587 case OPC_OUB_GET_DEVICE_STATE:
3588 PM8001_MSG_DBG(pm8001_ha,
3589 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3590 break;
3591 case OPC_OUB_SET_DEV_INFO:
3592 PM8001_MSG_DBG(pm8001_ha,
3593 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3594 break;
3595 case OPC_OUB_SAS_RE_INITIALIZE:
3596 PM8001_MSG_DBG(pm8001_ha,
3597 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3598 break;
3599 default:
3600 PM8001_MSG_DBG(pm8001_ha,
3601 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3602 opc));
3603 break;
3604 }
3605}
3606
3607static int process_oq(struct pm8001_hba_info *pm8001_ha)
3608{
3609 struct outbound_queue_table *circularQ;
3610 void *pMsg1 = NULL;
3611 u8 bc = 0;
3612 u32 ret = MPI_IO_STATUS_FAIL, processedMsgCount = 0;
3613
3614 circularQ = &pm8001_ha->outbnd_q_tbl[0];
3615 do {
3616 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3617 if (MPI_IO_STATUS_SUCCESS == ret) {
3618 /* process the outbound message */
3619 process_one_iomb(pm8001_ha, (void *)((u8 *)pMsg1 - 4));
3620 /* free the message from the outbound circular buffer */
3621 mpi_msg_free_set(pm8001_ha, circularQ, bc);
3622 processedMsgCount++;
3623 }
3624 if (MPI_IO_STATUS_BUSY == ret) {
3625 u32 producer_idx;
3626 /* Update the producer index from SPC */
3627 producer_idx = pm8001_read_32(circularQ->pi_virt);
3628 circularQ->producer_index = cpu_to_le32(producer_idx);
3629 if (circularQ->producer_index ==
3630 circularQ->consumer_idx)
3631 /* OQ is empty */
3632 break;
3633 }
3634 } while (100 > processedMsgCount);/*end message processing if hit the
3635 count*/
3636 return ret;
3637}
3638
3639/* PCI_DMA_... to our direction translation. */
3640static const u8 data_dir_flags[] = {
3641 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3642 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3643 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3644 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3645};
3646static void
3647pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3648{
3649 int i;
3650 struct scatterlist *sg;
3651 struct pm8001_prd *buf_prd = prd;
3652
3653 for_each_sg(scatter, sg, nr, i) {
3654 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3655 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3656 buf_prd->im_len.e = 0;
3657 buf_prd++;
3658 }
3659}
3660
3661static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3662{
3663 psmp_cmd->tag = cpu_to_le32(hTag);
3664 psmp_cmd->device_id = cpu_to_le32(deviceID);
3665 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3666}
3667
3668/**
3669 * pm8001_chip_smp_req - send a SMP task to FW
3670 * @pm8001_ha: our hba card information.
3671 * @ccb: the ccb information this request used.
3672 */
3673static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3674 struct pm8001_ccb_info *ccb)
3675{
3676 int elem, rc;
3677 struct sas_task *task = ccb->task;
3678 struct domain_device *dev = task->dev;
3679 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3680 struct scatterlist *sg_req, *sg_resp;
3681 u32 req_len, resp_len;
3682 struct smp_req smp_cmd;
3683 u32 opc;
3684 struct inbound_queue_table *circularQ;
3685
3686 memset(&smp_cmd, 0, sizeof(smp_cmd));
3687 /*
3688 * DMA-map SMP request, response buffers
3689 */
3690 sg_req = &task->smp_task.smp_req;
3691 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3692 if (!elem)
3693 return -ENOMEM;
3694 req_len = sg_dma_len(sg_req);
3695
3696 sg_resp = &task->smp_task.smp_resp;
3697 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3698 if (!elem) {
3699 rc = -ENOMEM;
3700 goto err_out;
3701 }
3702 resp_len = sg_dma_len(sg_resp);
3703 /* must be in dwords */
3704 if ((req_len & 0x3) || (resp_len & 0x3)) {
3705 rc = -EINVAL;
3706 goto err_out_2;
3707 }
3708
3709 opc = OPC_INB_SMP_REQUEST;
3710 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3711 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3712 smp_cmd.long_smp_req.long_req_addr =
3713 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3714 smp_cmd.long_smp_req.long_req_size =
3715 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3716 smp_cmd.long_smp_req.long_resp_addr =
3717 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3718 smp_cmd.long_smp_req.long_resp_size =
3719 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3720 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3721 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3722 return 0;
3723
3724err_out_2:
3725 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3726 PCI_DMA_FROMDEVICE);
3727err_out:
3728 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3729 PCI_DMA_TODEVICE);
3730 return rc;
3731}
3732
3733/**
3734 * pm8001_chip_ssp_io_req - send a SSP task to FW
3735 * @pm8001_ha: our hba card information.
3736 * @ccb: the ccb information this request used.
3737 */
3738static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3739 struct pm8001_ccb_info *ccb)
3740{
3741 struct sas_task *task = ccb->task;
3742 struct domain_device *dev = task->dev;
3743 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3744 struct ssp_ini_io_start_req ssp_cmd;
3745 u32 tag = ccb->ccb_tag;
3746 __le64 phys_addr;
3747 struct inbound_queue_table *circularQ;
3748 u32 opc = OPC_INB_SSPINIIOSTART;
3749 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3750 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3751 ssp_cmd.dir_m_tlr = data_dir_flags[task->data_dir] << 8 | 0x0;/*0 for
3752 SAS 1.1 compatible TLR*/
3753 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3754 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3755 ssp_cmd.tag = cpu_to_le32(tag);
3756 if (task->ssp_task.enable_first_burst)
3757 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3758 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3759 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3760 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3761 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3762
3763 /* fill in PRD (scatter/gather) table, if any */
3764 if (task->num_scatter > 1) {
3765 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3766 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3767 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3768 ssp_cmd.addr_low = lower_32_bits(phys_addr);
3769 ssp_cmd.addr_high = upper_32_bits(phys_addr);
3770 ssp_cmd.esgl = cpu_to_le32(1<<31);
3771 } else if (task->num_scatter == 1) {
3772 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3773 ssp_cmd.addr_low = lower_32_bits(dma_addr);
3774 ssp_cmd.addr_high = upper_32_bits(dma_addr);
3775 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3776 ssp_cmd.esgl = 0;
3777 } else if (task->num_scatter == 0) {
3778 ssp_cmd.addr_low = 0;
3779 ssp_cmd.addr_high = 0;
3780 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3781 ssp_cmd.esgl = 0;
3782 }
3783 mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
3784 return 0;
3785}
3786
3787static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3788 struct pm8001_ccb_info *ccb)
3789{
3790 struct sas_task *task = ccb->task;
3791 struct domain_device *dev = task->dev;
3792 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3793 u32 tag = ccb->ccb_tag;
3794 struct sata_start_req sata_cmd;
3795 u32 hdr_tag, ncg_tag = 0;
3796 __le64 phys_addr;
3797 u32 ATAP = 0x0;
3798 u32 dir;
3799 struct inbound_queue_table *circularQ;
3800 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3801 memset(&sata_cmd, 0, sizeof(sata_cmd));
3802 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3803 if (task->data_dir == PCI_DMA_NONE) {
3804 ATAP = 0x04; /* no data*/
3805 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
3806 } else if (likely(!task->ata_task.device_control_reg_update)) {
3807 if (task->ata_task.dma_xfer) {
3808 ATAP = 0x06; /* DMA */
3809 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
3810 } else {
3811 ATAP = 0x05; /* PIO*/
3812 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
3813 }
3814 if (task->ata_task.use_ncq &&
3815 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3816 ATAP = 0x07; /* FPDMA */
3817 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
3818 }
3819 }
3820 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3821 ncg_tag = cpu_to_le32(hdr_tag);
3822 dir = data_dir_flags[task->data_dir] << 8;
3823 sata_cmd.tag = cpu_to_le32(tag);
3824 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3825 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3826 sata_cmd.ncqtag_atap_dir_m =
3827 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
3828 sata_cmd.sata_fis = task->ata_task.fis;
3829 if (likely(!task->ata_task.device_control_reg_update))
3830 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3831 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3832 /* fill in PRD (scatter/gather) table, if any */
3833 if (task->num_scatter > 1) {
3834 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3835 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3836 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3837 sata_cmd.addr_low = lower_32_bits(phys_addr);
3838 sata_cmd.addr_high = upper_32_bits(phys_addr);
3839 sata_cmd.esgl = cpu_to_le32(1 << 31);
3840 } else if (task->num_scatter == 1) {
3841 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3842 sata_cmd.addr_low = lower_32_bits(dma_addr);
3843 sata_cmd.addr_high = upper_32_bits(dma_addr);
3844 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3845 sata_cmd.esgl = 0;
3846 } else if (task->num_scatter == 0) {
3847 sata_cmd.addr_low = 0;
3848 sata_cmd.addr_high = 0;
3849 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3850 sata_cmd.esgl = 0;
3851 }
3852 mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
3853 return 0;
3854}
3855
3856/**
3857 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
3858 * @pm8001_ha: our hba card information.
3859 * @num: the inbound queue number
3860 * @phy_id: the phy id which we wanted to start up.
3861 */
3862static int
3863pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3864{
3865 struct phy_start_req payload;
3866 struct inbound_queue_table *circularQ;
3867 u32 tag = 0x01;
3868 u32 opcode = OPC_INB_PHYSTART;
3869 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3870 memset(&payload, 0, sizeof(payload));
3871 payload.tag = cpu_to_le32(tag);
3872 /*
3873 ** [0:7] PHY Identifier
3874 ** [8:11] link rate 1.5G, 3G, 6G
3875 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
3876 ** [14] 0b disable spin up hold; 1b enable spin up hold
3877 */
3878 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3879 LINKMODE_AUTO | LINKRATE_15 |
3880 LINKRATE_30 | LINKRATE_60 | phy_id);
3881 payload.sas_identify.dev_type = SAS_END_DEV;
3882 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3883 memcpy(payload.sas_identify.sas_addr,
3884 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3885 payload.sas_identify.phy_id = phy_id;
3886 mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3887 return 0;
3888}
3889
3890/**
3891 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3892 * @pm8001_ha: our hba card information.
3893 * @num: the inbound queue number
3894 * @phy_id: the phy id which we wanted to start up.
3895 */
3896static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3897 u8 phy_id)
3898{
3899 struct phy_stop_req payload;
3900 struct inbound_queue_table *circularQ;
3901 u32 tag = 0x01;
3902 u32 opcode = OPC_INB_PHYSTOP;
3903 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3904 memset(&payload, 0, sizeof(payload));
3905 payload.tag = cpu_to_le32(tag);
3906 payload.phy_id = cpu_to_le32(phy_id);
3907 mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3908 return 0;
3909}
3910
3911/**
3912 * see comments on mpi_reg_resp.
3913 */
3914static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3915 struct pm8001_device *pm8001_dev, u32 flag)
3916{
3917 struct reg_dev_req payload;
3918 u32 opc;
3919 u32 stp_sspsmp_sata = 0x4;
3920 struct inbound_queue_table *circularQ;
3921 u32 linkrate, phy_id;
3922 u32 rc, tag = 0xdeadbeef;
3923 struct pm8001_ccb_info *ccb;
3924 u8 retryFlag = 0x1;
3925 u16 firstBurstSize = 0;
3926 u16 ITNT = 2000;
3927 struct domain_device *dev = pm8001_dev->sas_device;
3928 struct domain_device *parent_dev = dev->parent;
3929 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3930
3931 memset(&payload, 0, sizeof(payload));
3932 rc = pm8001_tag_alloc(pm8001_ha, &tag);
3933 if (rc)
3934 return rc;
3935 ccb = &pm8001_ha->ccb_info[tag];
3936 ccb->device = pm8001_dev;
3937 ccb->ccb_tag = tag;
3938 payload.tag = cpu_to_le32(tag);
3939 if (flag == 1)
3940 stp_sspsmp_sata = 0x02; /*direct attached sata */
3941 else {
3942 if (pm8001_dev->dev_type == SATA_DEV)
3943 stp_sspsmp_sata = 0x00; /* stp*/
3944 else if (pm8001_dev->dev_type == SAS_END_DEV ||
3945 pm8001_dev->dev_type == EDGE_DEV ||
3946 pm8001_dev->dev_type == FANOUT_DEV)
3947 stp_sspsmp_sata = 0x01; /*ssp or smp*/
3948 }
3949 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
3950 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
3951 else
3952 phy_id = pm8001_dev->attached_phy;
3953 opc = OPC_INB_REG_DEV;
3954 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
3955 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
3956 payload.phyid_portid =
3957 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
3958 ((phy_id & 0x0F) << 4));
3959 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
3960 ((linkrate & 0x0F) * 0x1000000) |
3961 ((stp_sspsmp_sata & 0x03) * 0x10000000));
3962 payload.firstburstsize_ITNexustimeout =
3963 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
3964 memcpy(&payload.sas_addr_hi, pm8001_dev->sas_device->sas_addr,
3965 SAS_ADDR_SIZE);
3966 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3967 return 0;
3968}
3969
3970/**
3971 * see comments on mpi_reg_resp.
3972 */
3973static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
3974 u32 device_id)
3975{
3976 struct dereg_dev_req payload;
3977 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
3978 struct inbound_queue_table *circularQ;
3979
3980 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3981 memset((u8 *)&payload, 0, sizeof(payload));
3982 payload.tag = 1;
3983 payload.device_id = cpu_to_le32(device_id);
3984 PM8001_MSG_DBG(pm8001_ha,
3985 pm8001_printk("unregister device device_id = %d\n", device_id));
3986 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3987 return 0;
3988}
3989
3990/**
3991 * pm8001_chip_phy_ctl_req - support the local phy operation
3992 * @pm8001_ha: our hba card information.
3993 * @num: the inbound queue number
3994 * @phy_id: the phy id which we wanted to operate
3995 * @phy_op:
3996 */
3997static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3998 u32 phyId, u32 phy_op)
3999{
4000 struct local_phy_ctl_req payload;
4001 struct inbound_queue_table *circularQ;
4002 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4003 memset((u8 *)&payload, 0, sizeof(payload));
4004 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4005 payload.tag = 1;
4006 payload.phyop_phyid =
4007 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4008 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4009 return 0;
4010}
4011
4012static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4013{
4014 u32 value;
4015#ifdef PM8001_USE_MSIX
4016 return 1;
4017#endif
4018 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4019 if (value)
4020 return 1;
4021 return 0;
4022
4023}
4024
4025/**
4026 * pm8001_chip_isr - PM8001 isr handler.
4027 * @pm8001_ha: our hba card information.
4028 * @irq: irq number.
4029 * @stat: stat.
4030 */
4031static void
4032pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4033{
4034 pm8001_chip_interrupt_disable(pm8001_ha);
4035 process_oq(pm8001_ha);
4036 pm8001_chip_interrupt_enable(pm8001_ha);
4037}
4038
4039static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4040 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4041{
4042 struct task_abort_req task_abort;
4043 struct inbound_queue_table *circularQ;
4044
4045 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4046 memset(&task_abort, 0, sizeof(task_abort));
4047 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4048 task_abort.abort_all = 0;
4049 task_abort.device_id = cpu_to_le32(dev_id);
4050 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4051 task_abort.tag = cpu_to_le32(cmd_tag);
4052 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4053 task_abort.abort_all = cpu_to_le32(1);
4054 task_abort.device_id = cpu_to_le32(dev_id);
4055 task_abort.tag = cpu_to_le32(cmd_tag);
4056 }
4057 mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4058 return 0;
4059}
4060
4061/**
4062 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4063 * @task: the task we wanted to aborted.
4064 * @flag: the abort flag.
4065 */
4066static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4067 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4068{
4069 u32 opc, device_id;
4070 int rc = TMF_RESP_FUNC_FAILED;
4071 PM8001_IO_DBG(pm8001_ha, pm8001_printk("Abort tag[%x]", task_tag));
4072 if (pm8001_dev->dev_type == SAS_END_DEV)
4073 opc = OPC_INB_SSP_ABORT;
4074 else if (pm8001_dev->dev_type == SATA_DEV)
4075 opc = OPC_INB_SATA_ABORT;
4076 else
4077 opc = OPC_INB_SMP_ABORT;/* SMP */
4078 device_id = pm8001_dev->device_id;
4079 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4080 task_tag, cmd_tag);
4081 if (rc != TMF_RESP_FUNC_COMPLETE)
4082 PM8001_IO_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4083 return rc;
4084}
4085
4086/**
4087 * pm8001_chip_ssp_tm_req - built the task managment command.
4088 * @pm8001_ha: our hba card information.
4089 * @ccb: the ccb information.
4090 * @tmf: task management function.
4091 */
4092static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4093 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4094{
4095 struct sas_task *task = ccb->task;
4096 struct domain_device *dev = task->dev;
4097 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4098 u32 opc = OPC_INB_SSPINITMSTART;
4099 struct inbound_queue_table *circularQ;
4100 struct ssp_ini_tm_start_req sspTMCmd;
4101
4102 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4103 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4104 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4105 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4106 sspTMCmd.ds_ads_m = cpu_to_le32(1 << 2);
4107 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4108 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4109 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4110 mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4111 return 0;
4112}
4113
4114static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4115 void *payload)
4116{
4117 u32 opc = OPC_INB_GET_NVMD_DATA;
4118 u32 nvmd_type;
4119 u32 rc;
4120 u32 tag;
4121 struct pm8001_ccb_info *ccb;
4122 struct inbound_queue_table *circularQ;
4123 struct get_nvm_data_req nvmd_req;
4124 struct fw_control_ex *fw_control_context;
4125 struct pm8001_ioctl_payload *ioctl_payload = payload;
4126
4127 nvmd_type = ioctl_payload->minor_function;
4128 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4129 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4130 fw_control_context->len = ioctl_payload->length;
4131 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4132 memset(&nvmd_req, 0, sizeof(nvmd_req));
4133 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4134 if (rc)
4135 return rc;
4136 ccb = &pm8001_ha->ccb_info[tag];
4137 ccb->ccb_tag = tag;
4138 ccb->fw_control_context = fw_control_context;
4139 nvmd_req.tag = cpu_to_le32(tag);
4140
4141 switch (nvmd_type) {
4142 case TWI_DEVICE: {
4143 u32 twi_addr, twi_page_size;
4144 twi_addr = 0xa8;
4145 twi_page_size = 2;
4146
4147 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4148 twi_page_size << 8 | TWI_DEVICE);
4149 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4150 nvmd_req.resp_addr_hi =
4151 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4152 nvmd_req.resp_addr_lo =
4153 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4154 break;
4155 }
4156 case C_SEEPROM: {
4157 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4158 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4159 nvmd_req.resp_addr_hi =
4160 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4161 nvmd_req.resp_addr_lo =
4162 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4163 break;
4164 }
4165 case VPD_FLASH: {
4166 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4167 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4168 nvmd_req.resp_addr_hi =
4169 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4170 nvmd_req.resp_addr_lo =
4171 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4172 break;
4173 }
4174 case EXPAN_ROM: {
4175 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4176 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4177 nvmd_req.resp_addr_hi =
4178 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4179 nvmd_req.resp_addr_lo =
4180 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4181 break;
4182 }
4183 default:
4184 break;
4185 }
4186 mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4187 return 0;
4188}
4189
4190static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4191 void *payload)
4192{
4193 u32 opc = OPC_INB_SET_NVMD_DATA;
4194 u32 nvmd_type;
4195 u32 rc;
4196 u32 tag;
4197 struct pm8001_ccb_info *ccb;
4198 struct inbound_queue_table *circularQ;
4199 struct set_nvm_data_req nvmd_req;
4200 struct fw_control_ex *fw_control_context;
4201 struct pm8001_ioctl_payload *ioctl_payload = payload;
4202
4203 nvmd_type = ioctl_payload->minor_function;
4204 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4205 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4206 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4207 ioctl_payload->func_specific,
4208 ioctl_payload->length);
4209 memset(&nvmd_req, 0, sizeof(nvmd_req));
4210 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4211 if (rc)
4212 return rc;
4213 ccb = &pm8001_ha->ccb_info[tag];
4214 ccb->fw_control_context = fw_control_context;
4215 ccb->ccb_tag = tag;
4216 nvmd_req.tag = cpu_to_le32(tag);
4217 switch (nvmd_type) {
4218 case TWI_DEVICE: {
4219 u32 twi_addr, twi_page_size;
4220 twi_addr = 0xa8;
4221 twi_page_size = 2;
4222 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4223 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4224 twi_page_size << 8 | TWI_DEVICE);
4225 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4226 nvmd_req.resp_addr_hi =
4227 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4228 nvmd_req.resp_addr_lo =
4229 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4230 break;
4231 }
4232 case C_SEEPROM:
4233 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4234 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4235 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4236 nvmd_req.resp_addr_hi =
4237 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4238 nvmd_req.resp_addr_lo =
4239 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4240 break;
4241 case VPD_FLASH:
4242 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4243 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4244 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4245 nvmd_req.resp_addr_hi =
4246 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4247 nvmd_req.resp_addr_lo =
4248 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4249 break;
4250 case EXPAN_ROM:
4251 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4252 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4253 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4254 nvmd_req.resp_addr_hi =
4255 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4256 nvmd_req.resp_addr_lo =
4257 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4258 break;
4259 default:
4260 break;
4261 }
4262 mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4263 return 0;
4264}
4265
4266/**
4267 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4268 * @pm8001_ha: our hba card information.
4269 * @fw_flash_updata_info: firmware flash update param
4270 */
4271static int
4272pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4273 void *fw_flash_updata_info, u32 tag)
4274{
4275 struct fw_flash_Update_req payload;
4276 struct fw_flash_updata_info *info;
4277 struct inbound_queue_table *circularQ;
4278 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4279
4280 memset((u8 *)&payload, 0, sizeof(struct fw_flash_Update_req));
4281 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4282 info = fw_flash_updata_info;
4283 payload.tag = cpu_to_le32(tag);
4284 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4285 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4286 payload.total_image_len = cpu_to_le32(info->total_image_len);
4287 payload.len = info->sgl.im_len.len ;
4288 payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4289 payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4290 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4291 return 0;
4292}
4293
4294static int
4295pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4296 void *payload)
4297{
4298 struct fw_flash_updata_info flash_update_info;
4299 struct fw_control_info *fw_control;
4300 struct fw_control_ex *fw_control_context;
4301 u32 rc;
4302 u32 tag;
4303 struct pm8001_ccb_info *ccb;
4304 void *buffer = NULL;
4305 dma_addr_t phys_addr;
4306 u32 phys_addr_hi;
4307 u32 phys_addr_lo;
4308 struct pm8001_ioctl_payload *ioctl_payload = payload;
4309
4310 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4311 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4312 if (fw_control->len != 0) {
4313 if (pm8001_mem_alloc(pm8001_ha->pdev,
4314 (void **)&buffer,
4315 &phys_addr,
4316 &phys_addr_hi,
4317 &phys_addr_lo,
4318 fw_control->len, 0) != 0) {
4319 PM8001_FAIL_DBG(pm8001_ha,
4320 pm8001_printk("Mem alloc failure\n"));
4321 return -ENOMEM;
4322 }
4323 }
4324 memset((void *)buffer, 0, fw_control->len);
4325 memcpy((void *)buffer, fw_control->buffer, fw_control->len);
4326 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4327 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4328 flash_update_info.sgl.im_len.e = 0;
4329 flash_update_info.cur_image_offset = fw_control->offset;
4330 flash_update_info.cur_image_len = fw_control->len;
4331 flash_update_info.total_image_len = fw_control->size;
4332 fw_control_context->fw_control = fw_control;
4333 fw_control_context->virtAddr = buffer;
4334 fw_control_context->len = fw_control->len;
4335 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4336 if (rc)
4337 return rc;
4338 ccb = &pm8001_ha->ccb_info[tag];
4339 ccb->fw_control_context = fw_control_context;
4340 ccb->ccb_tag = tag;
4341 pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, tag);
4342 return 0;
4343}
4344
4345static int
4346pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4347 struct pm8001_device *pm8001_dev, u32 state)
4348{
4349 struct set_dev_state_req payload;
4350 struct inbound_queue_table *circularQ;
4351 struct pm8001_ccb_info *ccb;
4352 u32 rc;
4353 u32 tag;
4354 u32 opc = OPC_INB_SET_DEVICE_STATE;
4355 memset((u8 *)&payload, 0, sizeof(payload));
4356 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4357 if (rc)
4358 return -1;
4359 ccb = &pm8001_ha->ccb_info[tag];
4360 ccb->ccb_tag = tag;
4361 ccb->device = pm8001_dev;
4362 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4363 payload.tag = cpu_to_le32(tag);
4364 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4365 payload.nds = cpu_to_le32(state);
4366 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4367 return 0;
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]4368}
4369
4370static int
4371pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4372{
4373 struct sas_re_initialization_req payload;
4374 struct inbound_queue_table *circularQ;
4375 struct pm8001_ccb_info *ccb;
4376 int rc;
4377 u32 tag;
4378 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4379 memset(&payload, 0, sizeof(payload));
4380 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4381 if (rc)
4382 return -1;
4383 ccb = &pm8001_ha->ccb_info[tag];
4384 ccb->ccb_tag = tag;
4385 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4386 payload.tag = cpu_to_le32(tag);
4387 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4388 payload.sata_hol_tmo = cpu_to_le32(80);
4389 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4390 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4391 return rc;
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]4392
4393}
4394
4395const struct pm8001_dispatch pm8001_8001_dispatch = {
4396 .name = "pmc8001",
4397 .chip_init = pm8001_chip_init,
4398 .chip_soft_rst = pm8001_chip_soft_rst,
4399 .chip_rst = pm8001_hw_chip_rst,
4400 .chip_iounmap = pm8001_chip_iounmap,
4401 .isr = pm8001_chip_isr,
4402 .is_our_interupt = pm8001_chip_is_our_interupt,
4403 .isr_process_oq = process_oq,
4404 .interrupt_enable = pm8001_chip_interrupt_enable,
4405 .interrupt_disable = pm8001_chip_interrupt_disable,
4406 .make_prd = pm8001_chip_make_sg,
4407 .smp_req = pm8001_chip_smp_req,
4408 .ssp_io_req = pm8001_chip_ssp_io_req,
4409 .sata_req = pm8001_chip_sata_req,
4410 .phy_start_req = pm8001_chip_phy_start_req,
4411 .phy_stop_req = pm8001_chip_phy_stop_req,
4412 .reg_dev_req = pm8001_chip_reg_dev_req,
4413 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4414 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4415 .task_abort = pm8001_chip_abort_task,
4416 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4417 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4418 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4419 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4420 .set_dev_state_req = pm8001_chip_set_dev_state_req,
jack_wangd0b68042009-11-05 22:32:31 +0800[diff] [blame^]4421 .sas_re_init_req = pm8001_chip_sas_re_initialization,
jack wangdbf9bfe2009-10-14 16:19:21 +0800[diff] [blame]4422};
4423