blob: 02e9fdeb8faf26891bdf43cb5846ae717fb720ea [file] [log] [blame]
Catalin Marinas8ad68bb2005-10-31 14:25:02 +00001/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000021#include <linux/init.h>
Russell King1be72282005-10-31 16:57:06 +000022#include <linux/platform_device.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000023#include <linux/dma-mapping.h>
24#include <linux/sysdev.h>
25#include <linux/interrupt.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000026#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h>
Russell Kingfced80c2008-09-06 12:10:45 +010028#include <linux/io.h>
Steve Glendinningc5142e82009-01-20 13:23:30 +000029#include <linux/smsc911x.h>
Catalin Marinas6be62ba2009-02-12 15:59:21 +010030#include <linux/ata_platform.h>
Linus Walleij6ef297f2009-09-22 14:29:36 +010031#include <linux/amba/mmci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/gfp.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000033
Russell Kingcf30fb42008-11-08 20:05:55 +000034#include <asm/clkdev.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000035#include <asm/system.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010036#include <mach/hardware.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000037#include <asm/irq.h>
38#include <asm/leds.h>
Colin Tuckley68c3d932008-11-10 14:10:11 +000039#include <asm/mach-types.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000040#include <asm/hardware/arm_timer.h>
Russell Kingc5a0adb2010-01-16 20:16:10 +000041#include <asm/hardware/icst.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000042
43#include <asm/mach/arch.h>
44#include <asm/mach/flash.h>
45#include <asm/mach/irq.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000046#include <asm/mach/map.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000047
48#include <asm/hardware/gic.h>
49
Russell Kingf4b8b312010-01-14 12:48:06 +000050#include <mach/clkdev.h>
Catalin Marinasee8c9572009-05-30 14:00:17 +010051#include <mach/platform.h>
52#include <mach/irqs.h>
Russell Kinge3887712010-01-14 13:30:16 +000053#include <plat/timer-sp.h>
Catalin Marinasee8c9572009-05-30 14:00:17 +010054
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000055#include "core.h"
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000056
Catalin Marinas1bbdf632008-12-01 14:54:58 +000057/* used by entry-macro.S and platsmp.c */
Catalin Marinasc4057f52008-02-04 17:41:01 +010058void __iomem *gic_cpu_base_addr;
59
Catalin Marinasc97c5aa2009-11-04 12:19:05 +000060#ifdef CONFIG_ZONE_DMA
61/*
62 * Adjust the zones if there are restrictions for DMA access.
63 */
64void __init realview_adjust_zones(int node, unsigned long *size,
65 unsigned long *hole)
66{
67 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
68
69 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
70 return;
71
72 size[ZONE_NORMAL] = size[0] - dma_size;
73 size[ZONE_DMA] = dma_size;
74 hole[ZONE_NORMAL] = hole[0];
75 hole[ZONE_DMA] = 0;
76}
77#endif
78
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000079
80#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
81
82static int realview_flash_init(void)
83{
84 u32 val;
85
86 val = __raw_readl(REALVIEW_FLASHCTRL);
87 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
88 __raw_writel(val, REALVIEW_FLASHCTRL);
89
90 return 0;
91}
92
93static void realview_flash_exit(void)
94{
95 u32 val;
96
97 val = __raw_readl(REALVIEW_FLASHCTRL);
98 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
99 __raw_writel(val, REALVIEW_FLASHCTRL);
100}
101
102static void realview_flash_set_vpp(int on)
103{
104 u32 val;
105
106 val = __raw_readl(REALVIEW_FLASHCTRL);
107 if (on)
108 val |= REALVIEW_FLASHPROG_FLVPPEN;
109 else
110 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
111 __raw_writel(val, REALVIEW_FLASHCTRL);
112}
113
114static struct flash_platform_data realview_flash_data = {
115 .map_name = "cfi_probe",
116 .width = 4,
117 .init = realview_flash_init,
118 .exit = realview_flash_exit,
119 .set_vpp = realview_flash_set_vpp,
120};
121
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000122struct platform_device realview_flash_device = {
123 .name = "armflash",
124 .id = 0,
125 .dev = {
126 .platform_data = &realview_flash_data,
127 },
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000128};
129
Catalin Marinasa44ddfd2008-04-18 22:43:10 +0100130int realview_flash_register(struct resource *res, u32 num)
131{
132 realview_flash_device.resource = res;
133 realview_flash_device.num_resources = num;
134 return platform_device_register(&realview_flash_device);
135}
136
Steve Glendinningc5142e82009-01-20 13:23:30 +0000137static struct smsc911x_platform_config smsc911x_config = {
138 .flags = SMSC911X_USE_32BIT,
139 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
140 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
141 .phy_interface = PHY_INTERFACE_MODE_MII,
Catalin Marinas0a5b2f62008-12-01 14:54:59 +0000142};
143
Catalin Marinas0a381332008-12-01 14:54:58 +0000144static struct platform_device realview_eth_device = {
Steve Glendinningc5142e82009-01-20 13:23:30 +0000145 .name = "smsc911x",
Catalin Marinas0a381332008-12-01 14:54:58 +0000146 .id = 0,
147 .num_resources = 2,
148};
149
150int realview_eth_register(const char *name, struct resource *res)
151{
152 if (name)
153 realview_eth_device.name = name;
154 realview_eth_device.resource = res;
Steve Glendinningc5142e82009-01-20 13:23:30 +0000155 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
156 realview_eth_device.dev.platform_data = &smsc911x_config;
Catalin Marinas0a381332008-12-01 14:54:58 +0000157
158 return platform_device_register(&realview_eth_device);
159}
160
Catalin Marinas7db21712009-02-12 16:00:21 +0100161struct platform_device realview_usb_device = {
162 .name = "isp1760",
163 .num_resources = 2,
164};
165
166int realview_usb_register(struct resource *res)
167{
168 realview_usb_device.resource = res;
169 return platform_device_register(&realview_usb_device);
170}
171
Catalin Marinas6be62ba2009-02-12 15:59:21 +0100172static struct pata_platform_info pata_platform_data = {
173 .ioport_shift = 1,
174};
175
176static struct resource pata_resources[] = {
177 [0] = {
178 .start = REALVIEW_CF_BASE,
179 .end = REALVIEW_CF_BASE + 0xff,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .start = REALVIEW_CF_BASE + 0x100,
184 .end = REALVIEW_CF_BASE + SZ_4K - 1,
185 .flags = IORESOURCE_MEM,
186 },
187};
188
189struct platform_device realview_cf_device = {
190 .name = "pata_platform",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(pata_resources),
193 .resource = pata_resources,
194 .dev = {
195 .platform_data = &pata_platform_data,
196 },
197};
198
Russell King6b65cd72006-12-10 21:21:32 +0100199static struct resource realview_i2c_resource = {
200 .start = REALVIEW_I2C_BASE,
201 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
202 .flags = IORESOURCE_MEM,
203};
204
205struct platform_device realview_i2c_device = {
206 .name = "versatile-i2c",
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100207 .id = 0,
Russell King6b65cd72006-12-10 21:21:32 +0100208 .num_resources = 1,
209 .resource = &realview_i2c_resource,
210};
211
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100212static struct i2c_board_info realview_i2c_board_info[] = {
213 {
Russell King64e8be62009-07-18 15:51:55 +0100214 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100215 },
216};
217
218static int __init realview_i2c_init(void)
219{
220 return i2c_register_board_info(0, realview_i2c_board_info,
221 ARRAY_SIZE(realview_i2c_board_info));
222}
223arch_initcall(realview_i2c_init);
224
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000225#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
226
Russell King98b09792009-07-09 15:17:41 +0100227/*
228 * This is only used if GPIOLIB support is disabled
229 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000230static unsigned int realview_mmc_status(struct device *dev)
231{
232 struct amba_device *adev = container_of(dev, struct amba_device, dev);
233 u32 mask;
234
235 if (adev->res.start == REALVIEW_MMCI0_BASE)
236 mask = 1;
237 else
238 mask = 2;
239
Russell King74bc8092010-07-29 15:58:59 +0100240 return readl(REALVIEW_SYSMCI) & mask;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000241}
242
Linus Walleij6ef297f2009-09-22 14:29:36 +0100243struct mmci_platform_data realview_mmc0_plat_data = {
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000244 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
245 .status = realview_mmc_status,
Russell King98b09792009-07-09 15:17:41 +0100246 .gpio_wp = 17,
247 .gpio_cd = 16,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000248};
249
Linus Walleij6ef297f2009-09-22 14:29:36 +0100250struct mmci_platform_data realview_mmc1_plat_data = {
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000251 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
252 .status = realview_mmc_status,
Russell King98b09792009-07-09 15:17:41 +0100253 .gpio_wp = 19,
254 .gpio_cd = 18,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000255};
256
257/*
258 * Clock handling
259 */
Russell King39c0cb02010-01-16 16:27:28 +0000260static const struct icst_params realview_oscvco_params = {
Russell King64fceb12010-01-16 17:28:44 +0000261 .ref = 24000000,
Russell King4de2edb2010-01-16 18:08:47 +0000262 .vco_max = ICST307_VCO_MAX,
Russell Kinge73a46a2010-01-16 19:49:39 +0000263 .vco_min = ICST307_VCO_MIN,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000264 .vd_min = 4 + 8,
265 .vd_max = 511 + 8,
266 .rd_min = 1 + 2,
267 .rd_max = 127 + 2,
Russell King232eaf72010-01-16 19:46:19 +0000268 .s2div = icst307_s2div,
269 .idx2s = icst307_idx2s,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000270};
271
Russell King39c0cb02010-01-16 16:27:28 +0000272static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000273{
274 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000275 u32 val;
276
Russell Kingd1914c72010-01-14 20:09:34 +0000277 val = readl(clk->vcoreg) & ~0x7ffff;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000278 val |= vco.v | (vco.r << 9) | (vco.s << 16);
279
280 writel(0xa05f, sys_lock);
Russell Kingd1914c72010-01-14 20:09:34 +0000281 writel(val, clk->vcoreg);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000282 writel(0, sys_lock);
283}
284
Russell King9bf5b2e2010-03-01 16:18:39 +0000285static const struct clk_ops oscvco_clk_ops = {
286 .round = icst_clk_round,
287 .set = icst_clk_set,
288 .setvco = realview_oscvco_set,
289};
290
Russell Kingcf30fb42008-11-08 20:05:55 +0000291static struct clk oscvco_clk = {
Russell King9bf5b2e2010-03-01 16:18:39 +0000292 .ops = &oscvco_clk_ops,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000293 .params = &realview_oscvco_params,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000294};
295
296/*
Russell Kingcf30fb42008-11-08 20:05:55 +0000297 * These are fixed clocks.
298 */
299static struct clk ref24_clk = {
300 .rate = 24000000,
301};
302
303static struct clk_lookup lookups[] = {
304 { /* UART0 */
Linus Walleij43215322009-09-21 12:30:32 +0100305 .dev_id = "dev:uart0",
Russell Kingcf30fb42008-11-08 20:05:55 +0000306 .clk = &ref24_clk,
307 }, { /* UART1 */
Linus Walleij43215322009-09-21 12:30:32 +0100308 .dev_id = "dev:uart1",
Russell Kingcf30fb42008-11-08 20:05:55 +0000309 .clk = &ref24_clk,
310 }, { /* UART2 */
Linus Walleij43215322009-09-21 12:30:32 +0100311 .dev_id = "dev:uart2",
Russell Kingcf30fb42008-11-08 20:05:55 +0000312 .clk = &ref24_clk,
313 }, { /* UART3 */
Linus Walleij43215322009-09-21 12:30:32 +0100314 .dev_id = "fpga:uart3",
Russell Kingcf30fb42008-11-08 20:05:55 +0000315 .clk = &ref24_clk,
316 }, { /* KMI0 */
Linus Walleij43215322009-09-21 12:30:32 +0100317 .dev_id = "fpga:kmi0",
Russell Kingcf30fb42008-11-08 20:05:55 +0000318 .clk = &ref24_clk,
319 }, { /* KMI1 */
Linus Walleij43215322009-09-21 12:30:32 +0100320 .dev_id = "fpga:kmi1",
Russell Kingcf30fb42008-11-08 20:05:55 +0000321 .clk = &ref24_clk,
322 }, { /* MMC0 */
Linus Walleij43215322009-09-21 12:30:32 +0100323 .dev_id = "fpga:mmc0",
Russell Kingcf30fb42008-11-08 20:05:55 +0000324 .clk = &ref24_clk,
325 }, { /* EB:CLCD */
Linus Walleij43215322009-09-21 12:30:32 +0100326 .dev_id = "dev:clcd",
Russell Kingcf30fb42008-11-08 20:05:55 +0000327 .clk = &oscvco_clk,
328 }, { /* PB:CLCD */
Linus Walleij43215322009-09-21 12:30:32 +0100329 .dev_id = "issp:clcd",
Russell Kingcf30fb42008-11-08 20:05:55 +0000330 .clk = &oscvco_clk,
331 }
332};
333
334static int __init clk_init(void)
335{
Russell Kingd1914c72010-01-14 20:09:34 +0000336 if (machine_is_realview_pb1176())
337 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
338 else
339 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
340
Russell King0a0300d2010-01-12 12:28:00 +0000341 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
Russell Kingd1914c72010-01-14 20:09:34 +0000342
Russell Kingcf30fb42008-11-08 20:05:55 +0000343 return 0;
344}
345arch_initcall(clk_init);
346
347/*
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000348 * CLCD support.
349 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000350#define SYS_CLCD_NLCDIOON (1 << 2)
351#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
352#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
353#define SYS_CLCD_ID_MASK (0x1f << 8)
354#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
355#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
356#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
357#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
358#define SYS_CLCD_ID_VGA (0x1f << 8)
359
360static struct clcd_panel vga = {
361 .mode = {
362 .name = "VGA",
363 .refresh = 60,
364 .xres = 640,
365 .yres = 480,
366 .pixclock = 39721,
367 .left_margin = 40,
368 .right_margin = 24,
369 .upper_margin = 32,
370 .lower_margin = 11,
371 .hsync_len = 96,
372 .vsync_len = 2,
373 .sync = 0,
374 .vmode = FB_VMODE_NONINTERLACED,
375 },
376 .width = -1,
377 .height = -1,
378 .tim2 = TIM2_BCD | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000379 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000380 .bpp = 16,
381};
382
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000383static struct clcd_panel xvga = {
384 .mode = {
385 .name = "XVGA",
386 .refresh = 60,
387 .xres = 1024,
388 .yres = 768,
389 .pixclock = 15748,
390 .left_margin = 152,
391 .right_margin = 48,
392 .upper_margin = 23,
393 .lower_margin = 3,
394 .hsync_len = 104,
395 .vsync_len = 4,
396 .sync = 0,
397 .vmode = FB_VMODE_NONINTERLACED,
398 },
399 .width = -1,
400 .height = -1,
401 .tim2 = TIM2_BCD | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000402 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000403 .bpp = 16,
404};
405
406static struct clcd_panel sanyo_3_8_in = {
407 .mode = {
408 .name = "Sanyo QVGA",
409 .refresh = 116,
410 .xres = 320,
411 .yres = 240,
412 .pixclock = 100000,
413 .left_margin = 6,
414 .right_margin = 6,
415 .upper_margin = 5,
416 .lower_margin = 5,
417 .hsync_len = 6,
418 .vsync_len = 6,
419 .sync = 0,
420 .vmode = FB_VMODE_NONINTERLACED,
421 },
422 .width = -1,
423 .height = -1,
424 .tim2 = TIM2_BCD,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000425 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000426 .bpp = 16,
427};
428
429static struct clcd_panel sanyo_2_5_in = {
430 .mode = {
431 .name = "Sanyo QVGA Portrait",
432 .refresh = 116,
433 .xres = 240,
434 .yres = 320,
435 .pixclock = 100000,
436 .left_margin = 20,
437 .right_margin = 10,
438 .upper_margin = 2,
439 .lower_margin = 2,
440 .hsync_len = 10,
441 .vsync_len = 2,
442 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
443 .vmode = FB_VMODE_NONINTERLACED,
444 },
445 .width = -1,
446 .height = -1,
447 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000448 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000449 .bpp = 16,
450};
451
452static struct clcd_panel epson_2_2_in = {
453 .mode = {
454 .name = "Epson QCIF",
455 .refresh = 390,
456 .xres = 176,
457 .yres = 220,
458 .pixclock = 62500,
459 .left_margin = 3,
460 .right_margin = 2,
461 .upper_margin = 1,
462 .lower_margin = 0,
463 .hsync_len = 3,
464 .vsync_len = 2,
465 .sync = 0,
466 .vmode = FB_VMODE_NONINTERLACED,
467 },
468 .width = -1,
469 .height = -1,
470 .tim2 = TIM2_BCD | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000471 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000472 .bpp = 16,
473};
474
475/*
476 * Detect which LCD panel is connected, and return the appropriate
477 * clcd_panel structure. Note: we do not have any information on
478 * the required timings for the 8.4in panel, so we presently assume
479 * VGA timings.
480 */
481static struct clcd_panel *realview_clcd_panel(void)
482{
483 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000484 struct clcd_panel *vga_panel;
485 struct clcd_panel *panel;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000486 u32 val;
487
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000488 if (machine_is_realview_eb())
489 vga_panel = &vga;
490 else
491 vga_panel = &xvga;
492
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000493 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
494 if (val == SYS_CLCD_ID_SANYO_3_8)
495 panel = &sanyo_3_8_in;
496 else if (val == SYS_CLCD_ID_SANYO_2_5)
497 panel = &sanyo_2_5_in;
498 else if (val == SYS_CLCD_ID_EPSON_2_2)
499 panel = &epson_2_2_in;
500 else if (val == SYS_CLCD_ID_VGA)
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000501 panel = vga_panel;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000502 else {
503 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
504 val);
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000505 panel = vga_panel;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000506 }
507
508 return panel;
509}
510
511/*
512 * Disable all display connectors on the interface module.
513 */
514static void realview_clcd_disable(struct clcd_fb *fb)
515{
516 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
517 u32 val;
518
519 val = readl(sys_clcd);
520 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
521 writel(val, sys_clcd);
522}
523
524/*
525 * Enable the relevant connector on the interface module.
526 */
527static void realview_clcd_enable(struct clcd_fb *fb)
528{
529 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
530 u32 val;
531
Catalin Marinas9e7714d2006-03-16 14:10:20 +0000532 /*
533 * Enable the PSUs
534 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000535 val = readl(sys_clcd);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000536 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
537 writel(val, sys_clcd);
538}
539
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000540static int realview_clcd_setup(struct clcd_fb *fb)
541{
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000542 unsigned long framesize;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000543 dma_addr_t dma;
544
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000545 if (machine_is_realview_eb())
546 /* VGA, 16bpp */
547 framesize = 640 * 480 * 2;
548 else
549 /* XVGA, 16bpp */
550 framesize = 1024 * 768 * 2;
551
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000552 fb->panel = realview_clcd_panel();
553
554 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
Catalin Marinasc97c5aa2009-11-04 12:19:05 +0000555 &dma, GFP_KERNEL | GFP_DMA);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000556 if (!fb->fb.screen_base) {
557 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
558 return -ENOMEM;
559 }
560
561 fb->fb.fix.smem_start = dma;
562 fb->fb.fix.smem_len = framesize;
563
564 return 0;
565}
566
567static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
568{
569 return dma_mmap_writecombine(&fb->dev->dev, vma,
570 fb->fb.screen_base,
571 fb->fb.fix.smem_start,
572 fb->fb.fix.smem_len);
573}
574
575static void realview_clcd_remove(struct clcd_fb *fb)
576{
577 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
578 fb->fb.screen_base, fb->fb.fix.smem_start);
579}
580
581struct clcd_board clcd_plat_data = {
582 .name = "RealView",
583 .check = clcdfb_check,
584 .decode = clcdfb_decode,
585 .disable = realview_clcd_disable,
586 .enable = realview_clcd_enable,
587 .setup = realview_clcd_setup,
588 .mmap = realview_clcd_mmap,
589 .remove = realview_clcd_remove,
590};
591
592#ifdef CONFIG_LEDS
593#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
594
595void realview_leds_event(led_event_t ledevt)
596{
597 unsigned long flags;
598 u32 val;
Catalin Marinasda055eb2009-05-30 13:56:16 +0100599 u32 led = 1 << smp_processor_id();
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000600
601 local_irq_save(flags);
602 val = readl(VA_LEDS_BASE);
603
604 switch (ledevt) {
605 case led_idle_start:
Catalin Marinasda055eb2009-05-30 13:56:16 +0100606 val = val & ~led;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000607 break;
608
609 case led_idle_end:
Catalin Marinasda055eb2009-05-30 13:56:16 +0100610 val = val | led;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000611 break;
612
613 case led_timer:
Catalin Marinasda055eb2009-05-30 13:56:16 +0100614 val = val ^ REALVIEW_SYS_LED7;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000615 break;
616
617 case led_halted:
618 val = 0;
619 break;
620
621 default:
622 break;
623 }
624
625 writel(val, VA_LEDS_BASE);
626 local_irq_restore(flags);
627}
628#endif /* CONFIG_LEDS */
629
630/*
631 * Where is the timer (VA)?
632 */
Catalin Marinas80192732008-04-18 22:43:11 +0100633void __iomem *timer0_va_base;
634void __iomem *timer1_va_base;
635void __iomem *timer2_va_base;
636void __iomem *timer3_va_base;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000637
638/*
Catalin Marinasa8655e82008-02-04 17:30:57 +0100639 * Set up the clock source and clock events devices
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000640 */
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100641void __init realview_timer_init(unsigned int timer_irq)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000642{
643 u32 val;
644
645 /*
646 * set clock frequency:
647 * REALVIEW_REFCLK is 32KHz
648 * REALVIEW_TIMCLK is 1MHz
649 */
650 val = readl(__io_address(REALVIEW_SCTL_BASE));
651 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
652 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
653 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
654 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
655 __io_address(REALVIEW_SCTL_BASE));
656
657 /*
658 * Initialise to a known state (all timers off)
659 */
Catalin Marinas80192732008-04-18 22:43:11 +0100660 writel(0, timer0_va_base + TIMER_CTRL);
661 writel(0, timer1_va_base + TIMER_CTRL);
662 writel(0, timer2_va_base + TIMER_CTRL);
663 writel(0, timer3_va_base + TIMER_CTRL);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000664
Russell Kinge3887712010-01-14 13:30:16 +0000665 sp804_clocksource_init(timer3_va_base);
666 sp804_clockevents_init(timer0_va_base, timer_irq);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000667}
Catalin Marinas5b39d152009-11-04 12:19:04 +0000668
669/*
670 * Setup the memory banks.
671 */
672void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
673 struct meminfo *meminfo)
674{
675 /*
676 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
677 * Half of this is mirrored at 0.
678 */
679#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
680 meminfo->bank[0].start = 0x70000000;
681 meminfo->bank[0].size = SZ_512M;
682 meminfo->nr_banks = 1;
683#else
684 meminfo->bank[0].start = 0;
685 meminfo->bank[0].size = SZ_256M;
686 meminfo->nr_banks = 1;
687#endif
688}