blob: 3c596c9f0305eda0aa87c5ea4b0d6c7a16416610 [file] [log] [blame]
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
Ville Syrjälä17316932013-04-24 18:52:38 +030035#include <drm/drm_rect.h>
Chandra Konduruc3318792015-04-15 15:15:02 -070036#include <drm/drm_atomic.h>
Matt Roperea2c67b2014-12-23 10:41:52 -080037#include <drm/drm_plane_helper.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080038#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010039#include <drm/i915_drm.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080040#include "i915_drv.h"
41
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +030042static bool
43format_is_yuv(uint32_t format)
44{
45 switch (format) {
46 case DRM_FORMAT_YUYV:
47 case DRM_FORMAT_UYVY:
48 case DRM_FORMAT_VYUY:
49 case DRM_FORMAT_YVYU:
50 return true;
51 default:
52 return false;
53 }
54}
55
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030056static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
57 int usecs)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030058{
59 /* paranoia */
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030060 if (!adjusted_mode->crtc_htotal)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030061 return 1;
62
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030063 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
64 1000 * adjusted_mode->crtc_htotal);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030065}
66
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020067/**
68 * intel_pipe_update_start() - start update of a set of display registers
69 * @crtc: the crtc of which the registers are going to be updated
70 * @start_vbl_count: vblank counter return pointer used for error checking
71 *
72 * Mark the start of an update to pipe registers that should be updated
73 * atomically regarding vblank. If the next vblank will happens within
74 * the next 100 us, this function waits until the vblank passes.
75 *
76 * After a successful call to this function, interrupts will be disabled
77 * until a subsequent call to intel_pipe_update_end(). That is done to
78 * avoid random delays. The value written to @start_vbl_count should be
79 * supplied to intel_pipe_update_end() for error checking.
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020080 */
Maarten Lankhorst34e0adb2015-08-31 13:04:25 +020081void intel_pipe_update_start(struct intel_crtc *crtc)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030082{
83 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä124abe02015-09-08 13:40:45 +030084 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030085 enum pipe pipe = crtc->pipe;
86 long timeout = msecs_to_jiffies_timeout(1);
87 int scanline, min, max, vblank_start;
Ville Syrjälä210871b2014-05-22 19:00:50 +030088 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030089 DEFINE_WAIT(wait);
90
Ville Syrjälä124abe02015-09-08 13:40:45 +030091 vblank_start = adjusted_mode->crtc_vblank_start;
92 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030093 vblank_start = DIV_ROUND_UP(vblank_start, 2);
94
95 /* FIXME needs to be calibrated sensibly */
Ville Syrjälä124abe02015-09-08 13:40:45 +030096 min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030097 max = vblank_start - 1;
98
Maarten Lankhorst8f539a82015-07-13 16:30:32 +020099 local_irq_disable();
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200100
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300101 if (min <= 0 || max <= 0)
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200102 return;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300103
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100104 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200105 return;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300106
Jesse Barnesd637ce32015-09-17 08:08:32 -0700107 crtc->debug.min_vbl = min;
108 crtc->debug.max_vbl = max;
109 trace_i915_pipe_update_start(crtc);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300110
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300111 for (;;) {
112 /*
113 * prepare_to_wait() has a memory barrier, which guarantees
114 * other CPUs can see the task state update by the time we
115 * read the scanline.
116 */
Ville Syrjälä210871b2014-05-22 19:00:50 +0300117 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300118
119 scanline = intel_get_crtc_scanline(crtc);
120 if (scanline < min || scanline > max)
121 break;
122
123 if (timeout <= 0) {
124 DRM_ERROR("Potential atomic update failure on pipe %c\n",
125 pipe_name(crtc->pipe));
126 break;
127 }
128
129 local_irq_enable();
130
131 timeout = schedule_timeout(timeout);
132
133 local_irq_disable();
134 }
135
Ville Syrjälä210871b2014-05-22 19:00:50 +0300136 finish_wait(wq, &wait);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300137
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100138 drm_crtc_vblank_put(&crtc->base);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300139
Jesse Barneseb120ef2015-09-15 14:19:32 -0700140 crtc->debug.scanline_start = scanline;
141 crtc->debug.start_vbl_time = ktime_get();
142 crtc->debug.start_vbl_count =
143 dev->driver->get_vblank_counter(dev, pipe);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300144
Jesse Barnesd637ce32015-09-17 08:08:32 -0700145 trace_i915_pipe_update_vblank_evaded(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300146}
147
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200148/**
149 * intel_pipe_update_end() - end update of a set of display registers
150 * @crtc: the crtc of which the registers were updated
151 * @start_vbl_count: start vblank counter (used for error checking)
152 *
153 * Mark the end of an update started with intel_pipe_update_start(). This
154 * re-enables interrupts and verifies the update was actually completed
155 * before a vblank using the value of @start_vbl_count.
156 */
Maarten Lankhorst34e0adb2015-08-31 13:04:25 +0200157void intel_pipe_update_end(struct intel_crtc *crtc)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300158{
159 struct drm_device *dev = crtc->base.dev;
160 enum pipe pipe = crtc->pipe;
Jesse Barneseb120ef2015-09-15 14:19:32 -0700161 int scanline_end = intel_get_crtc_scanline(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300162 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
Maarten Lankhorst85a62bf2015-09-01 12:15:33 +0200163 ktime_t end_vbl_time = ktime_get();
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300164
Jesse Barnesd637ce32015-09-17 08:08:32 -0700165 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300166
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300167 local_irq_enable();
168
Jesse Barneseb120ef2015-09-15 14:19:32 -0700169 if (crtc->debug.start_vbl_count &&
170 crtc->debug.start_vbl_count != end_vbl_count) {
171 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
172 pipe_name(pipe), crtc->debug.start_vbl_count,
173 end_vbl_count,
174 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
175 crtc->debug.min_vbl, crtc->debug.max_vbl,
176 crtc->debug.scanline_start, scanline_end);
177 }
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300178}
179
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800180static void
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100181skl_update_plane(struct drm_plane *drm_plane,
182 const struct intel_crtc_state *crtc_state,
183 const struct intel_plane_state *plane_state)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000184{
185 struct drm_device *dev = drm_plane->dev;
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100188 struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjäläbdd75542015-03-19 17:57:11 +0200189 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000190 const int pipe = intel_plane->pipe;
191 const int plane = intel_plane->plane + 1;
Sonika Jindal3b7a5112015-04-10 14:37:29 +0530192 u32 plane_ctl, stride_div, stride;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100193 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Mika Kuoppala44eb0cb2015-10-30 13:26:15 +0200194 u32 surf_addr;
Sonika Jindal3b7a5112015-04-10 14:37:29 +0530195 u32 tile_height, plane_offset, plane_size;
196 unsigned int rotation;
197 int x_offset, y_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100198 int crtc_x = plane_state->dst.x1;
199 int crtc_y = plane_state->dst.y1;
200 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
201 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
202 uint32_t x = plane_state->src.x1 >> 16;
203 uint32_t y = plane_state->src.y1 >> 16;
204 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
205 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
206 const struct intel_scaler *scaler =
207 &crtc_state->scaler_state.scalers[plane_state->scaler_id];
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000208
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200209 plane_ctl = PLANE_CTL_ENABLE |
Bob Paauwee12c8ce2015-08-27 13:46:30 -0700210 PLANE_CTL_PIPE_GAMMA_ENABLE |
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200211 PLANE_CTL_PIPE_CSC_ENABLE;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000212
Chandra Konduruc3318792015-04-15 15:15:02 -0700213 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
214 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
Damien Lespiaub3218032015-02-27 11:15:18 +0000215
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100216 rotation = plane_state->base.rotation;
Chandra Konduruc3318792015-04-15 15:15:02 -0700217 plane_ctl |= skl_plane_ctl_rotation(rotation);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000218
Damien Lespiaub3218032015-02-27 11:15:18 +0000219 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
220 fb->pixel_format);
221
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000222 /* Sizes are 0 based */
223 src_w--;
224 src_h--;
225 crtc_w--;
226 crtc_h--;
227
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200228 if (key->flags) {
229 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
230 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
231 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
232 }
233
234 if (key->flags & I915_SET_COLORKEY_DESTINATION)
235 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
236 else if (key->flags & I915_SET_COLORKEY_SOURCE)
237 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
238
Tvrtko Ursulindedf2782015-09-21 10:45:35 +0100239 surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +0000240
Sonika Jindal3b7a5112015-04-10 14:37:29 +0530241 if (intel_rotation_90_or_270(rotation)) {
242 /* stride: Surface height in tiles */
Chandra Konduru2614f172015-05-08 20:22:46 -0700243 tile_height = intel_tile_height(dev, fb->pixel_format,
Tvrtko Ursulinfe47ea02015-09-21 10:45:32 +0100244 fb->modifier[0], 0);
Sonika Jindal3b7a5112015-04-10 14:37:29 +0530245 stride = DIV_ROUND_UP(fb->height, tile_height);
246 plane_size = (src_w << 16) | src_h;
247 x_offset = stride * tile_height - y - (src_h + 1);
248 y_offset = x;
249 } else {
250 stride = fb->pitches[0] / stride_div;
251 plane_size = (src_h << 16) | src_w;
252 x_offset = x;
253 y_offset = y;
254 }
255 plane_offset = y_offset << 16 | x_offset;
256
257 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
258 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
Sonika Jindal3b7a5112015-04-10 14:37:29 +0530259 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
Chandra Konduruc3318792015-04-15 15:15:02 -0700260
261 /* program plane scaler */
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100262 if (plane_state->scaler_id >= 0) {
Chandra Konduruc3318792015-04-15 15:15:02 -0700263 uint32_t ps_ctrl = 0;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100264 int scaler_id = plane_state->scaler_id;
Chandra Konduruc3318792015-04-15 15:15:02 -0700265
266 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
267 PS_PLANE_SEL(plane));
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100268 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode;
Chandra Konduruc3318792015-04-15 15:15:02 -0700269 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
270 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
271 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
272 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
273 ((crtc_w + 1) << 16)|(crtc_h + 1));
274
275 I915_WRITE(PLANE_POS(pipe, plane), 0);
276 } else {
277 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
278 }
279
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000280 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +0000281 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000282 POSTING_READ(PLANE_SURF(pipe, plane));
283}
284
285static void
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +0200286skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000287{
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +0300288 struct drm_device *dev = dplane->dev;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000289 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +0300290 struct intel_plane *intel_plane = to_intel_plane(dplane);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000291 const int pipe = intel_plane->pipe;
292 const int plane = intel_plane->plane + 1;
293
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200294 I915_WRITE(PLANE_CTL(pipe, plane), 0);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000295
Ville Syrjälä2ddc1da2015-03-19 17:57:14 +0200296 I915_WRITE(PLANE_SURF(pipe, plane), 0);
297 POSTING_READ(PLANE_SURF(pipe, plane));
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000298}
299
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000300static void
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300301chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
302{
303 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
304 int plane = intel_plane->plane;
305
306 /* Seems RGB data bypasses the CSC always */
307 if (!format_is_yuv(format))
308 return;
309
310 /*
311 * BT.601 limited range YCbCr -> full range RGB
312 *
313 * |r| | 6537 4769 0| |cr |
314 * |g| = |-3330 4769 -1605| x |y-64|
315 * |b| | 0 4769 8263| |cb |
316 *
317 * Cb and Cr apparently come in as signed already, so no
318 * need for any offset. For Y we need to remove the offset.
319 */
320 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
321 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
322 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
323
324 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
325 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
326 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
327 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
328 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
329
330 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
331 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
332 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
333
334 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
335 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
336 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
337}
338
339static void
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100340vlv_update_plane(struct drm_plane *dplane,
341 const struct intel_crtc_state *crtc_state,
342 const struct intel_plane_state *plane_state)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700343{
344 struct drm_device *dev = dplane->dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
346 struct intel_plane *intel_plane = to_intel_plane(dplane);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100347 struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjäläbdd75542015-03-19 17:57:11 +0200348 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700349 int pipe = intel_plane->pipe;
350 int plane = intel_plane->plane;
351 u32 sprctl;
352 unsigned long sprsurf_offset, linear_offset;
353 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100354 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
355 int crtc_x = plane_state->dst.x1;
356 int crtc_y = plane_state->dst.y1;
357 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
358 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
359 uint32_t x = plane_state->src.x1 >> 16;
360 uint32_t y = plane_state->src.y1 >> 16;
361 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
362 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700363
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200364 sprctl = SP_ENABLE;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700365
366 switch (fb->pixel_format) {
367 case DRM_FORMAT_YUYV:
368 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
369 break;
370 case DRM_FORMAT_YVYU:
371 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
372 break;
373 case DRM_FORMAT_UYVY:
374 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
375 break;
376 case DRM_FORMAT_VYUY:
377 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
378 break;
379 case DRM_FORMAT_RGB565:
380 sprctl |= SP_FORMAT_BGR565;
381 break;
382 case DRM_FORMAT_XRGB8888:
383 sprctl |= SP_FORMAT_BGRX8888;
384 break;
385 case DRM_FORMAT_ARGB8888:
386 sprctl |= SP_FORMAT_BGRA8888;
387 break;
388 case DRM_FORMAT_XBGR2101010:
389 sprctl |= SP_FORMAT_RGBX1010102;
390 break;
391 case DRM_FORMAT_ABGR2101010:
392 sprctl |= SP_FORMAT_RGBA1010102;
393 break;
394 case DRM_FORMAT_XBGR8888:
395 sprctl |= SP_FORMAT_RGBX8888;
396 break;
397 case DRM_FORMAT_ABGR8888:
398 sprctl |= SP_FORMAT_RGBA8888;
399 break;
400 default:
401 /*
402 * If we get here one of the upper layers failed to filter
403 * out the unsupported plane formats
404 */
405 BUG();
406 break;
407 }
408
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -0800409 /*
410 * Enable gamma to match primary/cursor plane behaviour.
411 * FIXME should be user controllable via propertiesa.
412 */
413 sprctl |= SP_GAMMA_ENABLE;
414
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700415 if (obj->tiling_mode != I915_TILING_NONE)
416 sprctl |= SP_TILED;
417
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700418 /* Sizes are 0 based */
419 src_w--;
420 src_h--;
421 crtc_w--;
422 crtc_h--;
423
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700424 linear_offset = y * fb->pitches[0] + x * pixel_size;
Ville Syrjäläb5c65332016-01-12 21:08:31 +0200425 sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
426 fb->modifier[0],
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700427 pixel_size,
428 fb->pitches[0]);
429 linear_offset -= sprsurf_offset;
430
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100431 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530432 sprctl |= SP_ROTATE_180;
433
434 x += src_w;
435 y += src_h;
436 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
437 }
438
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200439 if (key->flags) {
440 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
441 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
442 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
443 }
444
445 if (key->flags & I915_SET_COLORKEY_SOURCE)
446 sprctl |= SP_SOURCE_KEY;
447
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300448 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
449 chv_update_csc(intel_plane, fb->pixel_format);
450
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200451 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
452 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
453
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700454 if (obj->tiling_mode != I915_TILING_NONE)
455 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
456 else
457 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
458
Ville Syrjäläc14b0482014-10-16 20:52:34 +0300459 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
460
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700461 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
462 I915_WRITE(SPCNTR(pipe, plane), sprctl);
Daniel Vetter85ba7b72014-01-24 10:31:44 +0100463 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
464 sprsurf_offset);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +0300465 POSTING_READ(SPSURF(pipe, plane));
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700466}
467
468static void
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +0200469vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700470{
471 struct drm_device *dev = dplane->dev;
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 struct intel_plane *intel_plane = to_intel_plane(dplane);
474 int pipe = intel_plane->pipe;
475 int plane = intel_plane->plane;
476
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200477 I915_WRITE(SPCNTR(pipe, plane), 0);
478
Daniel Vetter85ba7b72014-01-24 10:31:44 +0100479 I915_WRITE(SPSURF(pipe, plane), 0);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +0300480 POSTING_READ(SPSURF(pipe, plane));
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700481}
482
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700483static void
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100484ivb_update_plane(struct drm_plane *plane,
485 const struct intel_crtc_state *crtc_state,
486 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800487{
488 struct drm_device *dev = plane->dev;
489 struct drm_i915_private *dev_priv = dev->dev_private;
490 struct intel_plane *intel_plane = to_intel_plane(plane);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100491 struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjäläbdd75542015-03-19 17:57:11 +0200492 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200493 enum pipe pipe = intel_plane->pipe;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800494 u32 sprctl, sprscale = 0;
Damien Lespiau5a35e992012-10-26 18:20:12 +0100495 unsigned long sprsurf_offset, linear_offset;
Ville Syrjälä2bd3c3c2012-10-31 17:50:20 +0200496 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100497 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
498 int crtc_x = plane_state->dst.x1;
499 int crtc_y = plane_state->dst.y1;
500 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
501 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
502 uint32_t x = plane_state->src.x1 >> 16;
503 uint32_t y = plane_state->src.y1 >> 16;
504 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
505 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800506
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200507 sprctl = SPRITE_ENABLE;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800508
509 switch (fb->pixel_format) {
510 case DRM_FORMAT_XBGR8888:
Vijay Purushothaman5ee36912012-08-23 12:08:57 +0530511 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800512 break;
513 case DRM_FORMAT_XRGB8888:
Vijay Purushothaman5ee36912012-08-23 12:08:57 +0530514 sprctl |= SPRITE_FORMAT_RGBX888;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800515 break;
516 case DRM_FORMAT_YUYV:
517 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800518 break;
519 case DRM_FORMAT_YVYU:
520 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800521 break;
522 case DRM_FORMAT_UYVY:
523 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800524 break;
525 case DRM_FORMAT_VYUY:
526 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800527 break;
528 default:
Ville Syrjälä28d491d2012-10-31 17:50:21 +0200529 BUG();
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800530 }
531
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -0800532 /*
533 * Enable gamma to match primary/cursor plane behaviour.
534 * FIXME should be user controllable via propertiesa.
535 */
536 sprctl |= SPRITE_GAMMA_ENABLE;
537
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800538 if (obj->tiling_mode != I915_TILING_NONE)
539 sprctl |= SPRITE_TILED;
540
Ville Syrjäläb42c6002013-11-03 13:47:27 +0200541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -0300542 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
543 else
544 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
545
Ville Syrjälä6bbfa1c2013-11-02 21:07:39 -0700546 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjälä86d3efc2013-01-18 19:11:38 +0200547 sprctl |= SPRITE_PIPE_CSC_ENABLE;
548
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800549 /* Sizes are 0 based */
550 src_w--;
551 src_h--;
552 crtc_w--;
553 crtc_h--;
554
Ville Syrjälä8553c182013-12-05 15:51:39 +0200555 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800556 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800557
Chris Wilsonca320ac2012-12-19 12:14:22 +0000558 linear_offset = y * fb->pitches[0] + x * pixel_size;
Ville Syrjäläb5c65332016-01-12 21:08:31 +0200559 sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
560 fb->modifier[0],
561 pixel_size,
562 fb->pitches[0]);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100563 linear_offset -= sprsurf_offset;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800564
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100565 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530566 sprctl |= SPRITE_ROTATE_180;
567
568 /* HSW and BDW does this automagically in hardware */
569 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
570 x += src_w;
571 y += src_h;
572 linear_offset += src_h * fb->pitches[0] +
573 src_w * pixel_size;
574 }
575 }
576
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200577 if (key->flags) {
578 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
579 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
580 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
581 }
582
583 if (key->flags & I915_SET_COLORKEY_DESTINATION)
584 sprctl |= SPRITE_DEST_KEY;
585 else if (key->flags & I915_SET_COLORKEY_SOURCE)
586 sprctl |= SPRITE_SOURCE_KEY;
587
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200588 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
589 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
590
Damien Lespiau5a35e992012-10-26 18:20:12 +0100591 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
592 * register */
Paulo Zanonib3dc6852013-11-02 21:07:33 -0700593 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Damien Lespiau5a35e992012-10-26 18:20:12 +0100594 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
595 else if (obj->tiling_mode != I915_TILING_NONE)
596 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
597 else
598 I915_WRITE(SPRLINOFF(pipe), linear_offset);
Damien Lespiauc54173a2012-10-26 18:20:11 +0100599
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800600 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
Damien Lespiau2d354c32012-10-22 18:19:27 +0100601 if (intel_plane->can_scale)
602 I915_WRITE(SPRSCALE(pipe), sprscale);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800603 I915_WRITE(SPRCTL(pipe), sprctl);
Daniel Vetter85ba7b72014-01-24 10:31:44 +0100604 I915_WRITE(SPRSURF(pipe),
605 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +0300606 POSTING_READ(SPRSURF(pipe));
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800607}
608
609static void
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +0200610ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800611{
612 struct drm_device *dev = plane->dev;
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 struct intel_plane *intel_plane = to_intel_plane(plane);
615 int pipe = intel_plane->pipe;
616
Ville Syrjäläc5626572015-10-15 17:04:04 +0300617 I915_WRITE(SPRCTL(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800618 /* Can't leave the scaler enabled... */
Damien Lespiau2d354c32012-10-22 18:19:27 +0100619 if (intel_plane->can_scale)
620 I915_WRITE(SPRSCALE(pipe), 0);
Ville Syrjälä5b633d62014-04-29 13:35:47 +0300621
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +0300622 I915_WRITE(SPRSURF(pipe), 0);
623 POSTING_READ(SPRSURF(pipe));
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800624}
625
626static void
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100627ilk_update_plane(struct drm_plane *plane,
628 const struct intel_crtc_state *crtc_state,
629 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800630{
631 struct drm_device *dev = plane->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 struct intel_plane *intel_plane = to_intel_plane(plane);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100634 struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjäläbdd75542015-03-19 17:57:11 +0200635 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Ville Syrjälä2bd3c3c2012-10-31 17:50:20 +0200636 int pipe = intel_plane->pipe;
Damien Lespiau5a35e992012-10-26 18:20:12 +0100637 unsigned long dvssurf_offset, linear_offset;
Chris Wilson8aaa81a2012-04-14 22:14:26 +0100638 u32 dvscntr, dvsscale;
Ville Syrjälä2bd3c3c2012-10-31 17:50:20 +0200639 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100640 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
641 int crtc_x = plane_state->dst.x1;
642 int crtc_y = plane_state->dst.y1;
643 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
644 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
645 uint32_t x = plane_state->src.x1 >> 16;
646 uint32_t y = plane_state->src.y1 >> 16;
647 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
648 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800649
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200650 dvscntr = DVS_ENABLE;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800651
652 switch (fb->pixel_format) {
653 case DRM_FORMAT_XBGR8888:
Jesse Barnesab2f9df2012-02-27 12:40:10 -0800654 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800655 break;
656 case DRM_FORMAT_XRGB8888:
Jesse Barnesab2f9df2012-02-27 12:40:10 -0800657 dvscntr |= DVS_FORMAT_RGBX888;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800658 break;
659 case DRM_FORMAT_YUYV:
660 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800661 break;
662 case DRM_FORMAT_YVYU:
663 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800664 break;
665 case DRM_FORMAT_UYVY:
666 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800667 break;
668 case DRM_FORMAT_VYUY:
669 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800670 break;
671 default:
Ville Syrjälä28d491d2012-10-31 17:50:21 +0200672 BUG();
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800673 }
674
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -0800675 /*
676 * Enable gamma to match primary/cursor plane behaviour.
677 * FIXME should be user controllable via propertiesa.
678 */
679 dvscntr |= DVS_GAMMA_ENABLE;
680
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800681 if (obj->tiling_mode != I915_TILING_NONE)
682 dvscntr |= DVS_TILED;
683
Chris Wilsond1686ae2012-04-10 11:41:49 +0100684 if (IS_GEN6(dev))
685 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800686
687 /* Sizes are 0 based */
688 src_w--;
689 src_h--;
690 crtc_w--;
691 crtc_h--;
692
Chris Wilson8aaa81a2012-04-14 22:14:26 +0100693 dvsscale = 0;
Ville Syrjälä8368f012013-12-05 15:51:31 +0200694 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800695 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
696
Chris Wilsonca320ac2012-12-19 12:14:22 +0000697 linear_offset = y * fb->pitches[0] + x * pixel_size;
Ville Syrjäläb5c65332016-01-12 21:08:31 +0200698 dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
699 fb->modifier[0],
700 pixel_size,
701 fb->pitches[0]);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100702 linear_offset -= dvssurf_offset;
703
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100704 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530705 dvscntr |= DVS_ROTATE_180;
706
707 x += src_w;
708 y += src_h;
709 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
710 }
711
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200712 if (key->flags) {
713 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
714 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
715 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
716 }
717
718 if (key->flags & I915_SET_COLORKEY_DESTINATION)
719 dvscntr |= DVS_DEST_KEY;
720 else if (key->flags & I915_SET_COLORKEY_SOURCE)
721 dvscntr |= DVS_SOURCE_KEY;
722
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200723 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
724 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
725
Damien Lespiau5a35e992012-10-26 18:20:12 +0100726 if (obj->tiling_mode != I915_TILING_NONE)
727 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
728 else
729 I915_WRITE(DVSLINOFF(pipe), linear_offset);
730
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800731 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
732 I915_WRITE(DVSSCALE(pipe), dvsscale);
733 I915_WRITE(DVSCNTR(pipe), dvscntr);
Daniel Vetter85ba7b72014-01-24 10:31:44 +0100734 I915_WRITE(DVSSURF(pipe),
735 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +0300736 POSTING_READ(DVSSURF(pipe));
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800737}
738
739static void
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +0200740ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800741{
742 struct drm_device *dev = plane->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_plane *intel_plane = to_intel_plane(plane);
745 int pipe = intel_plane->pipe;
746
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200747 I915_WRITE(DVSCNTR(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800748 /* Disable the scaler */
749 I915_WRITE(DVSSCALE(pipe), 0);
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200750
Daniel Vetter85ba7b72014-01-24 10:31:44 +0100751 I915_WRITE(DVSSURF(pipe), 0);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +0300752 POSTING_READ(DVSSURF(pipe));
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800753}
754
Jesse Barnes8ea30862012-01-03 08:05:39 -0800755static int
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300756intel_check_sprite_plane(struct drm_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +0200757 struct intel_crtc_state *crtc_state,
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300758 struct intel_plane_state *state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800759{
Chandra Konduruc3318792015-04-15 15:15:02 -0700760 struct drm_device *dev = plane->dev;
Maarten Lankhorst061e4b82015-06-15 12:33:46 +0200761 struct drm_crtc *crtc = state->base.crtc;
762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800763 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper2b875c22014-12-01 15:40:13 -0800764 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300765 int crtc_x, crtc_y;
766 unsigned int crtc_w, crtc_h;
767 uint32_t src_x, src_y, src_w, src_h;
768 struct drm_rect *src = &state->src;
769 struct drm_rect *dst = &state->dst;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300770 const struct drm_rect *clip = &state->clip;
Ville Syrjälä17316932013-04-24 18:52:38 +0300771 int hscale, vscale;
772 int max_scale, min_scale;
Chandra Konduru225c2282015-05-18 16:18:44 -0700773 bool can_scale;
Matt Ropercf4c7c12014-12-04 10:27:42 -0800774 int pixel_size;
775
776 if (!fb) {
777 state->visible = false;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +0200778 return 0;
Matt Ropercf4c7c12014-12-04 10:27:42 -0800779 }
Jesse Barnes5e1bac22013-03-26 09:25:43 -0700780
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800781 /* Don't modify another pipe's plane */
Ville Syrjälä17316932013-04-24 18:52:38 +0300782 if (intel_plane->pipe != intel_crtc->pipe) {
783 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800784 return -EINVAL;
Ville Syrjälä17316932013-04-24 18:52:38 +0300785 }
786
787 /* FIXME check all gen limits */
788 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
789 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
790 return -EINVAL;
791 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800792
Chandra Konduru225c2282015-05-18 16:18:44 -0700793 /* setup can_scale, min_scale, max_scale */
794 if (INTEL_INFO(dev)->gen >= 9) {
795 /* use scaler when colorkey is not required */
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200796 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
Chandra Konduru225c2282015-05-18 16:18:44 -0700797 can_scale = 1;
798 min_scale = 1;
799 max_scale = skl_max_scale(intel_crtc, crtc_state);
800 } else {
801 can_scale = 0;
802 min_scale = DRM_PLANE_HELPER_NO_SCALING;
803 max_scale = DRM_PLANE_HELPER_NO_SCALING;
804 }
805 } else {
806 can_scale = intel_plane->can_scale;
807 max_scale = intel_plane->max_downscale << 16;
808 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
809 }
810
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300811 /*
812 * FIXME the following code does a bunch of fuzzy adjustments to the
813 * coordinates and sizes. We probably need some way to decide whether
814 * more strict checking should be done instead.
815 */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300816 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
Matt Roper8e7d6882015-01-21 16:35:41 -0800817 state->base.rotation);
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530818
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300819 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300820 BUG_ON(hscale < 0);
Ville Syrjälä17316932013-04-24 18:52:38 +0300821
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300822 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300823 BUG_ON(vscale < 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800824
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200825 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800826
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300827 crtc_x = dst->x1;
828 crtc_y = dst->y1;
829 crtc_w = drm_rect_width(dst);
830 crtc_h = drm_rect_height(dst);
Damien Lespiau2d354c32012-10-22 18:19:27 +0100831
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300832 if (state->visible) {
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300833 /* check again in case clipping clamped the results */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300834 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300835 if (hscale < 0) {
836 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
Ville Syrjäläc70f5772015-11-16 17:02:36 +0200837 drm_rect_debug_print("src: ", src, true);
838 drm_rect_debug_print("dst: ", dst, false);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300839
840 return hscale;
841 }
842
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300843 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300844 if (vscale < 0) {
845 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
Ville Syrjäläc70f5772015-11-16 17:02:36 +0200846 drm_rect_debug_print("src: ", src, true);
847 drm_rect_debug_print("dst: ", dst, false);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300848
849 return vscale;
850 }
851
Ville Syrjälä17316932013-04-24 18:52:38 +0300852 /* Make the source viewport size an exact multiple of the scaling factors. */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300853 drm_rect_adjust_size(src,
854 drm_rect_width(dst) * hscale - drm_rect_width(src),
855 drm_rect_height(dst) * vscale - drm_rect_height(src));
Ville Syrjälä17316932013-04-24 18:52:38 +0300856
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300857 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
Matt Roper8e7d6882015-01-21 16:35:41 -0800858 state->base.rotation);
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530859
Ville Syrjälä17316932013-04-24 18:52:38 +0300860 /* sanity check to make sure the src viewport wasn't enlarged */
Matt Roperea2c67b2014-12-23 10:41:52 -0800861 WARN_ON(src->x1 < (int) state->base.src_x ||
862 src->y1 < (int) state->base.src_y ||
863 src->x2 > (int) state->base.src_x + state->base.src_w ||
864 src->y2 > (int) state->base.src_y + state->base.src_h);
Ville Syrjälä17316932013-04-24 18:52:38 +0300865
866 /*
867 * Hardware doesn't handle subpixel coordinates.
868 * Adjust to (macro)pixel boundary, but be careful not to
869 * increase the source viewport size, because that could
870 * push the downscaling factor out of bounds.
Ville Syrjälä17316932013-04-24 18:52:38 +0300871 */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300872 src_x = src->x1 >> 16;
873 src_w = drm_rect_width(src) >> 16;
874 src_y = src->y1 >> 16;
875 src_h = drm_rect_height(src) >> 16;
Ville Syrjälä17316932013-04-24 18:52:38 +0300876
877 if (format_is_yuv(fb->pixel_format)) {
878 src_x &= ~1;
879 src_w &= ~1;
880
881 /*
882 * Must keep src and dst the
883 * same if we can't scale.
884 */
Chandra Konduru225c2282015-05-18 16:18:44 -0700885 if (!can_scale)
Ville Syrjälä17316932013-04-24 18:52:38 +0300886 crtc_w &= ~1;
887
888 if (crtc_w == 0)
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300889 state->visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300890 }
891 }
892
893 /* Check size restrictions when scaling */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300894 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300895 unsigned int width_bytes;
896
Chandra Konduru225c2282015-05-18 16:18:44 -0700897 WARN_ON(!can_scale);
Ville Syrjälä17316932013-04-24 18:52:38 +0300898
899 /* FIXME interlacing min height is 6 */
900
901 if (crtc_w < 3 || crtc_h < 3)
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300902 state->visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300903
904 if (src_w < 3 || src_h < 3)
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300905 state->visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300906
Matt Ropercf4c7c12014-12-04 10:27:42 -0800907 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300908 width_bytes = ((src_x * pixel_size) & 63) +
909 src_w * pixel_size;
Ville Syrjälä17316932013-04-24 18:52:38 +0300910
Chandra Konduruc3318792015-04-15 15:15:02 -0700911 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
912 width_bytes > 4096 || fb->pitches[0] > 4096)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300913 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
914 return -EINVAL;
915 }
916 }
917
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300918 if (state->visible) {
Chandra Konduru0a5ae1b2015-04-09 16:41:54 -0700919 src->x1 = src_x << 16;
920 src->x2 = (src_x + src_w) << 16;
921 src->y1 = src_y << 16;
922 src->y2 = (src_y + src_h) << 16;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300923 }
924
925 dst->x1 = crtc_x;
926 dst->x2 = crtc_x + crtc_w;
927 dst->y1 = crtc_y;
928 dst->y2 = crtc_y + crtc_h;
929
930 return 0;
931}
932
Jesse Barnes8ea30862012-01-03 08:05:39 -0800933int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
934 struct drm_file *file_priv)
935{
936 struct drm_intel_sprite_colorkey *set = data;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800937 struct drm_plane *plane;
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200938 struct drm_plane_state *plane_state;
939 struct drm_atomic_state *state;
940 struct drm_modeset_acquire_ctx ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800941 int ret = 0;
942
Jesse Barnes8ea30862012-01-03 08:05:39 -0800943 /* Make sure we don't try to enable both src & dest simultaneously */
944 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
945 return -EINVAL;
946
Wayne Boyer666a4532015-12-09 12:29:35 -0800947 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200948 set->flags & I915_SET_COLORKEY_DESTINATION)
949 return -EINVAL;
950
Rob Clark7707e652014-07-17 23:30:04 -0400951 plane = drm_plane_find(dev, set->plane_id);
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200952 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
953 return -ENOENT;
954
955 drm_modeset_acquire_init(&ctx, 0);
956
957 state = drm_atomic_state_alloc(plane->dev);
958 if (!state) {
959 ret = -ENOMEM;
960 goto out;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800961 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200962 state->acquire_ctx = &ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800963
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200964 while (1) {
965 plane_state = drm_atomic_get_plane_state(state, plane);
966 ret = PTR_ERR_OR_ZERO(plane_state);
967 if (!ret) {
968 to_intel_plane_state(plane_state)->ckey = *set;
969 ret = drm_atomic_commit(state);
Chandra Konduru6156a452015-04-27 13:48:39 -0700970 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200971
972 if (ret != -EDEADLK)
973 break;
974
975 drm_atomic_state_clear(state);
976 drm_modeset_backoff(&ctx);
Chandra Konduru6156a452015-04-27 13:48:39 -0700977 }
978
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200979 if (ret)
980 drm_atomic_state_free(state);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200981
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200982out:
983 drm_modeset_drop_locks(&ctx);
984 drm_modeset_acquire_fini(&ctx);
Jesse Barnes8ea30862012-01-03 08:05:39 -0800985 return ret;
986}
987
Damien Lespiaudada2d52015-05-12 16:13:22 +0100988static const uint32_t ilk_plane_formats[] = {
Chris Wilsond1686ae2012-04-10 11:41:49 +0100989 DRM_FORMAT_XRGB8888,
990 DRM_FORMAT_YUYV,
991 DRM_FORMAT_YVYU,
992 DRM_FORMAT_UYVY,
993 DRM_FORMAT_VYUY,
994};
995
Damien Lespiaudada2d52015-05-12 16:13:22 +0100996static const uint32_t snb_plane_formats[] = {
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800997 DRM_FORMAT_XBGR8888,
998 DRM_FORMAT_XRGB8888,
999 DRM_FORMAT_YUYV,
1000 DRM_FORMAT_YVYU,
1001 DRM_FORMAT_UYVY,
1002 DRM_FORMAT_VYUY,
1003};
1004
Damien Lespiaudada2d52015-05-12 16:13:22 +01001005static const uint32_t vlv_plane_formats[] = {
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001006 DRM_FORMAT_RGB565,
1007 DRM_FORMAT_ABGR8888,
1008 DRM_FORMAT_ARGB8888,
1009 DRM_FORMAT_XBGR8888,
1010 DRM_FORMAT_XRGB8888,
1011 DRM_FORMAT_XBGR2101010,
1012 DRM_FORMAT_ABGR2101010,
1013 DRM_FORMAT_YUYV,
1014 DRM_FORMAT_YVYU,
1015 DRM_FORMAT_UYVY,
1016 DRM_FORMAT_VYUY,
1017};
1018
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001019static uint32_t skl_plane_formats[] = {
1020 DRM_FORMAT_RGB565,
1021 DRM_FORMAT_ABGR8888,
1022 DRM_FORMAT_ARGB8888,
1023 DRM_FORMAT_XBGR8888,
1024 DRM_FORMAT_XRGB8888,
1025 DRM_FORMAT_YUYV,
1026 DRM_FORMAT_YVYU,
1027 DRM_FORMAT_UYVY,
1028 DRM_FORMAT_VYUY,
1029};
1030
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001031int
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001032intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001033{
1034 struct intel_plane *intel_plane;
Matt Roper8e7d6882015-01-21 16:35:41 -08001035 struct intel_plane_state *state;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001036 unsigned long possible_crtcs;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001037 const uint32_t *plane_formats;
1038 int num_plane_formats;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001039 int ret;
1040
Chris Wilsond1686ae2012-04-10 11:41:49 +01001041 if (INTEL_INFO(dev)->gen < 5)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001042 return -ENODEV;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001043
Daniel Vetterb14c5672013-09-19 12:18:32 +02001044 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001045 if (!intel_plane)
1046 return -ENOMEM;
1047
Matt Roper8e7d6882015-01-21 16:35:41 -08001048 state = intel_create_plane_state(&intel_plane->base);
1049 if (!state) {
Matt Roperea2c67b2014-12-23 10:41:52 -08001050 kfree(intel_plane);
1051 return -ENOMEM;
1052 }
Matt Roper8e7d6882015-01-21 16:35:41 -08001053 intel_plane->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -08001054
Chris Wilsond1686ae2012-04-10 11:41:49 +01001055 switch (INTEL_INFO(dev)->gen) {
1056 case 5:
1057 case 6:
Damien Lespiau2d354c32012-10-22 18:19:27 +01001058 intel_plane->can_scale = true;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001059 intel_plane->max_downscale = 16;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001060 intel_plane->update_plane = ilk_update_plane;
1061 intel_plane->disable_plane = ilk_disable_plane;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001062
1063 if (IS_GEN6(dev)) {
1064 plane_formats = snb_plane_formats;
1065 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1066 } else {
1067 plane_formats = ilk_plane_formats;
1068 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1069 }
1070 break;
1071
1072 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07001073 case 8:
Damien Lespiaud49f7092013-04-25 15:15:00 +01001074 if (IS_IVYBRIDGE(dev)) {
Damien Lespiau2d354c32012-10-22 18:19:27 +01001075 intel_plane->can_scale = true;
Damien Lespiaud49f7092013-04-25 15:15:00 +01001076 intel_plane->max_downscale = 2;
1077 } else {
1078 intel_plane->can_scale = false;
1079 intel_plane->max_downscale = 1;
1080 }
Chris Wilsond1686ae2012-04-10 11:41:49 +01001081
Wayne Boyer666a4532015-12-09 12:29:35 -08001082 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001083 intel_plane->update_plane = vlv_update_plane;
1084 intel_plane->disable_plane = vlv_disable_plane;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001085
1086 plane_formats = vlv_plane_formats;
1087 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1088 } else {
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001089 intel_plane->update_plane = ivb_update_plane;
1090 intel_plane->disable_plane = ivb_disable_plane;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001091
1092 plane_formats = snb_plane_formats;
1093 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1094 }
Chris Wilsond1686ae2012-04-10 11:41:49 +01001095 break;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001096 case 9:
Chandra Konduruc3318792015-04-15 15:15:02 -07001097 intel_plane->can_scale = true;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001098 intel_plane->update_plane = skl_update_plane;
1099 intel_plane->disable_plane = skl_disable_plane;
Chandra Konduru549e2bf2015-04-07 15:28:38 -07001100 state->scaler_id = -1;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001101
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001102 plane_formats = skl_plane_formats;
1103 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1104 break;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001105 default:
Jesper Juhla8b0bba2012-06-27 00:55:37 +02001106 kfree(intel_plane);
Chris Wilsond1686ae2012-04-10 11:41:49 +01001107 return -ENODEV;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001108 }
1109
1110 intel_plane->pipe = pipe;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001111 intel_plane->plane = plane;
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05301112 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
Matt Roperc59cb172014-12-01 15:40:16 -08001113 intel_plane->check_plane = intel_check_sprite_plane;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001114 possible_crtcs = (1 << pipe);
Derek Foreman8fe8a3f2014-09-03 10:38:20 -03001115 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
Matt Roper65a3fea2015-01-21 16:35:42 -08001116 &intel_plane_funcs,
Derek Foreman8fe8a3f2014-09-03 10:38:20 -03001117 plane_formats, num_plane_formats,
1118 DRM_PLANE_TYPE_OVERLAY);
Ville Syrjälä7ed6eee2014-08-05 11:26:55 +05301119 if (ret) {
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001120 kfree(intel_plane);
Ville Syrjälä7ed6eee2014-08-05 11:26:55 +05301121 goto out;
1122 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001123
Sonika Jindal3b7a5112015-04-10 14:37:29 +05301124 intel_create_rotation_property(dev, intel_plane);
Ville Syrjälä7ed6eee2014-08-05 11:26:55 +05301125
Matt Roperea2c67b2014-12-23 10:41:52 -08001126 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1127
Damien Lespiaucaf4e252015-06-04 16:56:18 +01001128out:
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001129 return ret;
1130}