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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl-topology.h"
27#include "skl.h"
28#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053029#include "../common/sst-dsp.h"
30#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010031
Jeeja KPf7590d42015-10-07 11:31:53 +010032#define SKL_CH_FIXUP_MASK (1 << 0)
33#define SKL_RATE_FIXUP_MASK (1 << 1)
34#define SKL_FMT_FIXUP_MASK (1 << 2)
35
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010036/*
37 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
38 * ignore. This helpers checks if the SKL driver handles this widget type
39 */
40static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
41{
42 switch (w->id) {
43 case snd_soc_dapm_dai_link:
44 case snd_soc_dapm_dai_in:
45 case snd_soc_dapm_aif_in:
46 case snd_soc_dapm_aif_out:
47 case snd_soc_dapm_dai_out:
48 case snd_soc_dapm_switch:
49 return false;
50 default:
51 return true;
52 }
53}
54
55/*
56 * Each pipelines needs memory to be allocated. Check if we have free memory
57 * from available pool. Then only add this to pool
58 * This is freed when pipe is deleted
59 * Note: DSP does actual memory management we only keep track for complete
60 * pool
61 */
62static bool skl_tplg_alloc_pipe_mem(struct skl *skl,
63 struct skl_module_cfg *mconfig)
64{
65 struct skl_sst *ctx = skl->skl_sst;
66
67 if (skl->resource.mem + mconfig->pipe->memory_pages >
68 skl->resource.max_mem) {
69 dev_err(ctx->dev,
70 "%s: module_id %d instance %d\n", __func__,
71 mconfig->id.module_id,
72 mconfig->id.instance_id);
73 dev_err(ctx->dev,
74 "exceeds ppl memory available %d mem %d\n",
75 skl->resource.max_mem, skl->resource.mem);
76 return false;
77 }
78
79 skl->resource.mem += mconfig->pipe->memory_pages;
80 return true;
81}
82
83/*
84 * Pipeline needs needs DSP CPU resources for computation, this is
85 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
86 *
87 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
88 * pipe. This adds the mcps to driver counter
89 * This is removed on pipeline delete
90 */
91static bool skl_tplg_alloc_pipe_mcps(struct skl *skl,
92 struct skl_module_cfg *mconfig)
93{
94 struct skl_sst *ctx = skl->skl_sst;
95
96 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
97 dev_err(ctx->dev,
98 "%s: module_id %d instance %d\n", __func__,
99 mconfig->id.module_id, mconfig->id.instance_id);
100 dev_err(ctx->dev,
101 "exceeds ppl memory available %d > mem %d\n",
102 skl->resource.max_mcps, skl->resource.mcps);
103 return false;
104 }
105
106 skl->resource.mcps += mconfig->mcps;
107 return true;
108}
109
110/*
111 * Free the mcps when tearing down
112 */
113static void
114skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
115{
116 skl->resource.mcps -= mconfig->mcps;
117}
118
119/*
120 * Free the memory when tearing down
121 */
122static void
123skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
124{
125 skl->resource.mem -= mconfig->pipe->memory_pages;
126}
127
Jeeja KPf7590d42015-10-07 11:31:53 +0100128
129static void skl_dump_mconfig(struct skl_sst *ctx,
130 struct skl_module_cfg *mcfg)
131{
132 dev_dbg(ctx->dev, "Dumping config\n");
133 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900134 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
135 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
136 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
137 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100138 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900139 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
140 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
141 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
142 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100143}
144
145static void skl_tplg_update_params(struct skl_module_fmt *fmt,
146 struct skl_pipe_params *params, int fixup)
147{
148 if (fixup & SKL_RATE_FIXUP_MASK)
149 fmt->s_freq = params->s_freq;
150 if (fixup & SKL_CH_FIXUP_MASK)
151 fmt->channels = params->ch;
Jeeja KP98256f82015-11-23 22:26:25 +0530152 if (fixup & SKL_FMT_FIXUP_MASK) {
153 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
154
155 /*
156 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
157 * container so update bit depth accordingly
158 */
159 switch (fmt->valid_bit_depth) {
160 case SKL_DEPTH_16BIT:
161 fmt->bit_depth = fmt->valid_bit_depth;
162 break;
163
164 default:
165 fmt->bit_depth = SKL_DEPTH_32BIT;
166 break;
167 }
168 }
169
Jeeja KPf7590d42015-10-07 11:31:53 +0100170}
171
172/*
173 * A pipeline may have modules which impact the pcm parameters, like SRC,
174 * channel converter, format converter.
175 * We need to calculate the output params by applying the 'fixup'
176 * Topology will tell driver which type of fixup is to be applied by
177 * supplying the fixup mask, so based on that we calculate the output
178 *
179 * Now In FE the pcm hw_params is source/target format. Same is applicable
180 * for BE with its hw_params invoked.
181 * here based on FE, BE pipeline and direction we calculate the input and
182 * outfix and then apply that for a module
183 */
184static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
185 struct skl_pipe_params *params, bool is_fe)
186{
187 int in_fixup, out_fixup;
188 struct skl_module_fmt *in_fmt, *out_fmt;
189
Hardik T Shah4cd98992015-10-27 09:22:55 +0900190 /* Fixups will be applied to pin 0 only */
191 in_fmt = &m_cfg->in_fmt[0];
192 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100193
194 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
195 if (is_fe) {
196 in_fixup = m_cfg->params_fixup;
197 out_fixup = (~m_cfg->converter) &
198 m_cfg->params_fixup;
199 } else {
200 out_fixup = m_cfg->params_fixup;
201 in_fixup = (~m_cfg->converter) &
202 m_cfg->params_fixup;
203 }
204 } else {
205 if (is_fe) {
206 out_fixup = m_cfg->params_fixup;
207 in_fixup = (~m_cfg->converter) &
208 m_cfg->params_fixup;
209 } else {
210 in_fixup = m_cfg->params_fixup;
211 out_fixup = (~m_cfg->converter) &
212 m_cfg->params_fixup;
213 }
214 }
215
216 skl_tplg_update_params(in_fmt, params, in_fixup);
217 skl_tplg_update_params(out_fmt, params, out_fixup);
218}
219
220/*
221 * A module needs input and output buffers, which are dependent upon pcm
222 * params, so once we have calculate params, we need buffer calculation as
223 * well.
224 */
225static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
226 struct skl_module_cfg *mcfg)
227{
228 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900229 struct skl_module_fmt *in_fmt, *out_fmt;
230
231
232 /* Since fixups is applied to pin 0 only, ibs, obs needs
233 * change for pin 0 only
234 */
235 in_fmt = &mcfg->in_fmt[0];
236 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100237
238 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
239 multiplier = 5;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900240 mcfg->ibs = (in_fmt->s_freq / 1000) *
241 (mcfg->in_fmt->channels) *
242 (mcfg->in_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100243 multiplier;
244
Hardik T Shah4cd98992015-10-27 09:22:55 +0900245 mcfg->obs = (mcfg->out_fmt->s_freq / 1000) *
246 (mcfg->out_fmt->channels) *
247 (mcfg->out_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100248 multiplier;
249}
250
251static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
252 struct skl_sst *ctx)
253{
254 struct skl_module_cfg *m_cfg = w->priv;
255 struct skl_pipe_params *params = m_cfg->pipe->p_params;
256 int p_conn_type = m_cfg->pipe->conn_type;
257 bool is_fe;
258
259 if (!m_cfg->params_fixup)
260 return;
261
262 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
263 w->name);
264
265 skl_dump_mconfig(ctx, m_cfg);
266
267 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
268 is_fe = true;
269 else
270 is_fe = false;
271
272 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
273 skl_tplg_update_buffer_size(ctx, m_cfg);
274
275 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
276 w->name);
277
278 skl_dump_mconfig(ctx, m_cfg);
279}
280
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100281/*
282 * A pipe can have multiple modules, each of them will be a DAPM widget as
283 * well. While managing a pipeline we need to get the list of all the
284 * widgets in a pipelines, so this helper - skl_tplg_get_pipe_widget() helps
285 * to get the SKL type widgets in that pipeline
286 */
287static int skl_tplg_alloc_pipe_widget(struct device *dev,
288 struct snd_soc_dapm_widget *w, struct skl_pipe *pipe)
289{
290 struct skl_module_cfg *src_module = NULL;
291 struct snd_soc_dapm_path *p = NULL;
292 struct skl_pipe_module *p_module = NULL;
293
294 p_module = devm_kzalloc(dev, sizeof(*p_module), GFP_KERNEL);
295 if (!p_module)
296 return -ENOMEM;
297
298 p_module->w = w;
299 list_add_tail(&p_module->node, &pipe->w_list);
300
301 snd_soc_dapm_widget_for_each_sink_path(w, p) {
302 if ((p->sink->priv == NULL)
303 && (!is_skl_dsp_widget_type(w)))
304 continue;
305
306 if ((p->sink->priv != NULL) && p->connect
307 && is_skl_dsp_widget_type(p->sink)) {
308
309 src_module = p->sink->priv;
310 if (pipe->ppl_id == src_module->pipe->ppl_id)
311 skl_tplg_alloc_pipe_widget(dev,
312 p->sink, pipe);
313 }
314 }
315 return 0;
316}
317
318/*
Jeeja KPabb74002015-11-28 15:01:49 +0530319 * some modules can have multiple params set from user control and
320 * need to be set after module is initialized. If set_param flag is
321 * set module params will be done after module is initialised.
322 */
323static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
324 struct skl_sst *ctx)
325{
326 int i, ret;
327 struct skl_module_cfg *mconfig = w->priv;
328 const struct snd_kcontrol_new *k;
329 struct soc_bytes_ext *sb;
330 struct skl_algo_data *bc;
331 struct skl_specific_cfg *sp_cfg;
332
333 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530334 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530335 sp_cfg = &mconfig->formats_config;
336 ret = skl_set_module_params(ctx, sp_cfg->caps,
337 sp_cfg->caps_size,
338 sp_cfg->param_id, mconfig);
339 if (ret < 0)
340 return ret;
341 }
342
343 for (i = 0; i < w->num_kcontrols; i++) {
344 k = &w->kcontrol_news[i];
345 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
346 sb = (void *) k->private_value;
347 bc = (struct skl_algo_data *)sb->dobj.private;
348
Jeeja KP4ced1822015-12-03 23:29:53 +0530349 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530350 ret = skl_set_module_params(ctx,
351 (u32 *)bc->params, bc->max,
352 bc->param_id, mconfig);
353 if (ret < 0)
354 return ret;
355 }
356 }
357 }
358
359 return 0;
360}
361
362/*
363 * some module param can set from user control and this is required as
364 * when module is initailzed. if module param is required in init it is
365 * identifed by set_param flag. if set_param flag is not set, then this
366 * parameter needs to set as part of module init.
367 */
368static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
369{
370 const struct snd_kcontrol_new *k;
371 struct soc_bytes_ext *sb;
372 struct skl_algo_data *bc;
373 struct skl_module_cfg *mconfig = w->priv;
374 int i;
375
376 for (i = 0; i < w->num_kcontrols; i++) {
377 k = &w->kcontrol_news[i];
378 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
379 sb = (struct soc_bytes_ext *)k->private_value;
380 bc = (struct skl_algo_data *)sb->dobj.private;
381
Jeeja KP4ced1822015-12-03 23:29:53 +0530382 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530383 continue;
384
385 mconfig->formats_config.caps = (u32 *)&bc->params;
386 mconfig->formats_config.caps_size = bc->max;
387
388 break;
389 }
390 }
391
392 return 0;
393}
394
395/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100396 * Inside a pipe instance, we can have various modules. These modules need
397 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
398 * skl_init_module() routine, so invoke that for all modules in a pipeline
399 */
400static int
401skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
402{
403 struct skl_pipe_module *w_module;
404 struct snd_soc_dapm_widget *w;
405 struct skl_module_cfg *mconfig;
406 struct skl_sst *ctx = skl->skl_sst;
407 int ret = 0;
408
409 list_for_each_entry(w_module, &pipe->w_list, node) {
410 w = w_module->w;
411 mconfig = w->priv;
412
413 /* check resource available */
414 if (!skl_tplg_alloc_pipe_mcps(skl, mconfig))
415 return -ENOMEM;
416
Dharageswari R6c5768b2015-12-03 23:29:50 +0530417 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
418 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
419 mconfig->id.module_id, mconfig->guid);
420 if (ret < 0)
421 return ret;
422 }
423
Jeeja KPf7590d42015-10-07 11:31:53 +0100424 /*
425 * apply fix/conversion to module params based on
426 * FE/BE params
427 */
428 skl_tplg_update_module_params(w, ctx);
Jeeja KPabb74002015-11-28 15:01:49 +0530429
430 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530431 ret = skl_init_module(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100432 if (ret < 0)
433 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530434
435 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100436 if (ret < 0)
437 return ret;
438 }
439
440 return 0;
441}
Vinod Kould93f8e52015-10-07 11:31:54 +0100442
Dharageswari R6c5768b2015-12-03 23:29:50 +0530443static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
444 struct skl_pipe *pipe)
445{
446 struct skl_pipe_module *w_module = NULL;
447 struct skl_module_cfg *mconfig = NULL;
448
449 list_for_each_entry(w_module, &pipe->w_list, node) {
450 mconfig = w_module->w->priv;
451
452 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod)
453 return ctx->dsp->fw_ops.unload_mod(ctx->dsp,
454 mconfig->id.module_id);
455 }
456
457 /* no modules to unload in this path, so return */
458 return 0;
459}
460
Vinod Kould93f8e52015-10-07 11:31:54 +0100461/*
462 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
463 * need create the pipeline. So we do following:
464 * - check the resources
465 * - Create the pipeline
466 * - Initialize the modules in pipeline
467 * - finally bind all modules together
468 */
469static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
470 struct skl *skl)
471{
472 int ret;
473 struct skl_module_cfg *mconfig = w->priv;
474 struct skl_pipe_module *w_module;
475 struct skl_pipe *s_pipe = mconfig->pipe;
476 struct skl_module_cfg *src_module = NULL, *dst_module;
477 struct skl_sst *ctx = skl->skl_sst;
478
479 /* check resource available */
480 if (!skl_tplg_alloc_pipe_mcps(skl, mconfig))
481 return -EBUSY;
482
483 if (!skl_tplg_alloc_pipe_mem(skl, mconfig))
484 return -ENOMEM;
485
486 /*
487 * Create a list of modules for pipe.
488 * This list contains modules from source to sink
489 */
490 ret = skl_create_pipeline(ctx, mconfig->pipe);
491 if (ret < 0)
492 return ret;
493
494 /*
495 * we create a w_list of all widgets in that pipe. This list is not
496 * freed on PMD event as widgets within a pipe are static. This
497 * saves us cycles to get widgets in pipe every time.
498 *
499 * So if we have already initialized all the widgets of a pipeline
500 * we skip, so check for list_empty and create the list if empty
501 */
502 if (list_empty(&s_pipe->w_list)) {
503 ret = skl_tplg_alloc_pipe_widget(ctx->dev, w, s_pipe);
504 if (ret < 0)
505 return ret;
506 }
507
508 /* Init all pipe modules from source to sink */
509 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
510 if (ret < 0)
511 return ret;
512
513 /* Bind modules from source to sink */
514 list_for_each_entry(w_module, &s_pipe->w_list, node) {
515 dst_module = w_module->w->priv;
516
517 if (src_module == NULL) {
518 src_module = dst_module;
519 continue;
520 }
521
522 ret = skl_bind_modules(ctx, src_module, dst_module);
523 if (ret < 0)
524 return ret;
525
526 src_module = dst_module;
527 }
528
529 return 0;
530}
531
Jeeja KP8724ff12015-10-27 09:22:52 +0900532static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
533 struct skl *skl,
534 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100535{
536 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530537 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900538 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100539 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900540 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100541
Jeeja KP8724ff12015-10-27 09:22:52 +0900542 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100543 if (!p->connect)
544 continue;
545
546 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
547 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
548
Jeeja KP0ed95d72015-11-13 19:22:11 +0530549 next_sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100550 /*
551 * here we will check widgets in sink pipelines, so that
552 * can be any widgets type and we are only interested if
553 * they are ones used for SKL so check that first
554 */
555 if ((p->sink->priv != NULL) &&
556 is_skl_dsp_widget_type(p->sink)) {
557
558 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100559 sink_mconfig = sink->priv;
560
561 /* Bind source to sink, mixin is always source */
562 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
563 if (ret)
564 return ret;
565
566 /* Start sinks pipe first */
567 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900568 if (sink_mconfig->pipe->conn_type !=
569 SKL_PIPE_CONN_TYPE_FE)
570 ret = skl_run_pipe(ctx,
571 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100572 if (ret)
573 return ret;
574 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100575 }
576 }
577
Jeeja KP8724ff12015-10-27 09:22:52 +0900578 if (!sink)
Jeeja KP0ed95d72015-11-13 19:22:11 +0530579 return skl_tplg_bind_sinks(next_sink, skl, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900580
581 return 0;
582}
583
Vinod Kould93f8e52015-10-07 11:31:54 +0100584/*
585 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
586 * we need to do following:
587 * - Bind to sink pipeline
588 * Since the sink pipes can be running and we don't get mixer event on
589 * connect for already running mixer, we need to find the sink pipes
590 * here and bind to them. This way dynamic connect works.
591 * - Start sink pipeline, if not running
592 * - Then run current pipe
593 */
594static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900595 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100596{
Jeeja KP8724ff12015-10-27 09:22:52 +0900597 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100598 struct skl_sst *ctx = skl->skl_sst;
599 int ret = 0;
600
Jeeja KP8724ff12015-10-27 09:22:52 +0900601 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100602
603 /*
604 * find which sink it is connected to, bind with the sink,
605 * if sink is not started, start sink pipe first, then start
606 * this pipe
607 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900608 ret = skl_tplg_bind_sinks(w, skl, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100609 if (ret)
610 return ret;
611
Vinod Kould93f8e52015-10-07 11:31:54 +0100612 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900613 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
614 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100615
616 return 0;
617}
618
Jeeja KP8724ff12015-10-27 09:22:52 +0900619static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
620 struct snd_soc_dapm_widget *w, struct skl *skl)
621{
622 struct snd_soc_dapm_path *p;
623 struct snd_soc_dapm_widget *src_w = NULL;
624 struct skl_sst *ctx = skl->skl_sst;
625
626 snd_soc_dapm_widget_for_each_source_path(w, p) {
627 src_w = p->source;
628 if (!p->connect)
629 continue;
630
631 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
632 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
633
634 /*
635 * here we will check widgets in sink pipelines, so that can
636 * be any widgets type and we are only interested if they are
637 * ones used for SKL so check that first
638 */
639 if ((p->source->priv != NULL) &&
640 is_skl_dsp_widget_type(p->source)) {
641 return p->source;
642 }
643 }
644
645 if (src_w != NULL)
646 return skl_get_src_dsp_widget(src_w, skl);
647
648 return NULL;
649}
650
Vinod Kould93f8e52015-10-07 11:31:54 +0100651/*
652 * in the Post-PMU event of mixer we need to do following:
653 * - Check if this pipe is running
654 * - if not, then
655 * - bind this pipeline to its source pipeline
656 * if source pipe is already running, this means it is a dynamic
657 * connection and we need to bind only to that pipe
658 * - start this pipeline
659 */
660static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
661 struct skl *skl)
662{
663 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100664 struct snd_soc_dapm_widget *source, *sink;
665 struct skl_module_cfg *src_mconfig, *sink_mconfig;
666 struct skl_sst *ctx = skl->skl_sst;
667 int src_pipe_started = 0;
668
669 sink = w;
670 sink_mconfig = sink->priv;
671
672 /*
673 * If source pipe is already started, that means source is driving
674 * one more sink before this sink got connected, Since source is
675 * started, bind this sink to source and start this pipe.
676 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900677 source = skl_get_src_dsp_widget(w, skl);
678 if (source != NULL) {
679 src_mconfig = source->priv;
680 sink_mconfig = sink->priv;
681 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100682
683 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900684 * check pipe state, then no need to bind or start the
685 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100686 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900687 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
688 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100689 }
690
691 if (src_pipe_started) {
692 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
693 if (ret)
694 return ret;
695
Jeeja KPd1730c32015-10-27 09:22:53 +0900696 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
697 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100698 }
699
700 return ret;
701}
702
703/*
704 * in the Pre-PMD event of mixer we need to do following:
705 * - Stop the pipe
706 * - find the source connections and remove that from dapm_path_list
707 * - unbind with source pipelines if still connected
708 */
709static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
710 struct skl *skl)
711{
Vinod Kould93f8e52015-10-07 11:31:54 +0100712 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900713 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100714 struct skl_sst *ctx = skl->skl_sst;
715
Jeeja KPce1b5552015-10-27 09:22:51 +0900716 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100717
718 /* Stop the pipe */
719 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
720 if (ret)
721 return ret;
722
Jeeja KPce1b5552015-10-27 09:22:51 +0900723 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
724 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
725 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
726 if (!src_mconfig)
727 continue;
728 /*
729 * If path_found == 1, that means pmd for source
730 * pipe has not occurred, source is connected to
731 * some other sink. so its responsibility of sink
732 * to unbind itself from source.
733 */
734 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
735 if (ret < 0)
736 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100737
Jeeja KPce1b5552015-10-27 09:22:51 +0900738 ret = skl_unbind_modules(ctx,
739 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100740 }
741 }
742
Vinod Kould93f8e52015-10-07 11:31:54 +0100743 return ret;
744}
745
746/*
747 * in the Post-PMD event of mixer we need to do following:
748 * - Free the mcps used
749 * - Free the mem used
750 * - Unbind the modules within the pipeline
751 * - Delete the pipeline (modules are not required to be explicitly
752 * deleted, pipeline delete is enough here
753 */
754static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
755 struct skl *skl)
756{
757 struct skl_module_cfg *mconfig = w->priv;
758 struct skl_pipe_module *w_module;
759 struct skl_module_cfg *src_module = NULL, *dst_module;
760 struct skl_sst *ctx = skl->skl_sst;
761 struct skl_pipe *s_pipe = mconfig->pipe;
762 int ret = 0;
763
764 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +0530765 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100766
767 list_for_each_entry(w_module, &s_pipe->w_list, node) {
768 dst_module = w_module->w->priv;
769
Vinod Koul7ae3cb12015-11-05 21:34:10 +0530770 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100771 if (src_module == NULL) {
772 src_module = dst_module;
773 continue;
774 }
775
776 ret = skl_unbind_modules(ctx, src_module, dst_module);
777 if (ret < 0)
778 return ret;
779
780 src_module = dst_module;
781 }
782
783 ret = skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100784
Dharageswari R6c5768b2015-12-03 23:29:50 +0530785 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100786}
787
788/*
789 * in the Post-PMD event of PGA we need to do following:
790 * - Free the mcps used
791 * - Stop the pipeline
792 * - In source pipe is connected, unbind with source pipelines
793 */
794static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
795 struct skl *skl)
796{
Vinod Kould93f8e52015-10-07 11:31:54 +0100797 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900798 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100799 struct skl_sst *ctx = skl->skl_sst;
800
Jeeja KPce1b5552015-10-27 09:22:51 +0900801 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100802
Vinod Kould93f8e52015-10-07 11:31:54 +0100803 /* Stop the pipe since this is a mixin module */
804 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
805 if (ret)
806 return ret;
807
Jeeja KPce1b5552015-10-27 09:22:51 +0900808 for (i = 0; i < src_mconfig->max_out_queue; i++) {
809 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
810 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
811 if (!sink_mconfig)
812 continue;
813 /*
814 * This is a connecter and if path is found that means
815 * unbind between source and sink has not happened yet
816 */
817 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
818 if (ret < 0)
819 return ret;
820 ret = skl_unbind_modules(ctx, src_mconfig,
821 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100822 }
823 }
824
Vinod Kould93f8e52015-10-07 11:31:54 +0100825 return ret;
826}
827
828/*
829 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
830 * mixer is not required then it is treated as static mixer aka vmixer with
831 * a hard path to source module
832 * So we don't need to check if source is started or not as hard path puts
833 * dependency on each other
834 */
835static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
836 struct snd_kcontrol *k, int event)
837{
838 struct snd_soc_dapm_context *dapm = w->dapm;
839 struct skl *skl = get_skl_ctx(dapm->dev);
840
841 switch (event) {
842 case SND_SOC_DAPM_PRE_PMU:
843 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
844
845 case SND_SOC_DAPM_POST_PMD:
846 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
847 }
848
849 return 0;
850}
851
852/*
853 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
854 * second one is required that is created as another pipe entity.
855 * The mixer is responsible for pipe management and represent a pipeline
856 * instance
857 */
858static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
859 struct snd_kcontrol *k, int event)
860{
861 struct snd_soc_dapm_context *dapm = w->dapm;
862 struct skl *skl = get_skl_ctx(dapm->dev);
863
864 switch (event) {
865 case SND_SOC_DAPM_PRE_PMU:
866 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
867
868 case SND_SOC_DAPM_POST_PMU:
869 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
870
871 case SND_SOC_DAPM_PRE_PMD:
872 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
873
874 case SND_SOC_DAPM_POST_PMD:
875 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
876 }
877
878 return 0;
879}
880
881/*
882 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
883 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
884 * the sink when it is running (two FE to one BE or one FE to two BE)
885 * scenarios
886 */
887static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
888 struct snd_kcontrol *k, int event)
889
890{
891 struct snd_soc_dapm_context *dapm = w->dapm;
892 struct skl *skl = get_skl_ctx(dapm->dev);
893
894 switch (event) {
895 case SND_SOC_DAPM_PRE_PMU:
896 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
897
898 case SND_SOC_DAPM_POST_PMD:
899 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
900 }
901
902 return 0;
903}
Vinod Koulcfb0a872015-10-07 11:31:55 +0100904
Jeeja KP140adfb2015-11-28 15:01:50 +0530905static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
906 unsigned int __user *data, unsigned int size)
907{
908 struct soc_bytes_ext *sb =
909 (struct soc_bytes_ext *)kcontrol->private_value;
910 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +0530911 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
912 struct skl_module_cfg *mconfig = w->priv;
913 struct skl *skl = get_skl_ctx(w->dapm->dev);
914
915 if (w->power)
916 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
917 bc->max, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +0530918
Vinod Koul41556f62016-02-03 17:59:44 +0530919 /* decrement size for TLV header */
920 size -= 2 * sizeof(u32);
921
922 /* check size as we don't want to send kernel data */
923 if (size > bc->max)
924 size = bc->max;
925
Jeeja KP140adfb2015-11-28 15:01:50 +0530926 if (bc->params) {
927 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
928 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +0300929 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +0530930 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +0300931 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +0530932 return -EFAULT;
933 }
934
935 return 0;
936}
937
938#define SKL_PARAM_VENDOR_ID 0xff
939
940static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
941 const unsigned int __user *data, unsigned int size)
942{
943 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
944 struct skl_module_cfg *mconfig = w->priv;
945 struct soc_bytes_ext *sb =
946 (struct soc_bytes_ext *)kcontrol->private_value;
947 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
948 struct skl *skl = get_skl_ctx(w->dapm->dev);
949
950 if (ac->params) {
951 /*
952 * if the param_is is of type Vendor, firmware expects actual
953 * parameter id and size from the control.
954 */
955 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
956 if (copy_from_user(ac->params, data, size))
957 return -EFAULT;
958 } else {
959 if (copy_from_user(ac->params,
960 data + 2 * sizeof(u32), size))
961 return -EFAULT;
962 }
963
964 if (w->power)
965 return skl_set_module_params(skl->skl_sst,
966 (u32 *)ac->params, ac->max,
967 ac->param_id, mconfig);
968 }
969
970 return 0;
971}
972
Vinod Koulcfb0a872015-10-07 11:31:55 +0100973/*
974 * The FE params are passed by hw_params of the DAI.
975 * On hw_params, the params are stored in Gateway module of the FE and we
976 * need to calculate the format in DSP module configuration, that
977 * conversion is done here
978 */
979int skl_tplg_update_pipe_params(struct device *dev,
980 struct skl_module_cfg *mconfig,
981 struct skl_pipe_params *params)
982{
983 struct skl_pipe *pipe = mconfig->pipe;
984 struct skl_module_fmt *format = NULL;
985
986 memcpy(pipe->p_params, params, sizeof(*params));
987
988 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +0900989 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +0100990 else
Hardik T Shah4cd98992015-10-27 09:22:55 +0900991 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +0100992
993 /* set the hw_params */
994 format->s_freq = params->s_freq;
995 format->channels = params->ch;
996 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
997
998 /*
999 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1000 * container so update bit depth accordingly
1001 */
1002 switch (format->valid_bit_depth) {
1003 case SKL_DEPTH_16BIT:
1004 format->bit_depth = format->valid_bit_depth;
1005 break;
1006
1007 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001008 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001009 format->bit_depth = SKL_DEPTH_32BIT;
1010 break;
1011
1012 default:
1013 dev_err(dev, "Invalid bit depth %x for pipe\n",
1014 format->valid_bit_depth);
1015 return -EINVAL;
1016 }
1017
1018 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1019 mconfig->ibs = (format->s_freq / 1000) *
1020 (format->channels) *
1021 (format->bit_depth >> 3);
1022 } else {
1023 mconfig->obs = (format->s_freq / 1000) *
1024 (format->channels) *
1025 (format->bit_depth >> 3);
1026 }
1027
1028 return 0;
1029}
1030
1031/*
1032 * Query the module config for the FE DAI
1033 * This is used to find the hw_params set for that DAI and apply to FE
1034 * pipeline
1035 */
1036struct skl_module_cfg *
1037skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1038{
1039 struct snd_soc_dapm_widget *w;
1040 struct snd_soc_dapm_path *p = NULL;
1041
1042 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1043 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301044 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001045 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001046 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001047 continue;
1048
1049 if (p->sink->priv) {
1050 dev_dbg(dai->dev, "set params for %s\n",
1051 p->sink->name);
1052 return p->sink->priv;
1053 }
1054 }
1055 } else {
1056 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301057 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001058 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001059 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001060 continue;
1061
1062 if (p->source->priv) {
1063 dev_dbg(dai->dev, "set params for %s\n",
1064 p->source->name);
1065 return p->source->priv;
1066 }
1067 }
1068 }
1069
1070 return NULL;
1071}
1072
1073static u8 skl_tplg_be_link_type(int dev_type)
1074{
1075 int ret;
1076
1077 switch (dev_type) {
1078 case SKL_DEVICE_BT:
1079 ret = NHLT_LINK_SSP;
1080 break;
1081
1082 case SKL_DEVICE_DMIC:
1083 ret = NHLT_LINK_DMIC;
1084 break;
1085
1086 case SKL_DEVICE_I2S:
1087 ret = NHLT_LINK_SSP;
1088 break;
1089
1090 case SKL_DEVICE_HDALINK:
1091 ret = NHLT_LINK_HDA;
1092 break;
1093
1094 default:
1095 ret = NHLT_LINK_INVALID;
1096 break;
1097 }
1098
1099 return ret;
1100}
1101
1102/*
1103 * Fill the BE gateway parameters
1104 * The BE gateway expects a blob of parameters which are kept in the ACPI
1105 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1106 * The port can have multiple settings so pick based on the PCM
1107 * parameters
1108 */
1109static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1110 struct skl_module_cfg *mconfig,
1111 struct skl_pipe_params *params)
1112{
1113 struct skl_pipe *pipe = mconfig->pipe;
1114 struct nhlt_specific_cfg *cfg;
1115 struct skl *skl = get_skl_ctx(dai->dev);
1116 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
1117
1118 memcpy(pipe->p_params, params, sizeof(*params));
1119
Jeeja KPb30c2752015-10-27 09:22:48 +09001120 if (link_type == NHLT_LINK_HDA)
1121 return 0;
1122
Vinod Koulcfb0a872015-10-07 11:31:55 +01001123 /* update the blob based on virtual bus_id*/
1124 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1125 params->s_fmt, params->ch,
1126 params->s_freq, params->stream);
1127 if (cfg) {
1128 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301129 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001130 } else {
1131 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1132 mconfig->vbus_id, link_type,
1133 params->stream);
1134 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1135 params->ch, params->s_freq, params->s_fmt);
1136 return -EINVAL;
1137 }
1138
1139 return 0;
1140}
1141
1142static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1143 struct snd_soc_dapm_widget *w,
1144 struct skl_pipe_params *params)
1145{
1146 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301147 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001148
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301149 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001150 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1151 p->source->priv) {
1152
Jeeja KP9a03cb42015-10-27 09:22:54 +09001153 ret = skl_tplg_be_fill_pipe_params(dai,
1154 p->source->priv, params);
1155 if (ret < 0)
1156 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001157 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001158 ret = skl_tplg_be_set_src_pipe_params(dai,
1159 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301160 if (ret < 0)
1161 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001162 }
1163 }
1164
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301165 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001166}
1167
1168static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1169 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1170{
1171 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301172 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001173
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301174 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001175 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1176 p->sink->priv) {
1177
Jeeja KP9a03cb42015-10-27 09:22:54 +09001178 ret = skl_tplg_be_fill_pipe_params(dai,
1179 p->sink->priv, params);
1180 if (ret < 0)
1181 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001182 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301183 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001184 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301185 if (ret < 0)
1186 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001187 }
1188 }
1189
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301190 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001191}
1192
1193/*
1194 * BE hw_params can be a source parameters (capture) or sink parameters
1195 * (playback). Based on sink and source we need to either find the source
1196 * list or the sink list and set the pipeline parameters
1197 */
1198int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1199 struct skl_pipe_params *params)
1200{
1201 struct snd_soc_dapm_widget *w;
1202
1203 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1204 w = dai->playback_widget;
1205
1206 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1207
1208 } else {
1209 w = dai->capture_widget;
1210
1211 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1212 }
1213
1214 return 0;
1215}
Vinod Koul3af36702015-10-07 11:31:56 +01001216
1217static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1218 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1219 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1220 {SKL_PGA_EVENT, skl_tplg_pga_event},
1221};
1222
Jeeja KP140adfb2015-11-28 15:01:50 +05301223static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1224 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1225 skl_tplg_tlv_control_set},
1226};
1227
Vinod Koul3af36702015-10-07 11:31:56 +01001228/*
1229 * The topology binary passes the pin info for a module so initialize the pin
1230 * info passed into module instance
1231 */
Jeeja KP6abca1d2015-10-22 23:22:42 +05301232static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin,
1233 struct skl_module_pin *m_pin,
1234 bool is_dynamic, int max_pin)
Vinod Koul3af36702015-10-07 11:31:56 +01001235{
1236 int i;
1237
1238 for (i = 0; i < max_pin; i++) {
Jeeja KP6abca1d2015-10-22 23:22:42 +05301239 m_pin[i].id.module_id = dfw_pin[i].module_id;
1240 m_pin[i].id.instance_id = dfw_pin[i].instance_id;
Vinod Koul3af36702015-10-07 11:31:56 +01001241 m_pin[i].in_use = false;
Jeeja KP6abca1d2015-10-22 23:22:42 +05301242 m_pin[i].is_dynamic = is_dynamic;
Jeeja KP4f745702015-10-27 09:22:49 +09001243 m_pin[i].pin_state = SKL_PIN_UNBIND;
Vinod Koul3af36702015-10-07 11:31:56 +01001244 }
1245}
1246
1247/*
1248 * Add pipeline from topology binary into driver pipeline list
1249 *
1250 * If already added we return that instance
1251 * Otherwise we create a new instance and add into driver list
1252 */
1253static struct skl_pipe *skl_tplg_add_pipe(struct device *dev,
1254 struct skl *skl, struct skl_dfw_pipe *dfw_pipe)
1255{
1256 struct skl_pipeline *ppl;
1257 struct skl_pipe *pipe;
1258 struct skl_pipe_params *params;
1259
1260 list_for_each_entry(ppl, &skl->ppl_list, node) {
1261 if (ppl->pipe->ppl_id == dfw_pipe->pipe_id)
1262 return ppl->pipe;
1263 }
1264
1265 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1266 if (!ppl)
1267 return NULL;
1268
1269 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1270 if (!pipe)
1271 return NULL;
1272
1273 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1274 if (!params)
1275 return NULL;
1276
1277 pipe->ppl_id = dfw_pipe->pipe_id;
1278 pipe->memory_pages = dfw_pipe->memory_pages;
1279 pipe->pipe_priority = dfw_pipe->pipe_priority;
1280 pipe->conn_type = dfw_pipe->conn_type;
1281 pipe->state = SKL_PIPE_INVALID;
1282 pipe->p_params = params;
1283 INIT_LIST_HEAD(&pipe->w_list);
1284
1285 ppl->pipe = pipe;
1286 list_add(&ppl->node, &skl->ppl_list);
1287
1288 return ppl->pipe;
1289}
1290
Hardik T Shah4cd98992015-10-27 09:22:55 +09001291static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt,
1292 struct skl_dfw_module_fmt *src_fmt,
1293 int pins)
1294{
1295 int i;
1296
1297 for (i = 0; i < pins; i++) {
1298 dst_fmt[i].channels = src_fmt[i].channels;
1299 dst_fmt[i].s_freq = src_fmt[i].freq;
1300 dst_fmt[i].bit_depth = src_fmt[i].bit_depth;
1301 dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth;
1302 dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg;
1303 dst_fmt[i].ch_map = src_fmt[i].ch_map;
1304 dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style;
1305 dst_fmt[i].sample_type = src_fmt[i].sample_type;
1306 }
1307}
1308
Vinod Koul3af36702015-10-07 11:31:56 +01001309/*
1310 * Topology core widget load callback
1311 *
1312 * This is used to save the private data for each widget which gives
1313 * information to the driver about module and pipeline parameters which DSP
1314 * FW expects like ids, resource values, formats etc
1315 */
1316static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001317 struct snd_soc_dapm_widget *w,
1318 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01001319{
1320 int ret;
1321 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1322 struct skl *skl = ebus_to_skl(ebus);
1323 struct hdac_bus *bus = ebus_to_hbus(ebus);
1324 struct skl_module_cfg *mconfig;
1325 struct skl_pipe *pipe;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001326 struct skl_dfw_module *dfw_config =
1327 (struct skl_dfw_module *)tplg_w->priv.data;
Vinod Koul3af36702015-10-07 11:31:56 +01001328
1329 if (!tplg_w->priv.size)
1330 goto bind_event;
1331
1332 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
1333
1334 if (!mconfig)
1335 return -ENOMEM;
1336
1337 w->priv = mconfig;
1338 mconfig->id.module_id = dfw_config->module_id;
1339 mconfig->id.instance_id = dfw_config->instance_id;
1340 mconfig->mcps = dfw_config->max_mcps;
1341 mconfig->ibs = dfw_config->ibs;
1342 mconfig->obs = dfw_config->obs;
1343 mconfig->core_id = dfw_config->core_id;
1344 mconfig->max_in_queue = dfw_config->max_in_queue;
1345 mconfig->max_out_queue = dfw_config->max_out_queue;
1346 mconfig->is_loadable = dfw_config->is_loadable;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001347 skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt,
1348 MODULE_MAX_IN_PINS);
1349 skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt,
1350 MODULE_MAX_OUT_PINS);
1351
Vinod Koul3af36702015-10-07 11:31:56 +01001352 mconfig->params_fixup = dfw_config->params_fixup;
1353 mconfig->converter = dfw_config->converter;
1354 mconfig->m_type = dfw_config->module_type;
1355 mconfig->vbus_id = dfw_config->vbus_id;
Jeeja KPb18c4582015-12-03 23:29:51 +05301356 mconfig->mem_pages = dfw_config->mem_pages;
Vinod Koul3af36702015-10-07 11:31:56 +01001357
1358 pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe);
1359 if (pipe)
1360 mconfig->pipe = pipe;
1361
1362 mconfig->dev_type = dfw_config->dev_type;
1363 mconfig->hw_conn_type = dfw_config->hw_conn_type;
1364 mconfig->time_slot = dfw_config->time_slot;
1365 mconfig->formats_config.caps_size = dfw_config->caps.caps_size;
1366
Hardik T Shah65aecfa2015-10-27 09:22:57 +09001367 if (dfw_config->is_loadable)
1368 memcpy(mconfig->guid, dfw_config->uuid,
1369 ARRAY_SIZE(dfw_config->uuid));
1370
Hardik T Shah4cd98992015-10-27 09:22:55 +09001371 mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) *
1372 sizeof(*mconfig->m_in_pin),
1373 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001374 if (!mconfig->m_in_pin)
1375 return -ENOMEM;
1376
Jeeja KP6abca1d2015-10-22 23:22:42 +05301377 mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) *
1378 sizeof(*mconfig->m_out_pin),
1379 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001380 if (!mconfig->m_out_pin)
1381 return -ENOMEM;
1382
Jeeja KP6abca1d2015-10-22 23:22:42 +05301383 skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin,
1384 dfw_config->is_dynamic_in_pin,
1385 mconfig->max_in_queue);
1386
1387 skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin,
1388 dfw_config->is_dynamic_out_pin,
1389 mconfig->max_out_queue);
1390
Vinod Koul3af36702015-10-07 11:31:56 +01001391
1392 if (mconfig->formats_config.caps_size == 0)
1393 goto bind_event;
1394
1395 mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001396 mconfig->formats_config.caps_size, GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001397
1398 if (mconfig->formats_config.caps == NULL)
1399 return -ENOMEM;
1400
1401 memcpy(mconfig->formats_config.caps, dfw_config->caps.caps,
Jeeja KPabb74002015-11-28 15:01:49 +05301402 dfw_config->caps.caps_size);
1403 mconfig->formats_config.param_id = dfw_config->caps.param_id;
1404 mconfig->formats_config.set_params = dfw_config->caps.set_params;
Vinod Koul3af36702015-10-07 11:31:56 +01001405
1406bind_event:
1407 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01001408 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01001409 return 0;
1410 }
1411
1412 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001413 ARRAY_SIZE(skl_tplg_widget_ops),
1414 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01001415
1416 if (ret) {
1417 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
1418 __func__, tplg_w->event_type);
1419 return -EINVAL;
1420 }
1421
1422 return 0;
1423}
1424
Jeeja KP140adfb2015-11-28 15:01:50 +05301425static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
1426 struct snd_soc_tplg_bytes_control *bc)
1427{
1428 struct skl_algo_data *ac;
1429 struct skl_dfw_algo_data *dfw_ac =
1430 (struct skl_dfw_algo_data *)bc->priv.data;
1431
1432 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
1433 if (!ac)
1434 return -ENOMEM;
1435
1436 /* Fill private data */
1437 ac->max = dfw_ac->max;
1438 ac->param_id = dfw_ac->param_id;
1439 ac->set_params = dfw_ac->set_params;
1440
1441 if (ac->max) {
1442 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
1443 if (!ac->params)
1444 return -ENOMEM;
1445
1446 if (dfw_ac->params)
1447 memcpy(ac->params, dfw_ac->params, ac->max);
1448 }
1449
1450 be->dobj.private = ac;
1451 return 0;
1452}
1453
1454static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
1455 struct snd_kcontrol_new *kctl,
1456 struct snd_soc_tplg_ctl_hdr *hdr)
1457{
1458 struct soc_bytes_ext *sb;
1459 struct snd_soc_tplg_bytes_control *tplg_bc;
1460 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1461 struct hdac_bus *bus = ebus_to_hbus(ebus);
1462
1463 switch (hdr->ops.info) {
1464 case SND_SOC_TPLG_CTL_BYTES:
1465 tplg_bc = container_of(hdr,
1466 struct snd_soc_tplg_bytes_control, hdr);
1467 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1468 sb = (struct soc_bytes_ext *)kctl->private_value;
1469 if (tplg_bc->priv.size)
1470 return skl_init_algo_data(
1471 bus->dev, sb, tplg_bc);
1472 }
1473 break;
1474
1475 default:
1476 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
1477 hdr->ops.get, hdr->ops.put, hdr->ops.info);
1478 break;
1479 }
1480
1481 return 0;
1482}
1483
Vinod Koul3af36702015-10-07 11:31:56 +01001484static struct snd_soc_tplg_ops skl_tplg_ops = {
1485 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05301486 .control_load = skl_tplg_control_load,
1487 .bytes_ext_ops = skl_tlv_ops,
1488 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Vinod Koul3af36702015-10-07 11:31:56 +01001489};
1490
1491/* This will be read from topology manifest, currently defined here */
1492#define SKL_MAX_MCPS 30000000
1493#define SKL_FW_MAX_MEM 1000000
1494
1495/*
1496 * SKL topology init routine
1497 */
1498int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
1499{
1500 int ret;
1501 const struct firmware *fw;
1502 struct hdac_bus *bus = ebus_to_hbus(ebus);
1503 struct skl *skl = ebus_to_skl(ebus);
1504
1505 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
1506 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001507 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul3af36702015-10-07 11:31:56 +01001508 "dfw_sst.bin", ret);
1509 return ret;
1510 }
1511
1512 /*
1513 * The complete tplg for SKL is loaded as index 0, we don't use
1514 * any other index
1515 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01001516 ret = snd_soc_tplg_component_load(&platform->component,
1517 &skl_tplg_ops, fw, 0);
Sudip Mukherjee87b5ed82015-11-23 16:38:48 +05301518 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01001519 if (ret < 0) {
1520 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05301521 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01001522 return -EINVAL;
1523 }
1524
1525 skl->resource.max_mcps = SKL_MAX_MCPS;
1526 skl->resource.max_mem = SKL_FW_MAX_MEM;
1527
1528 return 0;
1529}