blob: c2012184607355c7043651a8bf039da4d2cce853 [file] [log] [blame]
Shawn Guo0a886f52016-09-22 19:52:39 +08001/*
2 * Copyright 2016 Linaro Ltd.
3 * Copyright 2016 ZTE Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/clk.h>
12#include <linux/component.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/hdmi.h>
16#include <linux/irq.h>
17#include <linux/mfd/syscon.h>
18#include <linux/module.h>
19#include <linux/mutex.h>
20#include <linux/of_device.h>
21
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_crtc_helper.h>
24#include <drm/drm_edid.h>
25#include <drm/drm_of.h>
26#include <drm/drmP.h>
27
Shawn Guo83d71152016-12-01 17:20:31 +080028#include <sound/hdmi-codec.h>
29
Shawn Guo0a886f52016-09-22 19:52:39 +080030#include "zx_hdmi_regs.h"
31#include "zx_vou.h"
32
33#define ZX_HDMI_INFOFRAME_SIZE 31
34#define DDC_SEGMENT_ADDR 0x30
35
36struct zx_hdmi_i2c {
37 struct i2c_adapter adap;
38 struct mutex lock;
39};
40
41struct zx_hdmi {
42 struct drm_connector connector;
43 struct drm_encoder encoder;
44 struct zx_hdmi_i2c *ddc;
45 struct device *dev;
46 struct drm_device *drm;
47 void __iomem *mmio;
48 struct clk *cec_clk;
49 struct clk *osc_clk;
50 struct clk *xclk;
51 bool sink_is_hdmi;
52 bool sink_has_audio;
53 const struct vou_inf *inf;
Shawn Guo83d71152016-12-01 17:20:31 +080054 struct platform_device *audio_pdev;
Shawn Guo0a886f52016-09-22 19:52:39 +080055};
56
57#define to_zx_hdmi(x) container_of(x, struct zx_hdmi, x)
58
59static const struct vou_inf vou_inf_hdmi = {
60 .id = VOU_HDMI,
61 .data_sel = VOU_YUV444,
62 .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
63 .clocks_sel_bits = BIT(13) | BIT(2),
64};
65
66static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset)
67{
68 return readl_relaxed(hdmi->mmio + offset * 4);
69}
70
71static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val)
72{
73 writel_relaxed(val, hdmi->mmio + offset * 4);
74}
75
76static inline void hdmi_writeb_mask(struct zx_hdmi *hdmi, u16 offset,
77 u8 mask, u8 val)
78{
79 u8 tmp;
80
81 tmp = hdmi_readb(hdmi, offset);
82 tmp = (tmp & ~mask) | (val & mask);
83 hdmi_writeb(hdmi, offset, tmp);
84}
85
86static int zx_hdmi_infoframe_trans(struct zx_hdmi *hdmi,
87 union hdmi_infoframe *frame, u8 fsel)
88{
89 u8 buffer[ZX_HDMI_INFOFRAME_SIZE];
90 int num;
91 int i;
92
93 hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel);
94
95 num = hdmi_infoframe_pack(frame, buffer, ZX_HDMI_INFOFRAME_SIZE);
96 if (num < 0) {
97 DRM_DEV_ERROR(hdmi->dev, "failed to pack infoframe: %d\n", num);
98 return num;
99 }
100
101 for (i = 0; i < num; i++)
102 hdmi_writeb(hdmi, TPI_INFO_B0 + i, buffer[i]);
103
104 hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_RPT,
105 TPI_INFO_TRANS_RPT);
106 hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_EN,
107 TPI_INFO_TRANS_EN);
108
109 return num;
110}
111
112static int zx_hdmi_config_video_vsi(struct zx_hdmi *hdmi,
113 struct drm_display_mode *mode)
114{
115 union hdmi_infoframe frame;
116 int ret;
117
118 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
119 mode);
120 if (ret) {
121 DRM_DEV_ERROR(hdmi->dev, "failed to get vendor infoframe: %d\n",
122 ret);
123 return ret;
124 }
125
126 return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_VSIF);
127}
128
129static int zx_hdmi_config_video_avi(struct zx_hdmi *hdmi,
130 struct drm_display_mode *mode)
131{
132 union hdmi_infoframe frame;
133 int ret;
134
135 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
136 if (ret) {
137 DRM_DEV_ERROR(hdmi->dev, "failed to get avi infoframe: %d\n",
138 ret);
139 return ret;
140 }
141
142 /* We always use YUV444 for HDMI output. */
143 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
144
145 return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AVI);
146}
147
148static void zx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
149 struct drm_display_mode *mode,
150 struct drm_display_mode *adj_mode)
151{
152 struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
153
154 if (hdmi->sink_is_hdmi) {
155 zx_hdmi_config_video_avi(hdmi, mode);
156 zx_hdmi_config_video_vsi(hdmi, mode);
157 }
158}
159
160static void zx_hdmi_phy_start(struct zx_hdmi *hdmi)
161{
162 /* Copy from ZTE BSP code */
163 hdmi_writeb(hdmi, 0x222, 0x0);
164 hdmi_writeb(hdmi, 0x224, 0x4);
165 hdmi_writeb(hdmi, 0x909, 0x0);
166 hdmi_writeb(hdmi, 0x7b0, 0x90);
167 hdmi_writeb(hdmi, 0x7b1, 0x00);
168 hdmi_writeb(hdmi, 0x7b2, 0xa7);
169 hdmi_writeb(hdmi, 0x7b8, 0xaa);
170 hdmi_writeb(hdmi, 0x7b2, 0xa7);
171 hdmi_writeb(hdmi, 0x7b3, 0x0f);
172 hdmi_writeb(hdmi, 0x7b4, 0x0f);
173 hdmi_writeb(hdmi, 0x7b5, 0x55);
174 hdmi_writeb(hdmi, 0x7b7, 0x03);
175 hdmi_writeb(hdmi, 0x7b9, 0x12);
176 hdmi_writeb(hdmi, 0x7ba, 0x32);
177 hdmi_writeb(hdmi, 0x7bc, 0x68);
178 hdmi_writeb(hdmi, 0x7be, 0x40);
179 hdmi_writeb(hdmi, 0x7bf, 0x84);
180 hdmi_writeb(hdmi, 0x7c1, 0x0f);
181 hdmi_writeb(hdmi, 0x7c8, 0x02);
182 hdmi_writeb(hdmi, 0x7c9, 0x03);
183 hdmi_writeb(hdmi, 0x7ca, 0x40);
184 hdmi_writeb(hdmi, 0x7dc, 0x31);
185 hdmi_writeb(hdmi, 0x7e2, 0x04);
186 hdmi_writeb(hdmi, 0x7e0, 0x06);
187 hdmi_writeb(hdmi, 0x7cb, 0x68);
188 hdmi_writeb(hdmi, 0x7f9, 0x02);
189 hdmi_writeb(hdmi, 0x7b6, 0x02);
190 hdmi_writeb(hdmi, 0x7f3, 0x0);
191}
192
193static void zx_hdmi_hw_enable(struct zx_hdmi *hdmi)
194{
195 /* Enable pclk */
196 hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, CLKPWD_PDIDCK);
197
198 /* Enable HDMI for TX */
199 hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, FUNC_HDMI_EN);
200
201 /* Enable deep color packet */
202 hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
203
204 /* Enable HDMI/MHL mode for output */
205 hdmi_writeb_mask(hdmi, TEST_TXCTRL, TEST_TXCTRL_HDMI_MODE,
206 TEST_TXCTRL_HDMI_MODE);
207
208 /* Configure reg_qc_sel */
209 hdmi_writeb(hdmi, HDMICTL4, 0x3);
210
211 /* Enable interrupt */
212 hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT,
213 INTR1_MONITOR_DETECT);
214
215 /* Start up phy */
216 zx_hdmi_phy_start(hdmi);
217}
218
219static void zx_hdmi_hw_disable(struct zx_hdmi *hdmi)
220{
221 /* Disable interrupt */
222 hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT, 0);
223
224 /* Disable deep color packet */
225 hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
226
227 /* Disable HDMI for TX */
228 hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, 0);
229
230 /* Disable pclk */
231 hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, 0);
232}
233
234static void zx_hdmi_encoder_enable(struct drm_encoder *encoder)
235{
236 struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
237
238 clk_prepare_enable(hdmi->cec_clk);
239 clk_prepare_enable(hdmi->osc_clk);
240 clk_prepare_enable(hdmi->xclk);
241
242 zx_hdmi_hw_enable(hdmi);
243
244 vou_inf_enable(hdmi->inf, encoder->crtc);
245}
246
247static void zx_hdmi_encoder_disable(struct drm_encoder *encoder)
248{
249 struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
250
251 vou_inf_disable(hdmi->inf, encoder->crtc);
252
253 zx_hdmi_hw_disable(hdmi);
254
255 clk_disable_unprepare(hdmi->xclk);
256 clk_disable_unprepare(hdmi->osc_clk);
257 clk_disable_unprepare(hdmi->cec_clk);
258}
259
260static const struct drm_encoder_helper_funcs zx_hdmi_encoder_helper_funcs = {
261 .enable = zx_hdmi_encoder_enable,
262 .disable = zx_hdmi_encoder_disable,
263 .mode_set = zx_hdmi_encoder_mode_set,
264};
265
266static const struct drm_encoder_funcs zx_hdmi_encoder_funcs = {
267 .destroy = drm_encoder_cleanup,
268};
269
270static int zx_hdmi_connector_get_modes(struct drm_connector *connector)
271{
272 struct zx_hdmi *hdmi = to_zx_hdmi(connector);
273 struct edid *edid;
274 int ret;
275
276 edid = drm_get_edid(connector, &hdmi->ddc->adap);
277 if (!edid)
278 return 0;
279
280 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
281 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
282 drm_mode_connector_update_edid_property(connector, edid);
283 ret = drm_add_edid_modes(connector, edid);
284 kfree(edid);
285
286 return ret;
287}
288
289static enum drm_mode_status
290zx_hdmi_connector_mode_valid(struct drm_connector *connector,
291 struct drm_display_mode *mode)
292{
293 return MODE_OK;
294}
295
296static struct drm_connector_helper_funcs zx_hdmi_connector_helper_funcs = {
297 .get_modes = zx_hdmi_connector_get_modes,
298 .mode_valid = zx_hdmi_connector_mode_valid,
299};
300
301static enum drm_connector_status
302zx_hdmi_connector_detect(struct drm_connector *connector, bool force)
303{
304 struct zx_hdmi *hdmi = to_zx_hdmi(connector);
305
306 return (hdmi_readb(hdmi, TPI_HPD_RSEN) & TPI_HPD_CONNECTION) ?
307 connector_status_connected : connector_status_disconnected;
308}
309
310static const struct drm_connector_funcs zx_hdmi_connector_funcs = {
311 .dpms = drm_atomic_helper_connector_dpms,
312 .fill_modes = drm_helper_probe_single_connector_modes,
313 .detect = zx_hdmi_connector_detect,
314 .destroy = drm_connector_cleanup,
315 .reset = drm_atomic_helper_connector_reset,
316 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
317 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
318};
319
320static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi)
321{
322 struct drm_encoder *encoder = &hdmi->encoder;
323
324 encoder->possible_crtcs = VOU_CRTC_MASK;
325
326 drm_encoder_init(drm, encoder, &zx_hdmi_encoder_funcs,
327 DRM_MODE_ENCODER_TMDS, NULL);
328 drm_encoder_helper_add(encoder, &zx_hdmi_encoder_helper_funcs);
329
330 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
331
332 drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs,
333 DRM_MODE_CONNECTOR_HDMIA);
334 drm_connector_helper_add(&hdmi->connector,
335 &zx_hdmi_connector_helper_funcs);
336
337 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
338
339 return 0;
340}
341
342static irqreturn_t zx_hdmi_irq_thread(int irq, void *dev_id)
343{
344 struct zx_hdmi *hdmi = dev_id;
345
346 drm_helper_hpd_irq_event(hdmi->connector.dev);
347
348 return IRQ_HANDLED;
349}
350
351static irqreturn_t zx_hdmi_irq_handler(int irq, void *dev_id)
352{
353 struct zx_hdmi *hdmi = dev_id;
354 u8 lstat;
355
356 lstat = hdmi_readb(hdmi, L1_INTR_STAT);
357
358 /* Monitor detect/HPD interrupt */
359 if (lstat & L1_INTR_STAT_INTR1) {
360 u8 stat;
361
362 stat = hdmi_readb(hdmi, INTR1_STAT);
363 hdmi_writeb(hdmi, INTR1_STAT, stat);
364
365 if (stat & INTR1_MONITOR_DETECT)
366 return IRQ_WAKE_THREAD;
367 }
368
369 return IRQ_NONE;
370}
371
Shawn Guo83d71152016-12-01 17:20:31 +0800372static int zx_hdmi_audio_startup(struct device *dev, void *data)
373{
374 struct zx_hdmi *hdmi = dev_get_drvdata(dev);
375 struct drm_encoder *encoder = &hdmi->encoder;
376
377 vou_inf_hdmi_audio_sel(encoder->crtc, VOU_HDMI_AUD_SPDIF);
378
379 return 0;
380}
381
382static void zx_hdmi_audio_shutdown(struct device *dev, void *data)
383{
384 struct zx_hdmi *hdmi = dev_get_drvdata(dev);
385
386 /* Disable audio input */
387 hdmi_writeb_mask(hdmi, AUD_EN, AUD_IN_EN, 0);
388}
389
390static inline int zx_hdmi_audio_get_n(unsigned int fs)
391{
392 unsigned int n;
393
394 if (fs && (fs % 44100) == 0)
395 n = 6272 * (fs / 44100);
396 else
397 n = fs * 128 / 1000;
398
399 return n;
400}
401
402static int zx_hdmi_audio_hw_params(struct device *dev,
403 void *data,
404 struct hdmi_codec_daifmt *daifmt,
405 struct hdmi_codec_params *params)
406{
407 struct zx_hdmi *hdmi = dev_get_drvdata(dev);
408 struct hdmi_audio_infoframe *cea = &params->cea;
409 union hdmi_infoframe frame;
410 int n;
411
412 /* We only support spdif for now */
413 if (daifmt->fmt != HDMI_SPDIF) {
414 DRM_DEV_ERROR(hdmi->dev, "invalid daifmt %d\n", daifmt->fmt);
415 return -EINVAL;
416 }
417
418 switch (params->sample_width) {
419 case 16:
420 hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
421 SPDIF_SAMPLE_SIZE_16BIT);
422 break;
423 case 20:
424 hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
425 SPDIF_SAMPLE_SIZE_20BIT);
426 break;
427 case 24:
428 hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
429 SPDIF_SAMPLE_SIZE_24BIT);
430 break;
431 default:
432 DRM_DEV_ERROR(hdmi->dev, "invalid sample width %d\n",
433 params->sample_width);
434 return -EINVAL;
435 }
436
437 /* CTS is calculated by hardware, and we only need to take care of N */
438 n = zx_hdmi_audio_get_n(params->sample_rate);
439 hdmi_writeb(hdmi, N_SVAL1, n & 0xff);
440 hdmi_writeb(hdmi, N_SVAL2, (n >> 8) & 0xff);
441 hdmi_writeb(hdmi, N_SVAL3, (n >> 16) & 0xf);
442
443 /* Enable spdif mode */
444 hdmi_writeb_mask(hdmi, AUD_MODE, SPDIF_EN, SPDIF_EN);
445
446 /* Enable audio input */
447 hdmi_writeb_mask(hdmi, AUD_EN, AUD_IN_EN, AUD_IN_EN);
448
449 memcpy(&frame.audio, cea, sizeof(*cea));
450
451 return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AUDIO);
452}
453
454static int zx_hdmi_audio_digital_mute(struct device *dev, void *data,
455 bool enable)
456{
457 struct zx_hdmi *hdmi = dev_get_drvdata(dev);
458
459 if (enable)
460 hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, TPI_AUD_MUTE,
461 TPI_AUD_MUTE);
462 else
463 hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, TPI_AUD_MUTE, 0);
464
465 return 0;
466}
467
468static int zx_hdmi_audio_get_eld(struct device *dev, void *data,
469 uint8_t *buf, size_t len)
470{
471 struct zx_hdmi *hdmi = dev_get_drvdata(dev);
472 struct drm_connector *connector = &hdmi->connector;
473
474 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
475
476 return 0;
477}
478
479static const struct hdmi_codec_ops zx_hdmi_codec_ops = {
480 .audio_startup = zx_hdmi_audio_startup,
481 .hw_params = zx_hdmi_audio_hw_params,
482 .audio_shutdown = zx_hdmi_audio_shutdown,
483 .digital_mute = zx_hdmi_audio_digital_mute,
484 .get_eld = zx_hdmi_audio_get_eld,
485};
486
487static struct hdmi_codec_pdata zx_hdmi_codec_pdata = {
488 .ops = &zx_hdmi_codec_ops,
489 .spdif = 1,
490};
491
492static int zx_hdmi_audio_register(struct zx_hdmi *hdmi)
493{
494 struct platform_device *pdev;
495
496 pdev = platform_device_register_data(hdmi->dev, HDMI_CODEC_DRV_NAME,
497 PLATFORM_DEVID_AUTO,
498 &zx_hdmi_codec_pdata,
499 sizeof(zx_hdmi_codec_pdata));
500 if (IS_ERR(pdev))
501 return PTR_ERR(pdev);
502
503 hdmi->audio_pdev = pdev;
504
505 return 0;
506}
507
Shawn Guo0a886f52016-09-22 19:52:39 +0800508static int zx_hdmi_i2c_read(struct zx_hdmi *hdmi, struct i2c_msg *msg)
509{
510 int len = msg->len;
511 u8 *buf = msg->buf;
512 int retry = 0;
513 int ret = 0;
514
515 /* Bits [9:8] of bytes */
516 hdmi_writeb(hdmi, ZX_DDC_DIN_CNT2, (len >> 8) & 0xff);
517 /* Bits [7:0] of bytes */
518 hdmi_writeb(hdmi, ZX_DDC_DIN_CNT1, len & 0xff);
519
520 /* Clear FIFO */
521 hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK, DDC_CMD_CLEAR_FIFO);
522
523 /* Kick off the read */
524 hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK,
525 DDC_CMD_SEQUENTIAL_READ);
526
527 while (len > 0) {
528 int cnt, i;
529
530 /* FIFO needs some time to get ready */
531 usleep_range(500, 1000);
532
533 cnt = hdmi_readb(hdmi, ZX_DDC_DOUT_CNT) & DDC_DOUT_CNT_MASK;
534 if (cnt == 0) {
535 if (++retry > 5) {
536 DRM_DEV_ERROR(hdmi->dev,
537 "DDC FIFO read timed out!");
538 return -ETIMEDOUT;
539 }
540 continue;
541 }
542
543 for (i = 0; i < cnt; i++)
544 *buf++ = hdmi_readb(hdmi, ZX_DDC_DATA);
545 len -= cnt;
546 }
547
548 return ret;
549}
550
551static int zx_hdmi_i2c_write(struct zx_hdmi *hdmi, struct i2c_msg *msg)
552{
553 /*
554 * The DDC I2C adapter is only for reading EDID data, so we assume
555 * that the write to this adapter must be the EDID data offset.
556 */
557 if ((msg->len != 1) ||
558 ((msg->addr != DDC_ADDR) && (msg->addr != DDC_SEGMENT_ADDR)))
559 return -EINVAL;
560
561 if (msg->addr == DDC_SEGMENT_ADDR)
562 hdmi_writeb(hdmi, ZX_DDC_SEGM, msg->addr << 1);
563 else if (msg->addr == DDC_ADDR)
564 hdmi_writeb(hdmi, ZX_DDC_ADDR, msg->addr << 1);
565
566 hdmi_writeb(hdmi, ZX_DDC_OFFSET, msg->buf[0]);
567
568 return 0;
569}
570
571static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
572 int num)
573{
574 struct zx_hdmi *hdmi = i2c_get_adapdata(adap);
575 struct zx_hdmi_i2c *ddc = hdmi->ddc;
576 int i, ret = 0;
577
578 mutex_lock(&ddc->lock);
579
580 /* Enable DDC master access */
581 hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, HW_DDC_MASTER);
582
583 for (i = 0; i < num; i++) {
584 DRM_DEV_DEBUG(hdmi->dev,
585 "xfer: num: %d/%d, len: %d, flags: %#x\n",
586 i + 1, num, msgs[i].len, msgs[i].flags);
587
588 if (msgs[i].flags & I2C_M_RD)
589 ret = zx_hdmi_i2c_read(hdmi, &msgs[i]);
590 else
591 ret = zx_hdmi_i2c_write(hdmi, &msgs[i]);
592
593 if (ret < 0)
594 break;
595 }
596
597 if (!ret)
598 ret = num;
599
600 /* Disable DDC master access */
601 hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, 0);
602
603 mutex_unlock(&ddc->lock);
604
605 return ret;
606}
607
608static u32 zx_hdmi_i2c_func(struct i2c_adapter *adapter)
609{
610 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
611}
612
613static const struct i2c_algorithm zx_hdmi_algorithm = {
614 .master_xfer = zx_hdmi_i2c_xfer,
615 .functionality = zx_hdmi_i2c_func,
616};
617
618static int zx_hdmi_ddc_register(struct zx_hdmi *hdmi)
619{
620 struct i2c_adapter *adap;
621 struct zx_hdmi_i2c *ddc;
622 int ret;
623
624 ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
625 if (!ddc)
626 return -ENOMEM;
627
628 hdmi->ddc = ddc;
629 mutex_init(&ddc->lock);
630
631 adap = &ddc->adap;
632 adap->owner = THIS_MODULE;
633 adap->class = I2C_CLASS_DDC;
634 adap->dev.parent = hdmi->dev;
635 adap->algo = &zx_hdmi_algorithm;
636 snprintf(adap->name, sizeof(adap->name), "zx hdmi i2c");
637
638 ret = i2c_add_adapter(adap);
639 if (ret) {
640 DRM_DEV_ERROR(hdmi->dev, "failed to add I2C adapter: %d\n",
641 ret);
642 return ret;
643 }
644
645 i2c_set_adapdata(adap, hdmi);
646
647 return 0;
648}
649
650static int zx_hdmi_bind(struct device *dev, struct device *master, void *data)
651{
652 struct platform_device *pdev = to_platform_device(dev);
653 struct drm_device *drm = data;
654 struct resource *res;
655 struct zx_hdmi *hdmi;
656 int irq;
657 int ret;
658
659 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
660 if (!hdmi)
661 return -ENOMEM;
662
663 hdmi->dev = dev;
664 hdmi->drm = drm;
665 hdmi->inf = &vou_inf_hdmi;
666
667 dev_set_drvdata(dev, hdmi);
668
669 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
670 hdmi->mmio = devm_ioremap_resource(dev, res);
671 if (IS_ERR(hdmi->mmio)) {
672 ret = PTR_ERR(hdmi->mmio);
673 DRM_DEV_ERROR(dev, "failed to remap hdmi region: %d\n", ret);
674 return ret;
675 }
676
677 irq = platform_get_irq(pdev, 0);
678 if (irq < 0)
679 return irq;
680
681 hdmi->cec_clk = devm_clk_get(hdmi->dev, "osc_cec");
682 if (IS_ERR(hdmi->cec_clk)) {
683 ret = PTR_ERR(hdmi->cec_clk);
684 DRM_DEV_ERROR(dev, "failed to get cec_clk: %d\n", ret);
685 return ret;
686 }
687
688 hdmi->osc_clk = devm_clk_get(hdmi->dev, "osc_clk");
689 if (IS_ERR(hdmi->osc_clk)) {
690 ret = PTR_ERR(hdmi->osc_clk);
691 DRM_DEV_ERROR(dev, "failed to get osc_clk: %d\n", ret);
692 return ret;
693 }
694
695 hdmi->xclk = devm_clk_get(hdmi->dev, "xclk");
696 if (IS_ERR(hdmi->xclk)) {
697 ret = PTR_ERR(hdmi->xclk);
698 DRM_DEV_ERROR(dev, "failed to get xclk: %d\n", ret);
699 return ret;
700 }
701
702 ret = zx_hdmi_ddc_register(hdmi);
703 if (ret) {
704 DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
705 return ret;
706 }
707
Shawn Guo83d71152016-12-01 17:20:31 +0800708 ret = zx_hdmi_audio_register(hdmi);
709 if (ret) {
710 DRM_DEV_ERROR(dev, "failed to register audio: %d\n", ret);
711 return ret;
712 }
713
Shawn Guo0a886f52016-09-22 19:52:39 +0800714 ret = zx_hdmi_register(drm, hdmi);
715 if (ret) {
716 DRM_DEV_ERROR(dev, "failed to register hdmi: %d\n", ret);
717 return ret;
718 }
719
720 ret = devm_request_threaded_irq(dev, irq, zx_hdmi_irq_handler,
721 zx_hdmi_irq_thread, IRQF_SHARED,
722 dev_name(dev), hdmi);
723 if (ret) {
724 DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
725 return ret;
726 }
727
728 return 0;
729}
730
731static void zx_hdmi_unbind(struct device *dev, struct device *master,
732 void *data)
733{
734 struct zx_hdmi *hdmi = dev_get_drvdata(dev);
735
736 hdmi->connector.funcs->destroy(&hdmi->connector);
737 hdmi->encoder.funcs->destroy(&hdmi->encoder);
Shawn Guo83d71152016-12-01 17:20:31 +0800738
739 if (hdmi->audio_pdev)
740 platform_device_unregister(hdmi->audio_pdev);
Shawn Guo0a886f52016-09-22 19:52:39 +0800741}
742
743static const struct component_ops zx_hdmi_component_ops = {
744 .bind = zx_hdmi_bind,
745 .unbind = zx_hdmi_unbind,
746};
747
748static int zx_hdmi_probe(struct platform_device *pdev)
749{
750 return component_add(&pdev->dev, &zx_hdmi_component_ops);
751}
752
753static int zx_hdmi_remove(struct platform_device *pdev)
754{
755 component_del(&pdev->dev, &zx_hdmi_component_ops);
756 return 0;
757}
758
759static const struct of_device_id zx_hdmi_of_match[] = {
760 { .compatible = "zte,zx296718-hdmi", },
761 { /* end */ },
762};
763MODULE_DEVICE_TABLE(of, zx_hdmi_of_match);
764
765struct platform_driver zx_hdmi_driver = {
766 .probe = zx_hdmi_probe,
767 .remove = zx_hdmi_remove,
768 .driver = {
769 .name = "zx-hdmi",
770 .of_match_table = zx_hdmi_of_match,
771 },
772};