| David Cohen | ecd6910 | 2013-12-16 12:07:36 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * mfld.c: Intel Medfield platform setup code |
| 3 | * |
| 4 | * (C) Copyright 2013 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; version 2 |
| 9 | * of the License. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/init.h> |
| 13 | |
| 14 | #include <asm/apic.h> |
| 15 | #include <asm/intel-mid.h> |
| 16 | #include <asm/intel_mid_vrtc.h> |
| 17 | |
| 18 | void intel_mid_power_off(void) |
| 19 | { |
| 20 | } |
| 21 | |
| 22 | unsigned long __init intel_mid_calibrate_tsc(void) |
| 23 | { |
| 24 | unsigned long fast_calibrate; |
| 25 | u32 lo, hi, ratio, fsb; |
| 26 | |
| 27 | rdmsr(MSR_IA32_PERF_STATUS, lo, hi); |
| 28 | pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi); |
| 29 | ratio = (hi >> 8) & 0x1f; |
| 30 | pr_debug("ratio is %d\n", ratio); |
| 31 | if (!ratio) { |
| 32 | pr_err("read a zero ratio, should be incorrect!\n"); |
| 33 | pr_err("force tsc ratio to 16 ...\n"); |
| 34 | ratio = 16; |
| 35 | } |
| 36 | rdmsr(MSR_FSB_FREQ, lo, hi); |
| 37 | if ((lo & 0x7) == 0x7) |
| 38 | fsb = PENWELL_FSB_FREQ_83SKU; |
| 39 | else |
| 40 | fsb = PENWELL_FSB_FREQ_100SKU; |
| 41 | fast_calibrate = ratio * fsb; |
| 42 | pr_debug("read penwell tsc %lu khz\n", fast_calibrate); |
| 43 | lapic_timer_frequency = fsb * 1000 / HZ; |
| 44 | /* mark tsc clocksource as reliable */ |
| 45 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); |
| 46 | |
| 47 | if (fast_calibrate) |
| 48 | return fast_calibrate; |
| 49 | |
| 50 | return 0; |
| 51 | } |