blob: 485be42519b96ddec1dcceafd19c84431e45cd99 [file] [log] [blame]
Kevin Hilmana4768d22009-04-14 07:18:14 -05001/*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
Lad, Prabhakare7eff702013-06-17 20:27:58 +053020#include <linux/err.h>
Kevin Hilmana4768d22009-04-14 07:18:14 -050021#include <linux/kernel.h>
Kevin Hilmana4768d22009-04-14 07:18:14 -050022#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
Kevin Hilmana4768d22009-04-14 07:18:14 -050026#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090027#include <linux/slab.h>
Matt Porter6cba4352013-06-20 16:06:38 -050028#include <linux/edma.h>
Matt Porter6cba4352013-06-20 16:06:38 -050029#include <linux/of_address.h>
30#include <linux/of_device.h>
31#include <linux/of_dma.h>
32#include <linux/of_irq.h>
33#include <linux/pm_runtime.h>
Kevin Hilmana4768d22009-04-14 07:18:14 -050034
Matt Porter3ad7a422013-03-06 11:15:31 -050035#include <linux/platform_data/edma.h>
Kevin Hilmana4768d22009-04-14 07:18:14 -050036
37/* Offsets matching "struct edmacc_param" */
38#define PARM_OPT 0x00
39#define PARM_SRC 0x04
40#define PARM_A_B_CNT 0x08
41#define PARM_DST 0x0c
42#define PARM_SRC_DST_BIDX 0x10
43#define PARM_LINK_BCNTRLD 0x14
44#define PARM_SRC_DST_CIDX 0x18
45#define PARM_CCNT 0x1c
46
47#define PARM_SIZE 0x20
48
49/* Offsets for EDMA CC global channel registers and their shadows */
50#define SH_ER 0x00 /* 64 bits */
51#define SH_ECR 0x08 /* 64 bits */
52#define SH_ESR 0x10 /* 64 bits */
53#define SH_CER 0x18 /* 64 bits */
54#define SH_EER 0x20 /* 64 bits */
55#define SH_EECR 0x28 /* 64 bits */
56#define SH_EESR 0x30 /* 64 bits */
57#define SH_SER 0x38 /* 64 bits */
58#define SH_SECR 0x40 /* 64 bits */
59#define SH_IER 0x50 /* 64 bits */
60#define SH_IECR 0x58 /* 64 bits */
61#define SH_IESR 0x60 /* 64 bits */
62#define SH_IPR 0x68 /* 64 bits */
63#define SH_ICR 0x70 /* 64 bits */
64#define SH_IEVAL 0x78
65#define SH_QER 0x80
66#define SH_QEER 0x84
67#define SH_QEECR 0x88
68#define SH_QEESR 0x8c
69#define SH_QSER 0x90
70#define SH_QSECR 0x94
71#define SH_SIZE 0x200
72
73/* Offsets for EDMA CC global registers */
74#define EDMA_REV 0x0000
75#define EDMA_CCCFG 0x0004
76#define EDMA_QCHMAP 0x0200 /* 8 registers */
77#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
78#define EDMA_QDMAQNUM 0x0260
79#define EDMA_QUETCMAP 0x0280
80#define EDMA_QUEPRI 0x0284
81#define EDMA_EMR 0x0300 /* 64 bits */
82#define EDMA_EMCR 0x0308 /* 64 bits */
83#define EDMA_QEMR 0x0310
84#define EDMA_QEMCR 0x0314
85#define EDMA_CCERR 0x0318
86#define EDMA_CCERRCLR 0x031c
87#define EDMA_EEVAL 0x0320
88#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
89#define EDMA_QRAE 0x0380 /* 4 registers */
90#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
91#define EDMA_QSTAT 0x0600 /* 2 registers */
92#define EDMA_QWMTHRA 0x0620
93#define EDMA_QWMTHRB 0x0624
94#define EDMA_CCSTAT 0x0640
95
96#define EDMA_M 0x1000 /* global channel registers */
97#define EDMA_ECR 0x1008
98#define EDMA_ECRH 0x100C
99#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
100#define EDMA_PARM 0x4000 /* 128 param entries */
101
Kevin Hilmana4768d22009-04-14 07:18:14 -0500102#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
103
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400104#define EDMA_DCHMAP 0x0100 /* 64 registers */
Peter Ujfalusi6d10c392014-05-16 15:17:15 +0300105
106/* CCCFG register */
107#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
108#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
109#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
110#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
111#define CHMAP_EXIST BIT(24)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400112
Kevin Hilmana4768d22009-04-14 07:18:14 -0500113#define EDMA_MAX_DMACH 64
114#define EDMA_MAX_PARAMENTRY 512
Kevin Hilmana4768d22009-04-14 07:18:14 -0500115
116/*****************************************************************************/
117
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400118static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
Kevin Hilmana4768d22009-04-14 07:18:14 -0500119
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400120static inline unsigned int edma_read(unsigned ctlr, int offset)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500121{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400122 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500123}
124
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400125static inline void edma_write(unsigned ctlr, int offset, int val)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500126{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400127 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500128}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400129static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
130 unsigned or)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500131{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400132 unsigned val = edma_read(ctlr, offset);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500133 val &= and;
134 val |= or;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400135 edma_write(ctlr, offset, val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500136}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400137static inline void edma_and(unsigned ctlr, int offset, unsigned and)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500138{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400139 unsigned val = edma_read(ctlr, offset);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500140 val &= and;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400141 edma_write(ctlr, offset, val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500142}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400143static inline void edma_or(unsigned ctlr, int offset, unsigned or)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500144{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400145 unsigned val = edma_read(ctlr, offset);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500146 val |= or;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400147 edma_write(ctlr, offset, val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500148}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400149static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500150{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400151 return edma_read(ctlr, offset + (i << 2));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500152}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400153static inline void edma_write_array(unsigned ctlr, int offset, int i,
154 unsigned val)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500155{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400156 edma_write(ctlr, offset + (i << 2), val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500157}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400158static inline void edma_modify_array(unsigned ctlr, int offset, int i,
Kevin Hilmana4768d22009-04-14 07:18:14 -0500159 unsigned and, unsigned or)
160{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400161 edma_modify(ctlr, offset + (i << 2), and, or);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500162}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400163static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500164{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400165 edma_or(ctlr, offset + (i << 2), or);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500166}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400167static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
168 unsigned or)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500169{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400170 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500171}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400172static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
173 unsigned val)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500174{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400175 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500176}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400177static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500178{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400179 return edma_read(ctlr, EDMA_SHADOW0 + offset);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500180}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400181static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
182 int i)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500183{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400184 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500185}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400186static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500187{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400188 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500189}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400190static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
191 unsigned val)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500192{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400193 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500194}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400195static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
196 int param_no)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500197{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400198 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500199}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400200static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
201 unsigned val)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500202{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400203 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500204}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400205static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
Kevin Hilmana4768d22009-04-14 07:18:14 -0500206 unsigned and, unsigned or)
207{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400208 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500209}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400210static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
211 unsigned and)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500212{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400213 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500214}
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400215static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
216 unsigned or)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500217{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400218 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500219}
220
Rajashekhara, Sudhakar90bd4e62010-06-29 11:35:13 +0530221static inline void set_bits(int offset, int len, unsigned long *p)
222{
223 for (; len > 0; len--)
224 set_bit(offset + (len - 1), p);
225}
226
227static inline void clear_bits(int offset, int len, unsigned long *p)
228{
229 for (; len > 0; len--)
230 clear_bit(offset + (len - 1), p);
231}
232
Kevin Hilmana4768d22009-04-14 07:18:14 -0500233/*****************************************************************************/
234
235/* actual number of DMA channels and slots on this silicon */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400236struct edma {
237 /* how many dma resources of each type */
238 unsigned num_channels;
239 unsigned num_region;
240 unsigned num_slots;
241 unsigned num_tc;
Sandeep Paulraja0f02022009-07-27 09:57:07 -0400242 enum dma_event_q default_queue;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500243
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400244 /* list of channels with no even trigger; terminated by "-1" */
245 const s8 *noevent;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500246
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400247 /* The edma_inuse bit for each PaRAM slot is clear unless the
248 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
249 */
250 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500251
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530252 /* The edma_unused bit for each channel is clear unless
253 * it is not being used on this platform. It uses a bit
254 * of SOC-specific initialization code.
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400255 */
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530256 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400257
258 unsigned irq_res_start;
259 unsigned irq_res_end;
260
261 struct dma_interrupt_data {
262 void (*callback)(unsigned channel, unsigned short ch_status,
263 void *data);
264 void *data;
265 } intr_data[EDMA_MAX_DMACH];
266};
267
Sekhar Nori3f68b982010-05-04 14:11:35 +0530268static struct edma *edma_cc[EDMA_MAX_CC];
Sudhakar Rajashekhara2d517502010-01-06 17:28:44 +0530269static int arch_num_cc;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500270
271/* dummy param set used to (re)initialize parameter RAM slots */
272static const struct edmacc_param dummy_paramset = {
273 .link_bcntrld = 0xffff,
274 .ccnt = 1,
275};
276
Joel Fernandes6cdaca42013-09-26 16:55:46 -0500277static const struct of_device_id edma_of_ids[] = {
278 { .compatible = "ti,edma3", },
279 {}
280};
281
Kevin Hilmana4768d22009-04-14 07:18:14 -0500282/*****************************************************************************/
283
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400284static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
285 enum dma_event_q queue_no)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500286{
287 int bit = (ch_no & 0x7) * 4;
288
289 /* default to low priority queue */
290 if (queue_no == EVENTQ_DEFAULT)
Sekhar Nori3f68b982010-05-04 14:11:35 +0530291 queue_no = edma_cc[ctlr]->default_queue;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500292
293 queue_no &= 7;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400294 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
Kevin Hilmana4768d22009-04-14 07:18:14 -0500295 ~(0x7 << bit), queue_no << bit);
296}
297
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400298static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
299 int priority)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500300{
301 int bit = queue_no * 4;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400302 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
303 ((priority & 0x7) << bit));
304}
305
306/**
307 * map_dmach_param - Maps channel number to param entry number
308 *
309 * This maps the dma channel number to param entry numberter. In
310 * other words using the DMA channel mapping registers a param entry
311 * can be mapped to any channel
312 *
313 * Callers are responsible for ensuring the channel mapping logic is
314 * included in that particular EDMA variant (Eg : dm646x)
315 *
316 */
317static void __init map_dmach_param(unsigned ctlr)
318{
319 int i;
320 for (i = 0; i < EDMA_MAX_DMACH; i++)
321 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500322}
323
324static inline void
325setup_dma_interrupt(unsigned lch,
326 void (*callback)(unsigned channel, u16 ch_status, void *data),
327 void *data)
328{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400329 unsigned ctlr;
330
331 ctlr = EDMA_CTLR(lch);
332 lch = EDMA_CHAN_SLOT(lch);
333
Sekhar Nori243bc652010-05-04 14:11:36 +0530334 if (!callback)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400335 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
Sekhar Norid78a9492010-05-10 12:41:18 +0530336 BIT(lch & 0x1f));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500337
Sekhar Nori3f68b982010-05-04 14:11:35 +0530338 edma_cc[ctlr]->intr_data[lch].callback = callback;
339 edma_cc[ctlr]->intr_data[lch].data = data;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500340
341 if (callback) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400342 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
Sekhar Norid78a9492010-05-10 12:41:18 +0530343 BIT(lch & 0x1f));
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400344 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
Sekhar Norid78a9492010-05-10 12:41:18 +0530345 BIT(lch & 0x1f));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500346 }
347}
348
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400349static int irq2ctlr(int irq)
350{
Sekhar Nori3f68b982010-05-04 14:11:35 +0530351 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400352 return 0;
Sekhar Nori3f68b982010-05-04 14:11:35 +0530353 else if (irq >= edma_cc[1]->irq_res_start &&
354 irq <= edma_cc[1]->irq_res_end)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400355 return 1;
356
357 return -1;
358}
359
Kevin Hilmana4768d22009-04-14 07:18:14 -0500360/******************************************************************************
361 *
362 * DMA interrupt handler
363 *
364 *****************************************************************************/
365static irqreturn_t dma_irq_handler(int irq, void *data)
366{
Kulikov Vasiliy93fe23d2010-07-17 19:19:07 +0400367 int ctlr;
Sebastian Andrzej Siewiorbcd59b02012-02-09 13:28:26 +0100368 u32 sh_ier;
369 u32 sh_ipr;
370 u32 bank;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500371
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400372 ctlr = irq2ctlr(irq);
Kulikov Vasiliy93fe23d2010-07-17 19:19:07 +0400373 if (ctlr < 0)
374 return IRQ_NONE;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400375
Kevin Hilmana4768d22009-04-14 07:18:14 -0500376 dev_dbg(data, "dma_irq_handler\n");
377
Sebastian Andrzej Siewiorbcd59b02012-02-09 13:28:26 +0100378 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
379 if (!sh_ipr) {
380 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
381 if (!sh_ipr)
382 return IRQ_NONE;
383 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
384 bank = 1;
385 } else {
386 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
387 bank = 0;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500388 }
Sebastian Andrzej Siewiorbcd59b02012-02-09 13:28:26 +0100389
390 do {
391 u32 slot;
392 u32 channel;
393
394 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
395
396 slot = __ffs(sh_ipr);
397 sh_ipr &= ~(BIT(slot));
398
399 if (sh_ier & BIT(slot)) {
400 channel = (bank << 5) | slot;
401 /* Clear the corresponding IPR bits */
402 edma_shadow0_write_array(ctlr, SH_ICR, bank,
403 BIT(slot));
404 if (edma_cc[ctlr]->intr_data[channel].callback)
405 edma_cc[ctlr]->intr_data[channel].callback(
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530406 channel, EDMA_DMA_COMPLETE,
Sebastian Andrzej Siewiorbcd59b02012-02-09 13:28:26 +0100407 edma_cc[ctlr]->intr_data[channel].data);
408 }
409 } while (sh_ipr);
410
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400411 edma_shadow0_write(ctlr, SH_IEVAL, 1);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500412 return IRQ_HANDLED;
413}
414
415/******************************************************************************
416 *
417 * DMA error interrupt handler
418 *
419 *****************************************************************************/
420static irqreturn_t dma_ccerr_handler(int irq, void *data)
421{
422 int i;
Kulikov Vasiliy93fe23d2010-07-17 19:19:07 +0400423 int ctlr;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500424 unsigned int cnt = 0;
425
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400426 ctlr = irq2ctlr(irq);
Kulikov Vasiliy93fe23d2010-07-17 19:19:07 +0400427 if (ctlr < 0)
428 return IRQ_NONE;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400429
Kevin Hilmana4768d22009-04-14 07:18:14 -0500430 dev_dbg(data, "dma_ccerr_handler\n");
431
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400432 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
433 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
434 (edma_read(ctlr, EDMA_QEMR) == 0) &&
435 (edma_read(ctlr, EDMA_CCERR) == 0))
Kevin Hilmana4768d22009-04-14 07:18:14 -0500436 return IRQ_NONE;
437
438 while (1) {
439 int j = -1;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400440 if (edma_read_array(ctlr, EDMA_EMR, 0))
Kevin Hilmana4768d22009-04-14 07:18:14 -0500441 j = 0;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400442 else if (edma_read_array(ctlr, EDMA_EMR, 1))
Kevin Hilmana4768d22009-04-14 07:18:14 -0500443 j = 1;
444 if (j >= 0) {
445 dev_dbg(data, "EMR%d %08x\n", j,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400446 edma_read_array(ctlr, EDMA_EMR, j));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500447 for (i = 0; i < 32; i++) {
448 int k = (j << 5) + i;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400449 if (edma_read_array(ctlr, EDMA_EMR, j) &
Sekhar Norid78a9492010-05-10 12:41:18 +0530450 BIT(i)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500451 /* Clear the corresponding EMR bits */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400452 edma_write_array(ctlr, EDMA_EMCR, j,
Sekhar Norid78a9492010-05-10 12:41:18 +0530453 BIT(i));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500454 /* Clear any SER */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400455 edma_shadow0_write_array(ctlr, SH_SECR,
Sekhar Norid78a9492010-05-10 12:41:18 +0530456 j, BIT(i));
Sekhar Nori3f68b982010-05-04 14:11:35 +0530457 if (edma_cc[ctlr]->intr_data[k].
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400458 callback) {
Sekhar Nori3f68b982010-05-04 14:11:35 +0530459 edma_cc[ctlr]->intr_data[k].
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400460 callback(k,
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530461 EDMA_DMA_CC_ERROR,
Sekhar Nori3f68b982010-05-04 14:11:35 +0530462 edma_cc[ctlr]->intr_data
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400463 [k].data);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500464 }
465 }
466 }
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400467 } else if (edma_read(ctlr, EDMA_QEMR)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500468 dev_dbg(data, "QEMR %02x\n",
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400469 edma_read(ctlr, EDMA_QEMR));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500470 for (i = 0; i < 8; i++) {
Sekhar Norid78a9492010-05-10 12:41:18 +0530471 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500472 /* Clear the corresponding IPR bits */
Sekhar Norid78a9492010-05-10 12:41:18 +0530473 edma_write(ctlr, EDMA_QEMCR, BIT(i));
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400474 edma_shadow0_write(ctlr, SH_QSECR,
Sekhar Norid78a9492010-05-10 12:41:18 +0530475 BIT(i));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500476
477 /* NOTE: not reported!! */
478 }
479 }
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400480 } else if (edma_read(ctlr, EDMA_CCERR)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500481 dev_dbg(data, "CCERR %08x\n",
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400482 edma_read(ctlr, EDMA_CCERR));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500483 /* FIXME: CCERR.BIT(16) ignored! much better
484 * to just write CCERRCLR with CCERR value...
485 */
486 for (i = 0; i < 8; i++) {
Sekhar Norid78a9492010-05-10 12:41:18 +0530487 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500488 /* Clear the corresponding IPR bits */
Sekhar Norid78a9492010-05-10 12:41:18 +0530489 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500490
491 /* NOTE: not reported!! */
492 }
493 }
494 }
Sekhar Noria6374f52010-05-10 12:41:19 +0530495 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
496 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
497 (edma_read(ctlr, EDMA_QEMR) == 0) &&
498 (edma_read(ctlr, EDMA_CCERR) == 0))
Kevin Hilmana4768d22009-04-14 07:18:14 -0500499 break;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500500 cnt++;
501 if (cnt > 10)
502 break;
503 }
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400504 edma_write(ctlr, EDMA_EEVAL, 1);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500505 return IRQ_HANDLED;
506}
507
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400508static int reserve_contiguous_slots(int ctlr, unsigned int id,
509 unsigned int num_slots,
510 unsigned int start_slot)
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400511{
512 int i, j;
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400513 unsigned int count = num_slots;
514 int stop_slot = start_slot;
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400515 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400516
Sekhar Nori3f68b982010-05-04 14:11:35 +0530517 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400518 j = EDMA_CHAN_SLOT(i);
Sekhar Nori3f68b982010-05-04 14:11:35 +0530519 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400520 /* Record our current beginning slot */
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400521 if (count == num_slots)
522 stop_slot = i;
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400523
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400524 count--;
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400525 set_bit(j, tmp_inuse);
526
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400527 if (count == 0)
528 break;
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400529 } else {
530 clear_bit(j, tmp_inuse);
531
532 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400533 stop_slot = i;
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400534 break;
Sekhar Nori243bc652010-05-04 14:11:36 +0530535 } else {
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400536 count = num_slots;
Sekhar Nori243bc652010-05-04 14:11:36 +0530537 }
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400538 }
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400539 }
540
541 /*
542 * We have to clear any bits that we set
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400543 * if we run out parameter RAM slots, i.e we do find a set
544 * of contiguous parameter RAM slots but do not find the exact number
545 * requested as we may reach the total number of parameter RAM slots
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400546 */
Sekhar Nori3f68b982010-05-04 14:11:35 +0530547 if (i == edma_cc[ctlr]->num_slots)
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400548 stop_slot = i;
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400549
Akinobu Mita98e3b332012-04-11 20:36:53 +0900550 j = start_slot;
551 for_each_set_bit_from(j, tmp_inuse, stop_slot)
552 clear_bit(j, edma_cc[ctlr]->edma_inuse);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400553
Sandeep Paulrajcc93fc32009-09-20 13:47:03 -0400554 if (count)
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400555 return -EBUSY;
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400556
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400557 for (j = i - num_slots + 1; j <= i; ++j)
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400558 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
559 &dummy_paramset, PARM_SIZE);
560
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400561 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400562}
563
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530564static int prepare_unused_channel_list(struct device *dev, void *data)
565{
566 struct platform_device *pdev = to_platform_device(dev);
Joel Fernandes6cdaca42013-09-26 16:55:46 -0500567 int i, count, ctlr;
568 struct of_phandle_args dma_spec;
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530569
Joel Fernandes6cdaca42013-09-26 16:55:46 -0500570 if (dev->of_node) {
571 count = of_property_count_strings(dev->of_node, "dma-names");
572 if (count < 0)
573 return 0;
574 for (i = 0; i < count; i++) {
575 if (of_parse_phandle_with_args(dev->of_node, "dmas",
576 "#dma-cells", i,
577 &dma_spec))
578 continue;
579
580 if (!of_match_node(edma_of_ids, dma_spec.np)) {
581 of_node_put(dma_spec.np);
582 continue;
583 }
584
585 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
586 edma_cc[0]->edma_unused);
587 of_node_put(dma_spec.np);
588 }
589 return 0;
590 }
591
592 /* For non-OF case */
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530593 for (i = 0; i < pdev->num_resources; i++) {
594 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
595 (int)pdev->resource[i].start >= 0) {
596 ctlr = EDMA_CTLR(pdev->resource[i].start);
597 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
Joel Fernandes6cdaca42013-09-26 16:55:46 -0500598 edma_cc[ctlr]->edma_unused);
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530599 }
600 }
601
602 return 0;
603}
604
Kevin Hilmana4768d22009-04-14 07:18:14 -0500605/*-----------------------------------------------------------------------*/
606
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530607static bool unused_chan_list_done;
608
Kevin Hilmana4768d22009-04-14 07:18:14 -0500609/* Resource alloc/free: dma channels, parameter RAM slots */
610
611/**
612 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
613 * @channel: specific channel to allocate; negative for "any unmapped channel"
614 * @callback: optional; to be issued on DMA completion or errors
615 * @data: passed to callback
616 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
617 * Controller (TC) executes requests using this channel. Use
618 * EVENTQ_DEFAULT unless you really need a high priority queue.
619 *
620 * This allocates a DMA channel and its associated parameter RAM slot.
621 * The parameter RAM is initialized to hold a dummy transfer.
622 *
623 * Normal use is to pass a specific channel number as @channel, to make
624 * use of hardware events mapped to that channel. When the channel will
625 * be used only for software triggering or event chaining, channels not
626 * mapped to hardware events (or mapped to unused events) are preferable.
627 *
628 * DMA transfers start from a channel using edma_start(), or by
629 * chaining. When the transfer described in that channel's parameter RAM
630 * slot completes, that slot's data may be reloaded through a link.
631 *
632 * DMA errors are only reported to the @callback associated with the
633 * channel driving that transfer, but transfer completion callbacks can
634 * be sent to another channel under control of the TCC field in
635 * the option word of the transfer's parameter RAM set. Drivers must not
636 * use DMA transfer completion callbacks for channels they did not allocate.
637 * (The same applies to TCC codes used in transfer chaining.)
638 *
639 * Returns the number of the channel, else negative errno.
640 */
641int edma_alloc_channel(int channel,
642 void (*callback)(unsigned channel, u16 ch_status, void *data),
643 void *data,
644 enum dma_event_q eventq_no)
645{
Sudhakar Rajashekhara447f18f2010-01-06 17:29:11 +0530646 unsigned i, done = 0, ctlr = 0;
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +0530647 int ret = 0;
648
649 if (!unused_chan_list_done) {
650 /*
651 * Scan all the platform devices to find out the EDMA channels
652 * used and clear them in the unused list, making the rest
653 * available for ARM usage.
654 */
655 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
656 prepare_unused_channel_list);
657 if (ret < 0)
658 return ret;
659
660 unused_chan_list_done = true;
661 }
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400662
663 if (channel >= 0) {
664 ctlr = EDMA_CTLR(channel);
665 channel = EDMA_CHAN_SLOT(channel);
666 }
667
Kevin Hilmana4768d22009-04-14 07:18:14 -0500668 if (channel < 0) {
Sudhakar Rajashekhara2d517502010-01-06 17:28:44 +0530669 for (i = 0; i < arch_num_cc; i++) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400670 channel = 0;
671 for (;;) {
Sekhar Nori3f68b982010-05-04 14:11:35 +0530672 channel = find_next_bit(edma_cc[i]->edma_unused,
673 edma_cc[i]->num_channels,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400674 channel);
Sekhar Nori3f68b982010-05-04 14:11:35 +0530675 if (channel == edma_cc[i]->num_channels)
Sudhakar Rajashekhara447f18f2010-01-06 17:29:11 +0530676 break;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400677 if (!test_and_set_bit(channel,
Sekhar Nori3f68b982010-05-04 14:11:35 +0530678 edma_cc[i]->edma_inuse)) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400679 done = 1;
680 ctlr = i;
681 break;
682 }
683 channel++;
684 }
685 if (done)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500686 break;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500687 }
Sudhakar Rajashekhara447f18f2010-01-06 17:29:11 +0530688 if (!done)
689 return -ENOMEM;
Sekhar Nori3f68b982010-05-04 14:11:35 +0530690 } else if (channel >= edma_cc[ctlr]->num_channels) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500691 return -EINVAL;
Sekhar Nori3f68b982010-05-04 14:11:35 +0530692 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500693 return -EBUSY;
694 }
695
696 /* ensure access through shadow region 0 */
Sekhar Norid78a9492010-05-10 12:41:18 +0530697 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
Kevin Hilmana4768d22009-04-14 07:18:14 -0500698
699 /* ensure no events are pending */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400700 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
701 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
Kevin Hilmana4768d22009-04-14 07:18:14 -0500702 &dummy_paramset, PARM_SIZE);
703
704 if (callback)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400705 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
706 callback, data);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500707
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400708 map_dmach_queue(ctlr, channel, eventq_no);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500709
Sudhakar Rajashekhara0e6cb8d2010-01-06 17:28:36 +0530710 return EDMA_CTLR_CHAN(ctlr, channel);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500711}
712EXPORT_SYMBOL(edma_alloc_channel);
713
714
715/**
716 * edma_free_channel - deallocate DMA channel
717 * @channel: dma channel returned from edma_alloc_channel()
718 *
719 * This deallocates the DMA channel and associated parameter RAM slot
720 * allocated by edma_alloc_channel().
721 *
722 * Callers are responsible for ensuring the channel is inactive, and
723 * will not be reactivated by linking, chaining, or software calls to
724 * edma_start().
725 */
726void edma_free_channel(unsigned channel)
727{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400728 unsigned ctlr;
729
730 ctlr = EDMA_CTLR(channel);
731 channel = EDMA_CHAN_SLOT(channel);
732
Sekhar Nori3f68b982010-05-04 14:11:35 +0530733 if (channel >= edma_cc[ctlr]->num_channels)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500734 return;
735
736 setup_dma_interrupt(channel, NULL, NULL);
737 /* REVISIT should probably take out of shadow region 0 */
738
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400739 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
Kevin Hilmana4768d22009-04-14 07:18:14 -0500740 &dummy_paramset, PARM_SIZE);
Sekhar Nori3f68b982010-05-04 14:11:35 +0530741 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500742}
743EXPORT_SYMBOL(edma_free_channel);
744
745/**
746 * edma_alloc_slot - allocate DMA parameter RAM
747 * @slot: specific slot to allocate; negative for "any unused slot"
748 *
749 * This allocates a parameter RAM slot, initializing it to hold a
750 * dummy transfer. Slots allocated using this routine have not been
751 * mapped to a hardware DMA channel, and will normally be used by
752 * linking to them from a slot associated with a DMA channel.
753 *
754 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
755 * slots may be allocated on behalf of DSP firmware.
756 *
757 * Returns the number of the slot, else negative errno.
758 */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400759int edma_alloc_slot(unsigned ctlr, int slot)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500760{
Matt Porter06955272013-03-05 10:58:22 -0500761 if (!edma_cc[ctlr])
762 return -EINVAL;
763
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400764 if (slot >= 0)
765 slot = EDMA_CHAN_SLOT(slot);
766
Kevin Hilmana4768d22009-04-14 07:18:14 -0500767 if (slot < 0) {
Sekhar Nori3f68b982010-05-04 14:11:35 +0530768 slot = edma_cc[ctlr]->num_channels;
Kevin Hilmana4768d22009-04-14 07:18:14 -0500769 for (;;) {
Sekhar Nori3f68b982010-05-04 14:11:35 +0530770 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
771 edma_cc[ctlr]->num_slots, slot);
772 if (slot == edma_cc[ctlr]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500773 return -ENOMEM;
Sekhar Nori3f68b982010-05-04 14:11:35 +0530774 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
Kevin Hilmana4768d22009-04-14 07:18:14 -0500775 break;
776 }
Sekhar Nori3f68b982010-05-04 14:11:35 +0530777 } else if (slot < edma_cc[ctlr]->num_channels ||
778 slot >= edma_cc[ctlr]->num_slots) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500779 return -EINVAL;
Sekhar Nori3f68b982010-05-04 14:11:35 +0530780 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -0500781 return -EBUSY;
782 }
783
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400784 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
Kevin Hilmana4768d22009-04-14 07:18:14 -0500785 &dummy_paramset, PARM_SIZE);
786
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400787 return EDMA_CTLR_CHAN(ctlr, slot);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500788}
789EXPORT_SYMBOL(edma_alloc_slot);
790
791/**
792 * edma_free_slot - deallocate DMA parameter RAM
793 * @slot: parameter RAM slot returned from edma_alloc_slot()
794 *
795 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
796 * Callers are responsible for ensuring the slot is inactive, and will
797 * not be activated.
798 */
799void edma_free_slot(unsigned slot)
800{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400801 unsigned ctlr;
802
803 ctlr = EDMA_CTLR(slot);
804 slot = EDMA_CHAN_SLOT(slot);
805
Sekhar Nori3f68b982010-05-04 14:11:35 +0530806 if (slot < edma_cc[ctlr]->num_channels ||
807 slot >= edma_cc[ctlr]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -0500808 return;
809
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400810 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
Kevin Hilmana4768d22009-04-14 07:18:14 -0500811 &dummy_paramset, PARM_SIZE);
Sekhar Nori3f68b982010-05-04 14:11:35 +0530812 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500813}
814EXPORT_SYMBOL(edma_free_slot);
815
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400816
817/**
818 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
819 * The API will return the starting point of a set of
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400820 * contiguous parameter RAM slots that have been requested
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400821 *
822 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
823 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400824 * @count: number of contiguous Paramter RAM slots
825 * @slot - the start value of Parameter RAM slot that should be passed if id
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400826 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
827 *
828 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400829 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
830 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400831 *
832 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400833 * set of contiguous parameter RAM slots from the "slot" that is passed as an
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400834 * argument to the API.
835 *
836 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400837 * starts looking for a set of contiguous parameter RAMs from the "slot"
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400838 * that is passed as an argument to the API. On failure the API will try to
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400839 * find a set of contiguous Parameter RAM slots from the remaining Parameter
840 * RAM slots
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400841 */
842int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
843{
844 /*
845 * The start slot requested should be greater than
846 * the number of channels and lesser than the total number
847 * of slots
848 */
Sandeep Paulraj6b0cf4e2009-09-16 18:17:43 -0400849 if ((id != EDMA_CONT_PARAMS_ANY) &&
Sekhar Nori3f68b982010-05-04 14:11:35 +0530850 (slot < edma_cc[ctlr]->num_channels ||
851 slot >= edma_cc[ctlr]->num_slots))
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400852 return -EINVAL;
853
854 /*
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400855 * The number of parameter RAM slots requested cannot be less than 1
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400856 * and cannot be more than the number of slots minus the number of
857 * channels
858 */
859 if (count < 1 || count >
Sekhar Nori3f68b982010-05-04 14:11:35 +0530860 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400861 return -EINVAL;
862
863 switch (id) {
864 case EDMA_CONT_PARAMS_ANY:
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400865 return reserve_contiguous_slots(ctlr, id, count,
Sekhar Nori3f68b982010-05-04 14:11:35 +0530866 edma_cc[ctlr]->num_channels);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400867 case EDMA_CONT_PARAMS_FIXED_EXACT:
868 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400869 return reserve_contiguous_slots(ctlr, id, count, slot);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400870 default:
871 return -EINVAL;
872 }
873
874}
875EXPORT_SYMBOL(edma_alloc_cont_slots);
876
877/**
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400878 * edma_free_cont_slots - deallocate DMA parameter RAM slots
879 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
880 * @count: the number of contiguous parameter RAM slots to be freed
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400881 *
882 * This deallocates the parameter RAM slots allocated by
883 * edma_alloc_cont_slots.
884 * Callers/applications need to keep track of sets of contiguous
Sandeep Paulraj134ce222009-09-20 14:06:33 -0400885 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400886 * API.
887 * Callers are responsible for ensuring the slots are inactive, and will
888 * not be activated.
889 */
890int edma_free_cont_slots(unsigned slot, int count)
891{
Sandeep Paulraj51c99e02009-09-16 18:09:59 -0400892 unsigned ctlr, slot_to_free;
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400893 int i;
894
895 ctlr = EDMA_CTLR(slot);
896 slot = EDMA_CHAN_SLOT(slot);
897
Sekhar Nori3f68b982010-05-04 14:11:35 +0530898 if (slot < edma_cc[ctlr]->num_channels ||
899 slot >= edma_cc[ctlr]->num_slots ||
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400900 count < 1)
901 return -EINVAL;
902
903 for (i = slot; i < slot + count; ++i) {
904 ctlr = EDMA_CTLR(i);
Sandeep Paulraj51c99e02009-09-16 18:09:59 -0400905 slot_to_free = EDMA_CHAN_SLOT(i);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400906
Sandeep Paulraj51c99e02009-09-16 18:09:59 -0400907 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400908 &dummy_paramset, PARM_SIZE);
Sekhar Nori3f68b982010-05-04 14:11:35 +0530909 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
Sandeep Paulraj213765d2009-07-27 15:10:36 -0400910 }
911
912 return 0;
913}
914EXPORT_SYMBOL(edma_free_cont_slots);
915
Kevin Hilmana4768d22009-04-14 07:18:14 -0500916/*-----------------------------------------------------------------------*/
917
918/* Parameter RAM operations (i) -- read/write partial slots */
919
920/**
921 * edma_set_src - set initial DMA source address in parameter RAM slot
922 * @slot: parameter RAM slot being configured
923 * @src_port: physical address of source (memory, controller FIFO, etc)
924 * @addressMode: INCR, except in very rare cases
925 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
926 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
927 *
928 * Note that the source address is modified during the DMA transfer
929 * according to edma_set_src_index().
930 */
931void edma_set_src(unsigned slot, dma_addr_t src_port,
932 enum address_mode mode, enum fifo_width width)
933{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400934 unsigned ctlr;
935
936 ctlr = EDMA_CTLR(slot);
937 slot = EDMA_CHAN_SLOT(slot);
938
Sekhar Nori3f68b982010-05-04 14:11:35 +0530939 if (slot < edma_cc[ctlr]->num_slots) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400940 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500941
942 if (mode) {
943 /* set SAM and program FWID */
944 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
945 } else {
946 /* clear SAM */
947 i &= ~SAM;
948 }
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400949 edma_parm_write(ctlr, PARM_OPT, slot, i);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500950
951 /* set the source port address
952 in source register of param structure */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400953 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500954 }
955}
956EXPORT_SYMBOL(edma_set_src);
957
958/**
959 * edma_set_dest - set initial DMA destination address in parameter RAM slot
960 * @slot: parameter RAM slot being configured
961 * @dest_port: physical address of destination (memory, controller FIFO, etc)
962 * @addressMode: INCR, except in very rare cases
963 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
964 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
965 *
966 * Note that the destination address is modified during the DMA transfer
967 * according to edma_set_dest_index().
968 */
969void edma_set_dest(unsigned slot, dma_addr_t dest_port,
970 enum address_mode mode, enum fifo_width width)
971{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400972 unsigned ctlr;
973
974 ctlr = EDMA_CTLR(slot);
975 slot = EDMA_CHAN_SLOT(slot);
976
Sekhar Nori3f68b982010-05-04 14:11:35 +0530977 if (slot < edma_cc[ctlr]->num_slots) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400978 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500979
980 if (mode) {
981 /* set DAM and program FWID */
982 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
983 } else {
984 /* clear DAM */
985 i &= ~DAM;
986 }
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400987 edma_parm_write(ctlr, PARM_OPT, slot, i);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500988 /* set the destination port address
989 in dest register of param structure */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400990 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
Kevin Hilmana4768d22009-04-14 07:18:14 -0500991 }
992}
993EXPORT_SYMBOL(edma_set_dest);
994
995/**
Thomas Gleixnercdae05a2014-04-28 10:49:43 +0000996 * edma_get_position - returns the current transfer point
Kevin Hilmana4768d22009-04-14 07:18:14 -0500997 * @slot: parameter RAM slot being examined
Thomas Gleixnercdae05a2014-04-28 10:49:43 +0000998 * @dst: true selects the dest position, false the source
Kevin Hilmana4768d22009-04-14 07:18:14 -0500999 *
Thomas Gleixnercdae05a2014-04-28 10:49:43 +00001000 * Returns the position of the current active slot
Kevin Hilmana4768d22009-04-14 07:18:14 -05001001 */
Thomas Gleixnercdae05a2014-04-28 10:49:43 +00001002dma_addr_t edma_get_position(unsigned slot, bool dst)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001003{
Thomas Gleixnercdae05a2014-04-28 10:49:43 +00001004 u32 offs, ctlr = EDMA_CTLR(slot);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001005
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001006 slot = EDMA_CHAN_SLOT(slot);
1007
Thomas Gleixnercdae05a2014-04-28 10:49:43 +00001008 offs = PARM_OFFSET(slot);
1009 offs += dst ? PARM_DST : PARM_SRC;
1010
1011 return edma_read(ctlr, offs);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001012}
Kevin Hilmana4768d22009-04-14 07:18:14 -05001013
1014/**
1015 * edma_set_src_index - configure DMA source address indexing
1016 * @slot: parameter RAM slot being configured
1017 * @src_bidx: byte offset between source arrays in a frame
1018 * @src_cidx: byte offset between source frames in a block
1019 *
1020 * Offsets are specified to support either contiguous or discontiguous
1021 * memory transfers, or repeated access to a hardware register, as needed.
1022 * When accessing hardware registers, both offsets are normally zero.
1023 */
1024void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1025{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001026 unsigned ctlr;
1027
1028 ctlr = EDMA_CTLR(slot);
1029 slot = EDMA_CHAN_SLOT(slot);
1030
Sekhar Nori3f68b982010-05-04 14:11:35 +05301031 if (slot < edma_cc[ctlr]->num_slots) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001032 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
Kevin Hilmana4768d22009-04-14 07:18:14 -05001033 0xffff0000, src_bidx);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001034 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
Kevin Hilmana4768d22009-04-14 07:18:14 -05001035 0xffff0000, src_cidx);
1036 }
1037}
1038EXPORT_SYMBOL(edma_set_src_index);
1039
1040/**
1041 * edma_set_dest_index - configure DMA destination address indexing
1042 * @slot: parameter RAM slot being configured
1043 * @dest_bidx: byte offset between destination arrays in a frame
1044 * @dest_cidx: byte offset between destination frames in a block
1045 *
1046 * Offsets are specified to support either contiguous or discontiguous
1047 * memory transfers, or repeated access to a hardware register, as needed.
1048 * When accessing hardware registers, both offsets are normally zero.
1049 */
1050void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1051{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001052 unsigned ctlr;
1053
1054 ctlr = EDMA_CTLR(slot);
1055 slot = EDMA_CHAN_SLOT(slot);
1056
Sekhar Nori3f68b982010-05-04 14:11:35 +05301057 if (slot < edma_cc[ctlr]->num_slots) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001058 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
Kevin Hilmana4768d22009-04-14 07:18:14 -05001059 0x0000ffff, dest_bidx << 16);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001060 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
Kevin Hilmana4768d22009-04-14 07:18:14 -05001061 0x0000ffff, dest_cidx << 16);
1062 }
1063}
1064EXPORT_SYMBOL(edma_set_dest_index);
1065
1066/**
1067 * edma_set_transfer_params - configure DMA transfer parameters
1068 * @slot: parameter RAM slot being configured
1069 * @acnt: how many bytes per array (at least one)
1070 * @bcnt: how many arrays per frame (at least one)
1071 * @ccnt: how many frames per block (at least one)
1072 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1073 * the value to reload into bcnt when it decrements to zero
1074 * @sync_mode: ASYNC or ABSYNC
1075 *
1076 * See the EDMA3 documentation to understand how to configure and link
1077 * transfers using the fields in PaRAM slots. If you are not doing it
1078 * all at once with edma_write_slot(), you will use this routine
1079 * plus two calls each for source and destination, setting the initial
1080 * address and saying how to index that address.
1081 *
1082 * An example of an A-Synchronized transfer is a serial link using a
1083 * single word shift register. In that case, @acnt would be equal to
1084 * that word size; the serial controller issues a DMA synchronization
1085 * event to transfer each word, and memory access by the DMA transfer
1086 * controller will be word-at-a-time.
1087 *
1088 * An example of an AB-Synchronized transfer is a device using a FIFO.
1089 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1090 * The controller with the FIFO issues DMA synchronization events when
1091 * the FIFO threshold is reached, and the DMA transfer controller will
1092 * transfer one frame to (or from) the FIFO. It will probably use
1093 * efficient burst modes to access memory.
1094 */
1095void edma_set_transfer_params(unsigned slot,
1096 u16 acnt, u16 bcnt, u16 ccnt,
1097 u16 bcnt_rld, enum sync_dimension sync_mode)
1098{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001099 unsigned ctlr;
1100
1101 ctlr = EDMA_CTLR(slot);
1102 slot = EDMA_CHAN_SLOT(slot);
1103
Sekhar Nori3f68b982010-05-04 14:11:35 +05301104 if (slot < edma_cc[ctlr]->num_slots) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001105 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
Kevin Hilmana4768d22009-04-14 07:18:14 -05001106 0x0000ffff, bcnt_rld << 16);
1107 if (sync_mode == ASYNC)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001108 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001109 else
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001110 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001111 /* Set the acount, bcount, ccount registers */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001112 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1113 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001114 }
1115}
1116EXPORT_SYMBOL(edma_set_transfer_params);
1117
1118/**
1119 * edma_link - link one parameter RAM slot to another
1120 * @from: parameter RAM slot originating the link
1121 * @to: parameter RAM slot which is the link target
1122 *
1123 * The originating slot should not be part of any active DMA transfer.
1124 */
1125void edma_link(unsigned from, unsigned to)
1126{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001127 unsigned ctlr_from, ctlr_to;
1128
1129 ctlr_from = EDMA_CTLR(from);
1130 from = EDMA_CHAN_SLOT(from);
1131 ctlr_to = EDMA_CTLR(to);
1132 to = EDMA_CHAN_SLOT(to);
1133
Sekhar Nori3f68b982010-05-04 14:11:35 +05301134 if (from >= edma_cc[ctlr_from]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001135 return;
Sekhar Nori3f68b982010-05-04 14:11:35 +05301136 if (to >= edma_cc[ctlr_to]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001137 return;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001138 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1139 PARM_OFFSET(to));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001140}
1141EXPORT_SYMBOL(edma_link);
1142
1143/**
1144 * edma_unlink - cut link from one parameter RAM slot
1145 * @from: parameter RAM slot originating the link
1146 *
1147 * The originating slot should not be part of any active DMA transfer.
1148 * Its link is set to 0xffff.
1149 */
1150void edma_unlink(unsigned from)
1151{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001152 unsigned ctlr;
1153
1154 ctlr = EDMA_CTLR(from);
1155 from = EDMA_CHAN_SLOT(from);
1156
Sekhar Nori3f68b982010-05-04 14:11:35 +05301157 if (from >= edma_cc[ctlr]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001158 return;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001159 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001160}
1161EXPORT_SYMBOL(edma_unlink);
1162
1163/*-----------------------------------------------------------------------*/
1164
1165/* Parameter RAM operations (ii) -- read/write whole parameter sets */
1166
1167/**
1168 * edma_write_slot - write parameter RAM data for slot
1169 * @slot: number of parameter RAM slot being modified
1170 * @param: data to be written into parameter RAM slot
1171 *
1172 * Use this to assign all parameters of a transfer at once. This
1173 * allows more efficient setup of transfers than issuing multiple
1174 * calls to set up those parameters in small pieces, and provides
1175 * complete control over all transfer options.
1176 */
1177void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1178{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001179 unsigned ctlr;
1180
1181 ctlr = EDMA_CTLR(slot);
1182 slot = EDMA_CHAN_SLOT(slot);
1183
Sekhar Nori3f68b982010-05-04 14:11:35 +05301184 if (slot >= edma_cc[ctlr]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001185 return;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001186 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1187 PARM_SIZE);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001188}
1189EXPORT_SYMBOL(edma_write_slot);
1190
1191/**
1192 * edma_read_slot - read parameter RAM data from slot
1193 * @slot: number of parameter RAM slot being copied
1194 * @param: where to store copy of parameter RAM data
1195 *
1196 * Use this to read data from a parameter RAM slot, perhaps to
1197 * save them as a template for later reuse.
1198 */
1199void edma_read_slot(unsigned slot, struct edmacc_param *param)
1200{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001201 unsigned ctlr;
1202
1203 ctlr = EDMA_CTLR(slot);
1204 slot = EDMA_CHAN_SLOT(slot);
1205
Sekhar Nori3f68b982010-05-04 14:11:35 +05301206 if (slot >= edma_cc[ctlr]->num_slots)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001207 return;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001208 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1209 PARM_SIZE);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001210}
1211EXPORT_SYMBOL(edma_read_slot);
1212
1213/*-----------------------------------------------------------------------*/
1214
1215/* Various EDMA channel control operations */
1216
1217/**
1218 * edma_pause - pause dma on a channel
1219 * @channel: on which edma_start() has been called
1220 *
1221 * This temporarily disables EDMA hardware events on the specified channel,
1222 * preventing them from triggering new transfers on its behalf
1223 */
1224void edma_pause(unsigned channel)
1225{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001226 unsigned ctlr;
1227
1228 ctlr = EDMA_CTLR(channel);
1229 channel = EDMA_CHAN_SLOT(channel);
1230
Sekhar Nori3f68b982010-05-04 14:11:35 +05301231 if (channel < edma_cc[ctlr]->num_channels) {
Sekhar Norid78a9492010-05-10 12:41:18 +05301232 unsigned int mask = BIT(channel & 0x1f);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001233
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001234 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001235 }
1236}
1237EXPORT_SYMBOL(edma_pause);
1238
1239/**
1240 * edma_resume - resumes dma on a paused channel
1241 * @channel: on which edma_pause() has been called
1242 *
1243 * This re-enables EDMA hardware events on the specified channel.
1244 */
1245void edma_resume(unsigned channel)
1246{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001247 unsigned ctlr;
1248
1249 ctlr = EDMA_CTLR(channel);
1250 channel = EDMA_CHAN_SLOT(channel);
1251
Sekhar Nori3f68b982010-05-04 14:11:35 +05301252 if (channel < edma_cc[ctlr]->num_channels) {
Sekhar Norid78a9492010-05-10 12:41:18 +05301253 unsigned int mask = BIT(channel & 0x1f);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001254
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001255 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001256 }
1257}
1258EXPORT_SYMBOL(edma_resume);
1259
Joel Fernandes96874b92013-08-29 18:05:42 -05001260int edma_trigger_channel(unsigned channel)
1261{
1262 unsigned ctlr;
1263 unsigned int mask;
1264
1265 ctlr = EDMA_CTLR(channel);
1266 channel = EDMA_CHAN_SLOT(channel);
1267 mask = BIT(channel & 0x1f);
1268
1269 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1270
1271 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1272 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1273 return 0;
1274}
1275EXPORT_SYMBOL(edma_trigger_channel);
1276
Kevin Hilmana4768d22009-04-14 07:18:14 -05001277/**
1278 * edma_start - start dma on a channel
1279 * @channel: channel being activated
1280 *
1281 * Channels with event associations will be triggered by their hardware
1282 * events, and channels without such associations will be triggered by
1283 * software. (At this writing there is no interface for using software
1284 * triggers except with channels that don't support hardware triggers.)
1285 *
1286 * Returns zero on success, else negative errno.
1287 */
1288int edma_start(unsigned channel)
1289{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001290 unsigned ctlr;
1291
1292 ctlr = EDMA_CTLR(channel);
1293 channel = EDMA_CHAN_SLOT(channel);
1294
Sekhar Nori3f68b982010-05-04 14:11:35 +05301295 if (channel < edma_cc[ctlr]->num_channels) {
Kevin Hilmana4768d22009-04-14 07:18:14 -05001296 int j = channel >> 5;
Sekhar Norid78a9492010-05-10 12:41:18 +05301297 unsigned int mask = BIT(channel & 0x1f);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001298
1299 /* EDMA channels without event association */
Sekhar Nori3f68b982010-05-04 14:11:35 +05301300 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
Kevin Hilmana4768d22009-04-14 07:18:14 -05001301 pr_debug("EDMA: ESR%d %08x\n", j,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001302 edma_shadow0_read_array(ctlr, SH_ESR, j));
1303 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001304 return 0;
1305 }
1306
1307 /* EDMA channel with event association */
1308 pr_debug("EDMA: ER%d %08x\n", j,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001309 edma_shadow0_read_array(ctlr, SH_ER, j));
Brian Niebuhrbb17ef12010-03-09 16:48:03 -06001310 /* Clear any pending event or error */
1311 edma_write_array(ctlr, EDMA_ECR, j, mask);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001312 edma_write_array(ctlr, EDMA_EMCR, j, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001313 /* Clear any SER */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001314 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1315 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001316 pr_debug("EDMA: EER%d %08x\n", j,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001317 edma_shadow0_read_array(ctlr, SH_EER, j));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001318 return 0;
1319 }
1320
1321 return -EINVAL;
1322}
1323EXPORT_SYMBOL(edma_start);
1324
1325/**
1326 * edma_stop - stops dma on the channel passed
1327 * @channel: channel being deactivated
1328 *
1329 * When @lch is a channel, any active transfer is paused and
1330 * all pending hardware events are cleared. The current transfer
1331 * may not be resumed, and the channel's Parameter RAM should be
1332 * reinitialized before being reused.
1333 */
1334void edma_stop(unsigned channel)
1335{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001336 unsigned ctlr;
1337
1338 ctlr = EDMA_CTLR(channel);
1339 channel = EDMA_CHAN_SLOT(channel);
1340
Sekhar Nori3f68b982010-05-04 14:11:35 +05301341 if (channel < edma_cc[ctlr]->num_channels) {
Kevin Hilmana4768d22009-04-14 07:18:14 -05001342 int j = channel >> 5;
Sekhar Norid78a9492010-05-10 12:41:18 +05301343 unsigned int mask = BIT(channel & 0x1f);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001344
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001345 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1346 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1347 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1348 edma_write_array(ctlr, EDMA_EMCR, j, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001349
1350 pr_debug("EDMA: EER%d %08x\n", j,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001351 edma_shadow0_read_array(ctlr, SH_EER, j));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001352
1353 /* REVISIT: consider guarding against inappropriate event
1354 * chaining by overwriting with dummy_paramset.
1355 */
1356 }
1357}
1358EXPORT_SYMBOL(edma_stop);
1359
1360/******************************************************************************
1361 *
1362 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1363 * been removed before EDMA has finished.It is usedful for removable media.
1364 * Arguments:
1365 * ch_no - channel no
1366 *
1367 * Return: zero on success, or corresponding error no on failure
1368 *
1369 * FIXME this should not be needed ... edma_stop() should suffice.
1370 *
1371 *****************************************************************************/
1372
1373void edma_clean_channel(unsigned channel)
1374{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001375 unsigned ctlr;
1376
1377 ctlr = EDMA_CTLR(channel);
1378 channel = EDMA_CHAN_SLOT(channel);
1379
Sekhar Nori3f68b982010-05-04 14:11:35 +05301380 if (channel < edma_cc[ctlr]->num_channels) {
Kevin Hilmana4768d22009-04-14 07:18:14 -05001381 int j = (channel >> 5);
Sekhar Norid78a9492010-05-10 12:41:18 +05301382 unsigned int mask = BIT(channel & 0x1f);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001383
1384 pr_debug("EDMA: EMR%d %08x\n", j,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001385 edma_read_array(ctlr, EDMA_EMR, j));
1386 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001387 /* Clear the corresponding EMR bits */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001388 edma_write_array(ctlr, EDMA_EMCR, j, mask);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001389 /* Clear any SER */
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001390 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
Sekhar Norid78a9492010-05-10 12:41:18 +05301391 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001392 }
1393}
1394EXPORT_SYMBOL(edma_clean_channel);
1395
1396/*
1397 * edma_clear_event - clear an outstanding event on the DMA channel
1398 * Arguments:
1399 * channel - channel number
1400 */
1401void edma_clear_event(unsigned channel)
1402{
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001403 unsigned ctlr;
1404
1405 ctlr = EDMA_CTLR(channel);
1406 channel = EDMA_CHAN_SLOT(channel);
1407
Sekhar Nori3f68b982010-05-04 14:11:35 +05301408 if (channel >= edma_cc[ctlr]->num_channels)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001409 return;
1410 if (channel < 32)
Sekhar Norid78a9492010-05-10 12:41:18 +05301411 edma_write(ctlr, EDMA_ECR, BIT(channel));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001412 else
Sekhar Norid78a9492010-05-10 12:41:18 +05301413 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001414}
1415EXPORT_SYMBOL(edma_clear_event);
1416
Peter Ujfalusi6d10c392014-05-16 15:17:15 +03001417static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1418 struct edma *edma_cc)
1419{
1420 int i;
1421 u32 value, cccfg;
1422 s8 (*queue_priority_map)[2];
1423
1424 /* Decode the eDMA3 configuration from CCCFG register */
1425 cccfg = edma_read(0, EDMA_CCCFG);
1426
1427 value = GET_NUM_REGN(cccfg);
1428 edma_cc->num_region = BIT(value);
1429
1430 value = GET_NUM_DMACH(cccfg);
1431 edma_cc->num_channels = BIT(value + 1);
1432
1433 value = GET_NUM_PAENTRY(cccfg);
1434 edma_cc->num_slots = BIT(value + 4);
1435
1436 value = GET_NUM_EVQUE(cccfg);
1437 edma_cc->num_tc = value + 1;
1438
1439 dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
1440 dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1441 dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1442 dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
1443 dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
1444
1445 /* Nothing need to be done if queue priority is provided */
1446 if (pdata->queue_priority_mapping)
1447 return 0;
1448
1449 /*
1450 * Configure TC/queue priority as follows:
1451 * Q0 - priority 0
1452 * Q1 - priority 1
1453 * Q2 - priority 2
1454 * ...
1455 * The meaning of priority numbers: 0 highest priority, 7 lowest
1456 * priority. So Q0 is the highest priority queue and the last queue has
1457 * the lowest priority.
1458 */
1459 queue_priority_map = devm_kzalloc(dev,
1460 (edma_cc->num_tc + 1) * sizeof(s8),
1461 GFP_KERNEL);
1462 if (!queue_priority_map)
1463 return -ENOMEM;
1464
1465 for (i = 0; i < edma_cc->num_tc; i++) {
1466 queue_priority_map[i][0] = i;
1467 queue_priority_map[i][1] = i;
1468 }
1469 queue_priority_map[i][0] = -1;
1470 queue_priority_map[i][1] = -1;
1471
1472 pdata->queue_priority_mapping = queue_priority_map;
1473 pdata->default_queue = 0;
1474
1475 return 0;
1476}
1477
Matt Porter6cba4352013-06-20 16:06:38 -05001478#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001479
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001480static int edma_xbar_event_map(struct device *dev, struct device_node *node,
1481 struct edma_soc_info *pdata, size_t sz)
Matt Porter2646a0e2013-06-20 16:06:39 -05001482{
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001483 const char pname[] = "ti,edma-xbar-event-map";
Matt Porter2646a0e2013-06-20 16:06:39 -05001484 struct resource res;
1485 void __iomem *xbar;
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001486 s16 (*xbar_chans)[2];
1487 size_t nelm = sz / sizeof(s16);
Matt Porter2646a0e2013-06-20 16:06:39 -05001488 u32 shift, offset, mux;
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001489 int ret, i;
Matt Porter2646a0e2013-06-20 16:06:39 -05001490
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001491 xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
Matt Porter2646a0e2013-06-20 16:06:39 -05001492 if (!xbar_chans)
1493 return -ENOMEM;
1494
1495 ret = of_address_to_resource(node, 1, &res);
1496 if (ret)
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001497 return -ENOMEM;
Matt Porter2646a0e2013-06-20 16:06:39 -05001498
1499 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1500 if (!xbar)
1501 return -ENOMEM;
1502
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001503 ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
Matt Porter2646a0e2013-06-20 16:06:39 -05001504 if (ret)
1505 return -EIO;
1506
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001507 /* Invalidate last entry for the other user of this mess */
1508 nelm >>= 1;
1509 xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
1510
1511 for (i = 0; i < nelm; i++) {
Matt Porter2646a0e2013-06-20 16:06:39 -05001512 shift = (xbar_chans[i][1] & 0x03) << 3;
1513 offset = xbar_chans[i][1] & 0xfffffffc;
1514 mux = readl(xbar + offset);
1515 mux &= ~(0xff << shift);
1516 mux |= xbar_chans[i][0] << shift;
1517 writel(mux, (xbar + offset));
1518 }
1519
Thomas Gleixnercf7eb972014-04-13 20:44:46 +02001520 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
Matt Porter2646a0e2013-06-20 16:06:39 -05001521 return 0;
1522}
1523
Matt Porter6cba4352013-06-20 16:06:38 -05001524static int edma_of_parse_dt(struct device *dev,
1525 struct device_node *node,
1526 struct edma_soc_info *pdata)
1527{
Peter Ujfalusi6d10c392014-05-16 15:17:15 +03001528 int ret = 0;
Matt Porter2646a0e2013-06-20 16:06:39 -05001529 struct property *prop;
1530 size_t sz;
Matt Porter6cba4352013-06-20 16:06:38 -05001531 struct edma_rsv_info *rsv_info;
Matt Porter6cba4352013-06-20 16:06:38 -05001532
1533 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1534 if (!rsv_info)
1535 return -ENOMEM;
1536 pdata->rsv = rsv_info;
1537
Matt Porter2646a0e2013-06-20 16:06:39 -05001538 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1539 if (prop)
1540 ret = edma_xbar_event_map(dev, node, pdata, sz);
1541
Matt Porter6cba4352013-06-20 16:06:38 -05001542 return ret;
1543}
1544
1545static struct of_dma_filter_info edma_filter_info = {
1546 .filter_fn = edma_filter_fn,
1547};
1548
1549static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1550 struct device_node *node)
1551{
1552 struct edma_soc_info *info;
1553 int ret;
1554
1555 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1556 if (!info)
1557 return ERR_PTR(-ENOMEM);
1558
1559 ret = edma_of_parse_dt(dev, node, info);
1560 if (ret)
1561 return ERR_PTR(ret);
1562
1563 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
Peter Ujfalusi232b223d2014-04-14 14:42:00 +03001564 dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
Matt Porter6cba4352013-06-20 16:06:38 -05001565 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1566 &edma_filter_info);
1567
1568 return info;
1569}
1570#else
1571static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1572 struct device_node *node)
1573{
1574 return ERR_PTR(-ENOSYS);
1575}
1576#endif
1577
1578static int edma_probe(struct platform_device *pdev)
Kevin Hilmana4768d22009-04-14 07:18:14 -05001579{
Sekhar Noribc3ac9f2010-06-29 11:35:12 +05301580 struct edma_soc_info **info = pdev->dev.platform_data;
Matt Porter6cba4352013-06-20 16:06:38 -05001581 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1582 s8 (*queue_priority_mapping)[2];
Rajashekhara, Sudhakar90bd4e62010-06-29 11:35:13 +05301583 int i, j, off, ln, found = 0;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001584 int status = -1;
Rajashekhara, Sudhakar90bd4e62010-06-29 11:35:13 +05301585 const s16 (*rsv_chans)[2];
1586 const s16 (*rsv_slots)[2];
Matt Porter2646a0e2013-06-20 16:06:39 -05001587 const s16 (*xbar_chans)[2];
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001588 int irq[EDMA_MAX_CC] = {0, 0};
1589 int err_irq[EDMA_MAX_CC] = {0, 0};
1590 struct resource *r[EDMA_MAX_CC] = {NULL};
Matt Porter6cba4352013-06-20 16:06:38 -05001591 struct resource res[EDMA_MAX_CC];
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001592 char res_name[10];
Matt Porter6cba4352013-06-20 16:06:38 -05001593 struct device_node *node = pdev->dev.of_node;
1594 struct device *dev = &pdev->dev;
1595 int ret;
1596
1597 if (node) {
1598 /* Check if this is a second instance registered */
1599 if (arch_num_cc) {
1600 dev_err(dev, "only one EDMA instance is supported via DT\n");
1601 return -ENODEV;
1602 }
1603
1604 ninfo[0] = edma_setup_info_from_dt(dev, node);
1605 if (IS_ERR(ninfo[0])) {
1606 dev_err(dev, "failed to get DT data\n");
1607 return PTR_ERR(ninfo[0]);
1608 }
1609
1610 info = ninfo;
1611 }
Kevin Hilmana4768d22009-04-14 07:18:14 -05001612
1613 if (!info)
1614 return -ENODEV;
1615
Matt Porter6cba4352013-06-20 16:06:38 -05001616 pm_runtime_enable(dev);
1617 ret = pm_runtime_get_sync(dev);
1618 if (ret < 0) {
1619 dev_err(dev, "pm_runtime_get_sync() failed\n");
1620 return ret;
1621 }
1622
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001623 for (j = 0; j < EDMA_MAX_CC; j++) {
Matt Porter6cba4352013-06-20 16:06:38 -05001624 if (!info[j]) {
1625 if (!found)
1626 return -ENODEV;
1627 break;
1628 }
1629 if (node) {
1630 ret = of_address_to_resource(node, j, &res[j]);
1631 if (!ret)
1632 r[j] = &res[j];
1633 } else {
1634 sprintf(res_name, "edma_cc%d", j);
1635 r[j] = platform_get_resource_byname(pdev,
1636 IORESOURCE_MEM,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001637 res_name);
Matt Porter6cba4352013-06-20 16:06:38 -05001638 }
1639 if (!r[j]) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001640 if (found)
1641 break;
1642 else
1643 return -ENODEV;
Sekhar Nori243bc652010-05-04 14:11:36 +05301644 } else {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001645 found = 1;
Sekhar Nori243bc652010-05-04 14:11:36 +05301646 }
Kevin Hilmana4768d22009-04-14 07:18:14 -05001647
Lad, Prabhakare7eff702013-06-17 20:27:58 +05301648 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1649 if (IS_ERR(edmacc_regs_base[j]))
1650 return PTR_ERR(edmacc_regs_base[j]);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001651
Lad, Prabhakare7eff702013-06-17 20:27:58 +05301652 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1653 GFP_KERNEL);
1654 if (!edma_cc[j])
1655 return -ENOMEM;
Kevin Hilmana4768d22009-04-14 07:18:14 -05001656
Peter Ujfalusi6d10c392014-05-16 15:17:15 +03001657 /* Get eDMA3 configuration from IP */
1658 ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
1659 if (ret)
1660 return ret;
Kevin Hilmana4768d22009-04-14 07:18:14 -05001661
Sekhar Noribc3ac9f2010-06-29 11:35:12 +05301662 edma_cc[j]->default_queue = info[j]->default_queue;
Sandeep Paulraja0f02022009-07-27 09:57:07 -04001663
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001664 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1665 edmacc_regs_base[j]);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001666
Sekhar Nori3f68b982010-05-04 14:11:35 +05301667 for (i = 0; i < edma_cc[j]->num_slots; i++)
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001668 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1669 &dummy_paramset, PARM_SIZE);
Kevin Hilmana4768d22009-04-14 07:18:14 -05001670
Sudhakar Rajashekharaf900d552010-01-06 17:29:49 +05301671 /* Mark all channels as unused */
Sekhar Nori3f68b982010-05-04 14:11:35 +05301672 memset(edma_cc[j]->edma_unused, 0xff,
1673 sizeof(edma_cc[j]->edma_unused));
Kevin Hilmana4768d22009-04-14 07:18:14 -05001674
Rajashekhara, Sudhakar90bd4e62010-06-29 11:35:13 +05301675 if (info[j]->rsv) {
1676
1677 /* Clear the reserved channels in unused list */
1678 rsv_chans = info[j]->rsv->rsv_chans;
1679 if (rsv_chans) {
1680 for (i = 0; rsv_chans[i][0] != -1; i++) {
1681 off = rsv_chans[i][0];
1682 ln = rsv_chans[i][1];
1683 clear_bits(off, ln,
Matt Porter6cba4352013-06-20 16:06:38 -05001684 edma_cc[j]->edma_unused);
Rajashekhara, Sudhakar90bd4e62010-06-29 11:35:13 +05301685 }
1686 }
1687
1688 /* Set the reserved slots in inuse list */
1689 rsv_slots = info[j]->rsv->rsv_slots;
1690 if (rsv_slots) {
1691 for (i = 0; rsv_slots[i][0] != -1; i++) {
1692 off = rsv_slots[i][0];
1693 ln = rsv_slots[i][1];
1694 set_bits(off, ln,
1695 edma_cc[j]->edma_inuse);
1696 }
1697 }
1698 }
1699
Matt Porter2646a0e2013-06-20 16:06:39 -05001700 /* Clear the xbar mapped channels in unused list */
1701 xbar_chans = info[j]->xbar_chans;
1702 if (xbar_chans) {
1703 for (i = 0; xbar_chans[i][1] != -1; i++) {
1704 off = xbar_chans[i][1];
1705 clear_bits(off, 1,
1706 edma_cc[j]->edma_unused);
1707 }
1708 }
Matt Porter6cba4352013-06-20 16:06:38 -05001709
1710 if (node) {
1711 irq[j] = irq_of_parse_and_map(node, 0);
Peter Ujfalusi44161762014-05-13 10:26:01 +03001712 err_irq[j] = irq_of_parse_and_map(node, 2);
Matt Porter6cba4352013-06-20 16:06:38 -05001713 } else {
Peter Ujfalusi44161762014-05-13 10:26:01 +03001714 char irq_name[10];
1715
Matt Porter6cba4352013-06-20 16:06:38 -05001716 sprintf(irq_name, "edma%d", j);
1717 irq[j] = platform_get_irq_byname(pdev, irq_name);
Peter Ujfalusi44161762014-05-13 10:26:01 +03001718
1719 sprintf(irq_name, "edma%d_err", j);
1720 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
Matt Porter6cba4352013-06-20 16:06:38 -05001721 }
Sekhar Nori3f68b982010-05-04 14:11:35 +05301722 edma_cc[j]->irq_res_start = irq[j];
Peter Ujfalusi44161762014-05-13 10:26:01 +03001723 edma_cc[j]->irq_res_end = err_irq[j];
1724
1725 status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
1726 "edma", dev);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001727 if (status < 0) {
Lad, Prabhakare7eff702013-06-17 20:27:58 +05301728 dev_dbg(&pdev->dev,
1729 "devm_request_irq %d failed --> %d\n",
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001730 irq[j], status);
Lad, Prabhakare7eff702013-06-17 20:27:58 +05301731 return status;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001732 }
1733
Peter Ujfalusi44161762014-05-13 10:26:01 +03001734 status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
1735 "edma_error", dev);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001736 if (status < 0) {
Lad, Prabhakare7eff702013-06-17 20:27:58 +05301737 dev_dbg(&pdev->dev,
1738 "devm_request_irq %d failed --> %d\n",
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001739 err_irq[j], status);
Lad, Prabhakare7eff702013-06-17 20:27:58 +05301740 return status;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001741 }
1742
Sekhar Nori3f68b982010-05-04 14:11:35 +05301743 for (i = 0; i < edma_cc[j]->num_channels; i++)
Heiko Schocher0b7580b2012-01-19 08:05:21 +01001744 map_dmach_queue(j, i, info[j]->default_queue);
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001745
Sekhar Noribc3ac9f2010-06-29 11:35:12 +05301746 queue_priority_mapping = info[j]->queue_priority_mapping;
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001747
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001748 /* Event queue priority mapping */
1749 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1750 assign_priority_to_queue(j,
1751 queue_priority_mapping[i][0],
1752 queue_priority_mapping[i][1]);
1753
1754 /* Map the channel to param entry if channel mapping logic
1755 * exist
1756 */
1757 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1758 map_dmach_param(j);
1759
Peter Ujfalusi643efcf2014-05-16 15:17:14 +03001760 for (i = 0; i < edma_cc[j]->num_region; i++) {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -04001761 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1762 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1763 edma_write_array(j, EDMA_QRAE, i, 0x0);
1764 }
Sudhakar Rajashekhara2d517502010-01-06 17:28:44 +05301765 arch_num_cc++;
Kevin Hilmana4768d22009-04-14 07:18:14 -05001766 }
1767
Kevin Hilmana4768d22009-04-14 07:18:14 -05001768 return 0;
Kevin Hilmana4768d22009-04-14 07:18:14 -05001769}
1770
Kevin Hilmana4768d22009-04-14 07:18:14 -05001771static struct platform_driver edma_driver = {
Matt Porter6cba4352013-06-20 16:06:38 -05001772 .driver = {
1773 .name = "edma",
1774 .of_match_table = edma_of_ids,
1775 },
1776 .probe = edma_probe,
Kevin Hilmana4768d22009-04-14 07:18:14 -05001777};
1778
1779static int __init edma_init(void)
1780{
1781 return platform_driver_probe(&edma_driver, edma_probe);
1782}
1783arch_initcall(edma_init);
1784