blob: cc9afb733b48cd31a0da94f05771c0d04c0531ba [file] [log] [blame]
Philipp Zabel79924ca2014-07-23 12:28:45 -03001/*
2 * Coda multi-standard codec IP - BIT processor functions
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/clk.h>
16#include <linux/irqreturn.h>
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19#include <linux/reset.h>
20#include <linux/videodev2.h>
21
22#include <media/v4l2-common.h>
23#include <media/v4l2-ctrls.h>
24#include <media/v4l2-fh.h>
25#include <media/v4l2-mem2mem.h>
26#include <media/videobuf2-core.h>
27#include <media/videobuf2-dma-contig.h>
28#include <media/videobuf2-vmalloc.h>
29
30#include "coda.h"
31
32#define CODA7_PS_BUF_SIZE 0x28000
33#define CODA9_PS_SAVE_SIZE (512 * 1024)
34
35#define CODA_DEFAULT_GAMMA 4096
36#define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
37
38static inline int coda_is_initialized(struct coda_dev *dev)
39{
40 return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
41}
42
43static inline unsigned long coda_isbusy(struct coda_dev *dev)
44{
45 return coda_read(dev, CODA_REG_BIT_BUSY);
46}
47
48static int coda_wait_timeout(struct coda_dev *dev)
49{
50 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
51
52 while (coda_isbusy(dev)) {
53 if (time_after(jiffies, timeout))
54 return -ETIMEDOUT;
55 }
56 return 0;
57}
58
59static void coda_command_async(struct coda_ctx *ctx, int cmd)
60{
61 struct coda_dev *dev = ctx->dev;
62
63 if (dev->devtype->product == CODA_960 ||
64 dev->devtype->product == CODA_7541) {
65 /* Restore context related registers to CODA */
66 coda_write(dev, ctx->bit_stream_param,
67 CODA_REG_BIT_BIT_STREAM_PARAM);
68 coda_write(dev, ctx->frm_dis_flg,
69 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
70 coda_write(dev, ctx->frame_mem_ctrl,
71 CODA_REG_BIT_FRAME_MEM_CTRL);
72 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
73 }
74
75 if (dev->devtype->product == CODA_960) {
76 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
77 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
78 }
79
80 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
81
82 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
83 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
84 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
85
86 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
87}
88
89static int coda_command_sync(struct coda_ctx *ctx, int cmd)
90{
91 struct coda_dev *dev = ctx->dev;
92
93 coda_command_async(ctx, cmd);
94 return coda_wait_timeout(dev);
95}
96
97int coda_hw_reset(struct coda_ctx *ctx)
98{
99 struct coda_dev *dev = ctx->dev;
100 unsigned long timeout;
101 unsigned int idx;
102 int ret;
103
104 if (!dev->rstc)
105 return -ENOENT;
106
107 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
108
109 if (dev->devtype->product == CODA_960) {
110 timeout = jiffies + msecs_to_jiffies(100);
111 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
112 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
113 if (time_after(jiffies, timeout))
114 return -ETIME;
115 cpu_relax();
116 }
117 }
118
119 ret = reset_control_reset(dev->rstc);
120 if (ret < 0)
121 return ret;
122
123 if (dev->devtype->product == CODA_960)
124 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
125 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
126 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
127 ret = coda_wait_timeout(dev);
128 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
129
130 return ret;
131}
132
133static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
134{
135 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
136 struct coda_dev *dev = ctx->dev;
137 u32 rd_ptr;
138
139 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
140 kfifo->out = (kfifo->in & ~kfifo->mask) |
141 (rd_ptr - ctx->bitstream.paddr);
142 if (kfifo->out > kfifo->in)
143 kfifo->out -= kfifo->mask + 1;
144}
145
146static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
147{
148 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
149 struct coda_dev *dev = ctx->dev;
150 u32 rd_ptr, wr_ptr;
151
152 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
153 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
154 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
155 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
156}
157
158static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
159{
160 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
161 struct coda_dev *dev = ctx->dev;
162 u32 wr_ptr;
163
164 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
165 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
166}
167
168static int coda_bitstream_queue(struct coda_ctx *ctx, struct vb2_buffer *src_buf)
169{
170 u32 src_size = vb2_get_plane_payload(src_buf, 0);
171 u32 n;
172
173 n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0), src_size);
174 if (n < src_size)
175 return -ENOSPC;
176
177 dma_sync_single_for_device(&ctx->dev->plat_dev->dev, ctx->bitstream.paddr,
178 ctx->bitstream.size, DMA_TO_DEVICE);
179
180 src_buf->v4l2_buf.sequence = ctx->qsequence++;
181
182 return 0;
183}
184
185static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
186 struct vb2_buffer *src_buf)
187{
188 int ret;
189
190 if (coda_get_bitstream_payload(ctx) +
191 vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
192 return false;
193
194 if (vb2_plane_vaddr(src_buf, 0) == NULL) {
195 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
196 return true;
197 }
198
199 ret = coda_bitstream_queue(ctx, src_buf);
200 if (ret < 0) {
201 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
202 return false;
203 }
204 /* Sync read pointer to device */
205 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
206 coda_kfifo_sync_to_device_write(ctx);
207
208 ctx->hold = false;
209
210 return true;
211}
212
213void coda_fill_bitstream(struct coda_ctx *ctx)
214{
215 struct vb2_buffer *src_buf;
216 struct coda_timestamp *ts;
217
218 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
219 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
220
221 if (coda_bitstream_try_queue(ctx, src_buf)) {
222 /*
223 * Source buffer is queued in the bitstream ringbuffer;
224 * queue the timestamp and mark source buffer as done
225 */
226 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
227
228 ts = kmalloc(sizeof(*ts), GFP_KERNEL);
229 if (ts) {
230 ts->sequence = src_buf->v4l2_buf.sequence;
231 ts->timecode = src_buf->v4l2_buf.timecode;
232 ts->timestamp = src_buf->v4l2_buf.timestamp;
233 list_add_tail(&ts->list, &ctx->timestamp_list);
234 }
235
236 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
237 } else {
238 break;
239 }
240 }
241}
242
243void coda_bit_stream_end_flag(struct coda_ctx *ctx)
244{
245 struct coda_dev *dev = ctx->dev;
246
247 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
248
249 if ((dev->devtype->product == CODA_960) &&
250 coda_isbusy(dev) &&
251 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
252 /* If this context is currently running, update the hardware flag */
253 coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM);
254 }
255}
256
257static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
258{
259 struct coda_dev *dev = ctx->dev;
260 u32 *p = ctx->parabuf.vaddr;
261
262 if (dev->devtype->product == CODA_DX6)
263 p[index] = value;
264 else
265 p[index ^ 1] = value;
266}
267
268static void coda_free_framebuffers(struct coda_ctx *ctx)
269{
270 int i;
271
272 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
273 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
274}
275
276static int coda_alloc_framebuffers(struct coda_ctx *ctx,
277 struct coda_q_data *q_data, u32 fourcc)
278{
279 struct coda_dev *dev = ctx->dev;
280 int width, height;
281 dma_addr_t paddr;
282 int ysize;
283 int ret;
284 int i;
285
286 if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
287 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
288 width = round_up(q_data->width, 16);
289 height = round_up(q_data->height, 16);
290 } else {
291 width = round_up(q_data->width, 8);
292 height = q_data->height;
293 }
294 ysize = width * height;
295
296 /* Allocate frame buffers */
297 for (i = 0; i < ctx->num_internal_frames; i++) {
298 size_t size;
299 char *name;
300
301 size = ysize + ysize / 2;
302 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
303 dev->devtype->product != CODA_DX6)
304 size += ysize / 4;
305 name = kasprintf(GFP_KERNEL, "fb%d", i);
306 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
307 size, name);
308 kfree(name);
309 if (ret < 0) {
310 coda_free_framebuffers(ctx);
311 return ret;
312 }
313 }
314
315 /* Register frame buffers in the parameter buffer */
316 for (i = 0; i < ctx->num_internal_frames; i++) {
317 paddr = ctx->internal_frames[i].paddr;
318 coda_parabuf_write(ctx, i * 3 + 0, paddr); /* Y */
319 coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize); /* Cb */
320 coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize/4); /* Cr */
321
322 /* mvcol buffer for h.264 */
323 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
324 dev->devtype->product != CODA_DX6)
325 coda_parabuf_write(ctx, 96 + i,
326 ctx->internal_frames[i].paddr +
327 ysize + ysize/4 + ysize/4);
328 }
329
330 /* mvcol buffer for mpeg4 */
331 if ((dev->devtype->product != CODA_DX6) &&
332 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
333 coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
334 ysize + ysize/4 + ysize/4);
335
336 return 0;
337}
338
339static void coda_free_context_buffers(struct coda_ctx *ctx)
340{
341 struct coda_dev *dev = ctx->dev;
342
343 coda_free_aux_buf(dev, &ctx->slicebuf);
344 coda_free_aux_buf(dev, &ctx->psbuf);
345 if (dev->devtype->product != CODA_DX6)
346 coda_free_aux_buf(dev, &ctx->workbuf);
347}
348
349static int coda_alloc_context_buffers(struct coda_ctx *ctx,
350 struct coda_q_data *q_data)
351{
352 struct coda_dev *dev = ctx->dev;
353 size_t size;
354 int ret;
355
356 if (dev->devtype->product == CODA_DX6)
357 return 0;
358
359 if (ctx->psbuf.vaddr) {
360 v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
361 return -EBUSY;
362 }
363 if (ctx->slicebuf.vaddr) {
364 v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
365 return -EBUSY;
366 }
367 if (ctx->workbuf.vaddr) {
368 v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
369 ret = -EBUSY;
370 return -ENOMEM;
371 }
372
373 if (q_data->fourcc == V4L2_PIX_FMT_H264) {
374 /* worst case slice size */
375 size = (DIV_ROUND_UP(q_data->width, 16) *
376 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
377 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size, "slicebuf");
378 if (ret < 0) {
379 v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte slice buffer",
380 ctx->slicebuf.size);
381 return ret;
382 }
383 }
384
385 if (dev->devtype->product == CODA_7541) {
386 ret = coda_alloc_context_buf(ctx, &ctx->psbuf, CODA7_PS_BUF_SIZE, "psbuf");
387 if (ret < 0) {
388 v4l2_err(&dev->v4l2_dev, "failed to allocate psmem buffer");
389 goto err;
390 }
391 }
392
393 size = dev->devtype->workbuf_size;
394 if (dev->devtype->product == CODA_960 &&
395 q_data->fourcc == V4L2_PIX_FMT_H264)
396 size += CODA9_PS_SAVE_SIZE;
397 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
398 if (ret < 0) {
399 v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte context buffer",
400 ctx->workbuf.size);
401 goto err;
402 }
403
404 return 0;
405
406err:
407 coda_free_context_buffers(ctx);
408 return ret;
409}
410
411static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
412 int header_code, u8 *header, int *size)
413{
414 struct coda_dev *dev = ctx->dev;
415 size_t bufsize;
416 int ret;
417 int i;
418
419 if (dev->devtype->product == CODA_960)
420 memset(vb2_plane_vaddr(buf, 0), 0, 64);
421
422 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
423 CODA_CMD_ENC_HEADER_BB_START);
424 bufsize = vb2_plane_size(buf, 0);
425 if (dev->devtype->product == CODA_960)
426 bufsize /= 1024;
427 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
428 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
429 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
430 if (ret < 0) {
431 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
432 return ret;
433 }
434
435 if (dev->devtype->product == CODA_960) {
436 for (i = 63; i > 0; i--)
437 if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
438 break;
439 *size = i + 1;
440 } else {
441 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
442 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
443 }
444 memcpy(header, vb2_plane_vaddr(buf, 0), *size);
445
446 return 0;
447}
448
449static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
450{
451 phys_addr_t ret;
452
453 size = round_up(size, 1024);
454 if (size > iram->remaining)
455 return 0;
456 iram->remaining -= size;
457
458 ret = iram->next_paddr;
459 iram->next_paddr += size;
460
461 return ret;
462}
463
464static void coda_setup_iram(struct coda_ctx *ctx)
465{
466 struct coda_iram_info *iram_info = &ctx->iram_info;
467 struct coda_dev *dev = ctx->dev;
468 int mb_width;
469 int dbk_bits;
470 int bit_bits;
471 int ip_bits;
472
473 memset(iram_info, 0, sizeof(*iram_info));
474 iram_info->next_paddr = dev->iram.paddr;
475 iram_info->remaining = dev->iram.size;
476
477 switch (dev->devtype->product) {
478 case CODA_7541:
479 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
480 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
481 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
482 break;
483 case CODA_960:
484 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
485 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
486 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
487 break;
488 default: /* CODA_DX6 */
489 return;
490 }
491
492 if (ctx->inst_type == CODA_INST_ENCODER) {
493 struct coda_q_data *q_data_src;
494
495 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
496 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
497
498 /* Prioritize in case IRAM is too small for everything */
499 if (dev->devtype->product == CODA_7541) {
500 iram_info->search_ram_size = round_up(mb_width * 16 *
501 36 + 2048, 1024);
502 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
503 iram_info->search_ram_size);
504 if (!iram_info->search_ram_paddr) {
505 pr_err("IRAM is smaller than the search ram size\n");
506 goto out;
507 }
508 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
509 CODA7_USE_ME_ENABLE;
510 }
511
512 /* Only H.264BP and H.263P3 are considered */
513 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, 64 * mb_width);
514 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, 64 * mb_width);
515 if (!iram_info->buf_dbk_c_use)
516 goto out;
517 iram_info->axi_sram_use |= dbk_bits;
518
519 iram_info->buf_bit_use = coda_iram_alloc(iram_info, 128 * mb_width);
520 if (!iram_info->buf_bit_use)
521 goto out;
522 iram_info->axi_sram_use |= bit_bits;
523
524 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, 128 * mb_width);
525 if (!iram_info->buf_ip_ac_dc_use)
526 goto out;
527 iram_info->axi_sram_use |= ip_bits;
528
529 /* OVL and BTP disabled for encoder */
530 } else if (ctx->inst_type == CODA_INST_DECODER) {
531 struct coda_q_data *q_data_dst;
532
533 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
534 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
535
536 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, 128 * mb_width);
537 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, 128 * mb_width);
538 if (!iram_info->buf_dbk_c_use)
539 goto out;
540 iram_info->axi_sram_use |= dbk_bits;
541
542 iram_info->buf_bit_use = coda_iram_alloc(iram_info, 128 * mb_width);
543 if (!iram_info->buf_bit_use)
544 goto out;
545 iram_info->axi_sram_use |= bit_bits;
546
547 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, 128 * mb_width);
548 if (!iram_info->buf_ip_ac_dc_use)
549 goto out;
550 iram_info->axi_sram_use |= ip_bits;
551
552 /* OVL and BTP unused as there is no VC1 support yet */
553 }
554
555out:
556 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
557 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
558 "IRAM smaller than needed\n");
559
560 if (dev->devtype->product == CODA_7541) {
561 /* TODO - Enabling these causes picture errors on CODA7541 */
562 if (ctx->inst_type == CODA_INST_DECODER) {
563 /* fw 1.4.50 */
564 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
565 CODA7_USE_IP_ENABLE);
566 } else {
567 /* fw 13.4.29 */
568 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
569 CODA7_USE_HOST_DBK_ENABLE |
570 CODA7_USE_IP_ENABLE |
571 CODA7_USE_DBK_ENABLE);
572 }
573 }
574}
575
576static u32 coda_supported_firmwares[] = {
577 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
578 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
579 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
580};
581
582static bool coda_firmware_supported(u32 vernum)
583{
584 int i;
585
586 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
587 if (vernum == coda_supported_firmwares[i])
588 return true;
589 return false;
590}
591
592int coda_check_firmware(struct coda_dev *dev)
593{
594 u16 product, major, minor, release;
595 u32 data;
596 int ret;
597
598 ret = clk_prepare_enable(dev->clk_per);
599 if (ret)
600 goto err_clk_per;
601
602 ret = clk_prepare_enable(dev->clk_ahb);
603 if (ret)
604 goto err_clk_ahb;
605
606 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
607 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
608 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
609 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
610 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
611 if (coda_wait_timeout(dev)) {
612 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
613 ret = -EIO;
614 goto err_run_cmd;
615 }
616
617 if (dev->devtype->product == CODA_960) {
618 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
619 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
620 data);
621 }
622
623 /* Check we are compatible with the loaded firmware */
624 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
625 product = CODA_FIRMWARE_PRODUCT(data);
626 major = CODA_FIRMWARE_MAJOR(data);
627 minor = CODA_FIRMWARE_MINOR(data);
628 release = CODA_FIRMWARE_RELEASE(data);
629
630 clk_disable_unprepare(dev->clk_per);
631 clk_disable_unprepare(dev->clk_ahb);
632
633 if (product != dev->devtype->product) {
634 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
635 " Version: %u.%u.%u\n",
636 coda_product_name(dev->devtype->product),
637 coda_product_name(product), major, minor, release);
638 return -EINVAL;
639 }
640
641 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
642 coda_product_name(product));
643
644 if (coda_firmware_supported(data)) {
645 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
646 major, minor, release);
647 } else {
648 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
649 "%u.%u.%u\n", major, minor, release);
650 }
651
652 return 0;
653
654err_run_cmd:
655 clk_disable_unprepare(dev->clk_ahb);
656err_clk_ahb:
657 clk_disable_unprepare(dev->clk_per);
658err_clk_per:
659 return ret;
660}
661
662/*
663 * Encoder context operations
664 */
665
666static int coda_start_encoding(struct coda_ctx *ctx)
667{
668 struct coda_dev *dev = ctx->dev;
669 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
670 struct coda_q_data *q_data_src, *q_data_dst;
671 u32 bitstream_buf, bitstream_size;
672 struct vb2_buffer *buf;
673 int gamma, ret, value;
674 u32 dst_fourcc;
675
676 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
677 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
678 dst_fourcc = q_data_dst->fourcc;
679
680 /* Allocate per-instance buffers */
681 ret = coda_alloc_context_buffers(ctx, q_data_src);
682 if (ret < 0)
683 return ret;
684
685 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
686 bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
687 bitstream_size = q_data_dst->sizeimage;
688
689 if (!coda_is_initialized(dev)) {
690 v4l2_err(v4l2_dev, "coda is not initialized.\n");
691 return -EFAULT;
692 }
693
694 mutex_lock(&dev->coda_mutex);
695
696 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
697 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
698 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
699 switch (dev->devtype->product) {
700 case CODA_DX6:
701 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
702 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
703 break;
704 case CODA_960:
705 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
706 /* fallthrough */
707 case CODA_7541:
708 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
709 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
710 break;
711 }
712
713 value = coda_read(dev, CODA_REG_BIT_FRAME_MEM_CTRL);
714 value &= ~(1 << 2 | 0x7 << 9);
715 ctx->frame_mem_ctrl = value;
716 coda_write(dev, value, CODA_REG_BIT_FRAME_MEM_CTRL);
717
718 if (dev->devtype->product == CODA_DX6) {
719 /* Configure the coda */
720 coda_write(dev, dev->iram.paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
721 }
722
723 /* Could set rotation here if needed */
724 switch (dev->devtype->product) {
725 case CODA_DX6:
726 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
727 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
728 break;
729 case CODA_7541:
730 if (dst_fourcc == V4L2_PIX_FMT_H264) {
731 value = (round_up(q_data_src->width, 16) &
732 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
733 value |= (round_up(q_data_src->height, 16) &
734 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
735 break;
736 }
737 /* fallthrough */
738 case CODA_960:
739 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
740 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
741 }
742 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
743 coda_write(dev, ctx->params.framerate,
744 CODA_CMD_ENC_SEQ_SRC_F_RATE);
745
746 ctx->params.codec_mode = ctx->codec->mode;
747 switch (dst_fourcc) {
748 case V4L2_PIX_FMT_MPEG4:
749 if (dev->devtype->product == CODA_960)
750 coda_write(dev, CODA9_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
751 else
752 coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
753 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
754 break;
755 case V4L2_PIX_FMT_H264:
756 if (dev->devtype->product == CODA_960)
757 coda_write(dev, CODA9_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
758 else
759 coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
760 if (ctx->params.h264_deblk_enabled) {
761 value = ((ctx->params.h264_deblk_alpha &
762 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
763 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
764 ((ctx->params.h264_deblk_beta &
765 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
766 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
767 } else {
768 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
769 }
770 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
771 break;
772 default:
773 v4l2_err(v4l2_dev,
774 "dst format (0x%08x) invalid.\n", dst_fourcc);
775 ret = -EINVAL;
776 goto out;
777 }
778
779 switch (ctx->params.slice_mode) {
780 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
781 value = 0;
782 break;
783 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
784 value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
785 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
786 value |= 1 & CODA_SLICING_MODE_MASK;
787 break;
788 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
789 value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
790 value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
791 value |= 1 & CODA_SLICING_MODE_MASK;
792 break;
793 }
794 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
795 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
796 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
797
798 if (ctx->params.bitrate) {
799 /* Rate control enabled */
800 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
801 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
802 if (dev->devtype->product == CODA_960)
803 value |= BIT(31); /* disable autoskip */
804 } else {
805 value = 0;
806 }
807 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
808
809 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
810 coda_write(dev, ctx->params.intra_refresh,
811 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
812
813 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
814 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
815
816
817 value = 0;
818 if (dev->devtype->product == CODA_960)
819 gamma = CODA9_DEFAULT_GAMMA;
820 else
821 gamma = CODA_DEFAULT_GAMMA;
822 if (gamma > 0) {
823 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
824 CODA_CMD_ENC_SEQ_RC_GAMMA);
825 }
826
827 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
828 coda_write(dev,
829 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
830 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
831 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
832 }
833 if (dev->devtype->product == CODA_960) {
834 if (ctx->params.h264_max_qp)
835 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
836 if (CODA_DEFAULT_GAMMA > 0)
837 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
838 } else {
839 if (CODA_DEFAULT_GAMMA > 0) {
840 if (dev->devtype->product == CODA_DX6)
841 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
842 else
843 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
844 }
845 if (ctx->params.h264_min_qp)
846 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
847 if (ctx->params.h264_max_qp)
848 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
849 }
850 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
851
852 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
853
854 coda_setup_iram(ctx);
855
856 if (dst_fourcc == V4L2_PIX_FMT_H264) {
857 switch (dev->devtype->product) {
858 case CODA_DX6:
859 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
860 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
861 break;
862 case CODA_7541:
863 coda_write(dev, ctx->iram_info.search_ram_paddr,
864 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
865 coda_write(dev, ctx->iram_info.search_ram_size,
866 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
867 break;
868 case CODA_960:
869 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
870 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
871 }
872 }
873
874 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
875 if (ret < 0) {
876 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
877 goto out;
878 }
879
880 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
881 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
882 ret = -EFAULT;
883 goto out;
884 }
885
886 if (dev->devtype->product == CODA_960)
887 ctx->num_internal_frames = 4;
888 else
889 ctx->num_internal_frames = 2;
890 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
891 if (ret < 0) {
892 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
893 goto out;
894 }
895
896 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
897 coda_write(dev, q_data_src->bytesperline,
898 CODA_CMD_SET_FRAME_BUF_STRIDE);
899 if (dev->devtype->product == CODA_7541) {
900 coda_write(dev, q_data_src->bytesperline,
901 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
902 }
903 if (dev->devtype->product != CODA_DX6) {
904 coda_write(dev, ctx->iram_info.buf_bit_use,
905 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
906 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
907 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
908 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
909 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
910 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
911 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
912 coda_write(dev, ctx->iram_info.buf_ovl_use,
913 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
914 if (dev->devtype->product == CODA_960) {
915 coda_write(dev, ctx->iram_info.buf_btp_use,
916 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
917
918 /* FIXME */
919 coda_write(dev, ctx->internal_frames[2].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_A);
920 coda_write(dev, ctx->internal_frames[3].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_B);
921 }
922 }
923
924 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
925 if (ret < 0) {
926 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
927 goto out;
928 }
929
930 /* Save stream headers */
931 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
932 switch (dst_fourcc) {
933 case V4L2_PIX_FMT_H264:
934 /*
935 * Get SPS in the first frame and copy it to an
936 * intermediate buffer.
937 */
938 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
939 &ctx->vpu_header[0][0],
940 &ctx->vpu_header_size[0]);
941 if (ret < 0)
942 goto out;
943
944 /*
945 * Get PPS in the first frame and copy it to an
946 * intermediate buffer.
947 */
948 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
949 &ctx->vpu_header[1][0],
950 &ctx->vpu_header_size[1]);
951 if (ret < 0)
952 goto out;
953
954 /*
955 * Length of H.264 headers is variable and thus it might not be
956 * aligned for the coda to append the encoded frame. In that is
957 * the case a filler NAL must be added to header 2.
958 */
959 ctx->vpu_header_size[2] = coda_h264_padding(
960 (ctx->vpu_header_size[0] +
961 ctx->vpu_header_size[1]),
962 ctx->vpu_header[2]);
963 break;
964 case V4L2_PIX_FMT_MPEG4:
965 /*
966 * Get VOS in the first frame and copy it to an
967 * intermediate buffer
968 */
969 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
970 &ctx->vpu_header[0][0],
971 &ctx->vpu_header_size[0]);
972 if (ret < 0)
973 goto out;
974
975 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
976 &ctx->vpu_header[1][0],
977 &ctx->vpu_header_size[1]);
978 if (ret < 0)
979 goto out;
980
981 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
982 &ctx->vpu_header[2][0],
983 &ctx->vpu_header_size[2]);
984 if (ret < 0)
985 goto out;
986 break;
987 default:
988 /* No more formats need to save headers at the moment */
989 break;
990 }
991
992out:
993 mutex_unlock(&dev->coda_mutex);
994 return ret;
995}
996
997static int coda_prepare_encode(struct coda_ctx *ctx)
998{
999 struct coda_q_data *q_data_src, *q_data_dst;
1000 struct vb2_buffer *src_buf, *dst_buf;
1001 struct coda_dev *dev = ctx->dev;
1002 int force_ipicture;
1003 int quant_param = 0;
1004 u32 picture_y, picture_cb, picture_cr;
1005 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1006 u32 dst_fourcc;
1007
1008 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1009 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1010 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1011 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1012 dst_fourcc = q_data_dst->fourcc;
1013
1014 src_buf->v4l2_buf.sequence = ctx->osequence;
1015 dst_buf->v4l2_buf.sequence = ctx->osequence;
1016 ctx->osequence++;
1017
1018 /*
1019 * Workaround coda firmware BUG that only marks the first
1020 * frame as IDR. This is a problem for some decoders that can't
1021 * recover when a frame is lost.
1022 */
1023 if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
1024 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1025 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1026 } else {
1027 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1028 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1029 }
1030
1031 if (dev->devtype->product == CODA_960)
1032 coda_set_gdi_regs(ctx);
1033
1034 /*
1035 * Copy headers at the beginning of the first frame for H.264 only.
1036 * In MPEG4 they are already copied by the coda.
1037 */
1038 if (src_buf->v4l2_buf.sequence == 0) {
1039 pic_stream_buffer_addr =
1040 vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
1041 ctx->vpu_header_size[0] +
1042 ctx->vpu_header_size[1] +
1043 ctx->vpu_header_size[2];
1044 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
1045 ctx->vpu_header_size[0] -
1046 ctx->vpu_header_size[1] -
1047 ctx->vpu_header_size[2];
1048 memcpy(vb2_plane_vaddr(dst_buf, 0),
1049 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1050 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
1051 &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
1052 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
1053 ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
1054 ctx->vpu_header_size[2]);
1055 } else {
1056 pic_stream_buffer_addr =
1057 vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1058 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
1059 }
1060
1061 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1062 force_ipicture = 1;
1063 switch (dst_fourcc) {
1064 case V4L2_PIX_FMT_H264:
1065 quant_param = ctx->params.h264_intra_qp;
1066 break;
1067 case V4L2_PIX_FMT_MPEG4:
1068 quant_param = ctx->params.mpeg4_intra_qp;
1069 break;
1070 default:
1071 v4l2_warn(&ctx->dev->v4l2_dev,
1072 "cannot set intra qp, fmt not supported\n");
1073 break;
1074 }
1075 } else {
1076 force_ipicture = 0;
1077 switch (dst_fourcc) {
1078 case V4L2_PIX_FMT_H264:
1079 quant_param = ctx->params.h264_inter_qp;
1080 break;
1081 case V4L2_PIX_FMT_MPEG4:
1082 quant_param = ctx->params.mpeg4_inter_qp;
1083 break;
1084 default:
1085 v4l2_warn(&ctx->dev->v4l2_dev,
1086 "cannot set inter qp, fmt not supported\n");
1087 break;
1088 }
1089 }
1090
1091 /* submit */
1092 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1093 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1094
1095
1096 picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
1097 switch (q_data_src->fourcc) {
1098 case V4L2_PIX_FMT_YVU420:
1099 /* Switch Cb and Cr for YVU420 format */
1100 picture_cr = picture_y + q_data_src->bytesperline *
1101 q_data_src->height;
1102 picture_cb = picture_cr + q_data_src->bytesperline / 2 *
1103 q_data_src->height / 2;
1104 break;
1105 case V4L2_PIX_FMT_YUV420:
1106 default:
1107 picture_cb = picture_y + q_data_src->bytesperline *
1108 q_data_src->height;
1109 picture_cr = picture_cb + q_data_src->bytesperline / 2 *
1110 q_data_src->height / 2;
1111 break;
1112 }
1113
1114 if (dev->devtype->product == CODA_960) {
1115 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1116 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1117 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1118
1119 coda_write(dev, picture_y, CODA9_CMD_ENC_PIC_SRC_ADDR_Y);
1120 coda_write(dev, picture_cb, CODA9_CMD_ENC_PIC_SRC_ADDR_CB);
1121 coda_write(dev, picture_cr, CODA9_CMD_ENC_PIC_SRC_ADDR_CR);
1122 } else {
1123 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
1124 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
1125 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
1126 }
1127 coda_write(dev, force_ipicture << 1 & 0x2,
1128 CODA_CMD_ENC_PIC_OPTION);
1129
1130 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1131 coda_write(dev, pic_stream_buffer_size / 1024,
1132 CODA_CMD_ENC_PIC_BB_SIZE);
1133
1134 if (!ctx->streamon_out) {
1135 /* After streamoff on the output side, set the stream end flag */
1136 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1137 coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM);
1138 }
1139
1140 if (dev->devtype->product != CODA_DX6)
1141 coda_write(dev, ctx->iram_info.axi_sram_use,
1142 CODA7_REG_BIT_AXI_SRAM_USE);
1143
1144 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1145
1146 return 0;
1147}
1148
1149static void coda_finish_encode(struct coda_ctx *ctx)
1150{
1151 struct vb2_buffer *src_buf, *dst_buf;
1152 struct coda_dev *dev = ctx->dev;
1153 u32 wr_ptr, start_ptr;
1154
1155 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1156 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1157
1158 /* Get results from the coda */
1159 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1160 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1161
1162 /* Calculate bytesused field */
1163 if (dst_buf->v4l2_buf.sequence == 0) {
1164 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
1165 ctx->vpu_header_size[0] +
1166 ctx->vpu_header_size[1] +
1167 ctx->vpu_header_size[2]);
1168 } else {
1169 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
1170 }
1171
1172 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1173 wr_ptr - start_ptr);
1174
1175 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1176 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1177
1178 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1179 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1180 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1181 } else {
1182 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1183 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1184 }
1185
1186 dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
1187 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1188 dst_buf->v4l2_buf.flags |=
1189 src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1190 dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
1191
1192 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1193
1194 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1195 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1196
1197 ctx->gopcounter--;
1198 if (ctx->gopcounter < 0)
1199 ctx->gopcounter = ctx->params.gop_size - 1;
1200
1201 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1202 "job finished: encoding frame (%d) (%s)\n",
1203 dst_buf->v4l2_buf.sequence,
1204 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1205 "KEYFRAME" : "PFRAME");
1206}
1207
1208static void coda_seq_end_work(struct work_struct *work)
1209{
1210 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1211 struct coda_dev *dev = ctx->dev;
1212
1213 mutex_lock(&ctx->buffer_mutex);
1214 mutex_lock(&dev->coda_mutex);
1215
1216 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1217 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx, __func__);
1218 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1219 v4l2_err(&dev->v4l2_dev,
1220 "CODA_COMMAND_SEQ_END failed\n");
1221 }
1222
1223 kfifo_init(&ctx->bitstream_fifo,
1224 ctx->bitstream.vaddr, ctx->bitstream.size);
1225
1226 coda_free_framebuffers(ctx);
1227 coda_free_context_buffers(ctx);
1228
1229 mutex_unlock(&dev->coda_mutex);
1230 mutex_unlock(&ctx->buffer_mutex);
1231}
1232
1233static void coda_bit_release(struct coda_ctx *ctx)
1234{
1235 coda_free_framebuffers(ctx);
1236 coda_free_context_buffers(ctx);
1237}
1238
1239const struct coda_context_ops coda_bit_encode_ops = {
1240 .queue_init = coda_encoder_queue_init,
1241 .start_streaming = coda_start_encoding,
1242 .prepare_run = coda_prepare_encode,
1243 .finish_run = coda_finish_encode,
1244 .seq_end_work = coda_seq_end_work,
1245 .release = coda_bit_release,
1246};
1247
1248/*
1249 * Decoder context operations
1250 */
1251
1252static int __coda_start_decoding(struct coda_ctx *ctx)
1253{
1254 struct coda_q_data *q_data_src, *q_data_dst;
1255 u32 bitstream_buf, bitstream_size;
1256 struct coda_dev *dev = ctx->dev;
1257 int width, height;
1258 u32 src_fourcc;
1259 u32 val;
1260 int ret;
1261
1262 /* Start decoding */
1263 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1264 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1265 bitstream_buf = ctx->bitstream.paddr;
1266 bitstream_size = ctx->bitstream.size;
1267 src_fourcc = q_data_src->fourcc;
1268
1269 /* Allocate per-instance buffers */
1270 ret = coda_alloc_context_buffers(ctx, q_data_src);
1271 if (ret < 0)
1272 return ret;
1273
1274 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1275
1276 /* Update coda bitstream read and write pointers from kfifo */
1277 coda_kfifo_sync_to_device_full(ctx);
1278
1279 ctx->display_idx = -1;
1280 ctx->frm_dis_flg = 0;
1281 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1282
1283 coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1284 CODA_REG_BIT_BIT_STREAM_PARAM);
1285
1286 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1287 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1288 val = 0;
1289 if ((dev->devtype->product == CODA_7541) ||
1290 (dev->devtype->product == CODA_960))
1291 val |= CODA_REORDER_ENABLE;
1292 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1293
1294 ctx->params.codec_mode = ctx->codec->mode;
1295 if (dev->devtype->product == CODA_960 &&
1296 src_fourcc == V4L2_PIX_FMT_MPEG4)
1297 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1298 else
1299 ctx->params.codec_mode_aux = 0;
1300 if (src_fourcc == V4L2_PIX_FMT_H264) {
1301 if (dev->devtype->product == CODA_7541) {
1302 coda_write(dev, ctx->psbuf.paddr,
1303 CODA_CMD_DEC_SEQ_PS_BB_START);
1304 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1305 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1306 }
1307 if (dev->devtype->product == CODA_960) {
1308 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1309 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1310 }
1311 }
1312 if (dev->devtype->product != CODA_960)
1313 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1314
1315 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1316 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1317 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1318 return -ETIMEDOUT;
1319 }
1320
1321 /* Update kfifo out pointer from coda bitstream read pointer */
1322 coda_kfifo_sync_from_device(ctx);
1323
1324 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1325
1326 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1327 v4l2_err(&dev->v4l2_dev,
1328 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1329 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1330 return -EAGAIN;
1331 }
1332
1333 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1334 if (dev->devtype->product == CODA_DX6) {
1335 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1336 height = val & CODADX6_PICHEIGHT_MASK;
1337 } else {
1338 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1339 height = val & CODA7_PICHEIGHT_MASK;
1340 }
1341
1342 if (width > q_data_dst->width || height > q_data_dst->height) {
1343 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1344 width, height, q_data_dst->width, q_data_dst->height);
1345 return -EINVAL;
1346 }
1347
1348 width = round_up(width, 16);
1349 height = round_up(height, 16);
1350
1351 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1352 __func__, ctx->idx, width, height);
1353
1354 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1355 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1356 v4l2_err(&dev->v4l2_dev,
1357 "not enough framebuffers to decode (%d < %d)\n",
1358 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1359 return -EINVAL;
1360 }
1361
1362 if (src_fourcc == V4L2_PIX_FMT_H264) {
1363 u32 left_right;
1364 u32 top_bottom;
1365
1366 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1367 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1368
1369 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1370 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1371 q_data_dst->rect.width = width - q_data_dst->rect.left -
1372 (left_right & 0x3ff);
1373 q_data_dst->rect.height = height - q_data_dst->rect.top -
1374 (top_bottom & 0x3ff);
1375 }
1376
1377 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1378 if (ret < 0)
1379 return ret;
1380
1381 /* Tell the decoder how many frame buffers we allocated. */
1382 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1383 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1384
1385 if (dev->devtype->product != CODA_DX6) {
1386 /* Set secondary AXI IRAM */
1387 coda_setup_iram(ctx);
1388
1389 coda_write(dev, ctx->iram_info.buf_bit_use,
1390 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1391 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1392 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1393 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1394 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1395 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1396 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1397 coda_write(dev, ctx->iram_info.buf_ovl_use,
1398 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1399 if (dev->devtype->product == CODA_960)
1400 coda_write(dev, ctx->iram_info.buf_btp_use,
1401 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1402 }
1403
1404 if (dev->devtype->product == CODA_960) {
1405 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1406
1407 coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
1408 coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
1409 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
1410 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
1411 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
1412 CODA9_CMD_SET_FRAME_CACHE_CONFIG);
1413 }
1414
1415 if (src_fourcc == V4L2_PIX_FMT_H264) {
1416 coda_write(dev, ctx->slicebuf.paddr,
1417 CODA_CMD_SET_FRAME_SLICE_BB_START);
1418 coda_write(dev, ctx->slicebuf.size / 1024,
1419 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1420 }
1421
1422 if (dev->devtype->product == CODA_7541) {
1423 int max_mb_x = 1920 / 16;
1424 int max_mb_y = 1088 / 16;
1425 int max_mb_num = max_mb_x * max_mb_y;
1426
1427 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1428 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1429 } else if (dev->devtype->product == CODA_960) {
1430 int max_mb_x = 1920 / 16;
1431 int max_mb_y = 1088 / 16;
1432 int max_mb_num = max_mb_x * max_mb_y;
1433
1434 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1435 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1436 }
1437
1438 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1439 v4l2_err(&ctx->dev->v4l2_dev,
1440 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1441 return -ETIMEDOUT;
1442 }
1443
1444 return 0;
1445}
1446
1447static int coda_start_decoding(struct coda_ctx *ctx)
1448{
1449 struct coda_dev *dev = ctx->dev;
1450 int ret;
1451
1452 mutex_lock(&dev->coda_mutex);
1453 ret = __coda_start_decoding(ctx);
1454 mutex_unlock(&dev->coda_mutex);
1455
1456 return ret;
1457}
1458
1459static int coda_prepare_decode(struct coda_ctx *ctx)
1460{
1461 struct vb2_buffer *dst_buf;
1462 struct coda_dev *dev = ctx->dev;
1463 struct coda_q_data *q_data_dst;
1464 u32 stridey, height;
1465 u32 picture_y, picture_cb, picture_cr;
1466
1467 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1468 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1469
1470 if (ctx->params.rot_mode & CODA_ROT_90) {
1471 stridey = q_data_dst->height;
1472 height = q_data_dst->width;
1473 } else {
1474 stridey = q_data_dst->width;
1475 height = q_data_dst->height;
1476 }
1477
1478 /* Try to copy source buffer contents into the bitstream ringbuffer */
1479 mutex_lock(&ctx->bitstream_mutex);
1480 coda_fill_bitstream(ctx);
1481 mutex_unlock(&ctx->bitstream_mutex);
1482
1483 if (coda_get_bitstream_payload(ctx) < 512 &&
1484 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1485 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1486 "bitstream payload: %d, skipping\n",
1487 coda_get_bitstream_payload(ctx));
1488 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1489 return -EAGAIN;
1490 }
1491
1492 /* Run coda_start_decoding (again) if not yet initialized */
1493 if (!ctx->initialized) {
1494 int ret = __coda_start_decoding(ctx);
1495
1496 if (ret < 0) {
1497 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1498 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1499 return -EAGAIN;
1500 } else {
1501 ctx->initialized = 1;
1502 }
1503 }
1504
1505 if (dev->devtype->product == CODA_960)
1506 coda_set_gdi_regs(ctx);
1507
1508 /* Set rotator output */
1509 picture_y = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1510 if (q_data_dst->fourcc == V4L2_PIX_FMT_YVU420) {
1511 /* Switch Cr and Cb for YVU420 format */
1512 picture_cr = picture_y + stridey * height;
1513 picture_cb = picture_cr + stridey / 2 * height / 2;
1514 } else {
1515 picture_cb = picture_y + stridey * height;
1516 picture_cr = picture_cb + stridey / 2 * height / 2;
1517 }
1518
1519 if (dev->devtype->product == CODA_960) {
1520 /*
1521 * The CODA960 seems to have an internal list of buffers with
1522 * 64 entries that includes the registered frame buffers as
1523 * well as the rotator buffer output.
1524 * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1525 */
1526 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
1527 CODA9_CMD_DEC_PIC_ROT_INDEX);
1528 coda_write(dev, picture_y, CODA9_CMD_DEC_PIC_ROT_ADDR_Y);
1529 coda_write(dev, picture_cb, CODA9_CMD_DEC_PIC_ROT_ADDR_CB);
1530 coda_write(dev, picture_cr, CODA9_CMD_DEC_PIC_ROT_ADDR_CR);
1531 coda_write(dev, stridey, CODA9_CMD_DEC_PIC_ROT_STRIDE);
1532 } else {
1533 coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y);
1534 coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB);
1535 coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR);
1536 coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE);
1537 }
1538 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1539 CODA_CMD_DEC_PIC_ROT_MODE);
1540
1541 switch (dev->devtype->product) {
1542 case CODA_DX6:
1543 /* TBD */
1544 case CODA_7541:
1545 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1546 break;
1547 case CODA_960:
1548 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION); /* 'hardcode to use interrupt disable mode'? */
1549 break;
1550 }
1551
1552 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1553
1554 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1555 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1556
1557 if (dev->devtype->product != CODA_DX6)
1558 coda_write(dev, ctx->iram_info.axi_sram_use,
1559 CODA7_REG_BIT_AXI_SRAM_USE);
1560
1561 coda_kfifo_sync_to_device_full(ctx);
1562
1563 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1564
1565 return 0;
1566}
1567
1568static void coda_finish_decode(struct coda_ctx *ctx)
1569{
1570 struct coda_dev *dev = ctx->dev;
1571 struct coda_q_data *q_data_src;
1572 struct coda_q_data *q_data_dst;
1573 struct vb2_buffer *dst_buf;
1574 struct coda_timestamp *ts;
1575 int width, height;
1576 int decoded_idx;
1577 int display_idx;
1578 u32 src_fourcc;
1579 int success;
1580 u32 err_mb;
1581 u32 val;
1582
Philipp Zabel79924ca2014-07-23 12:28:45 -03001583 /* Update kfifo out pointer from coda bitstream read pointer */
1584 coda_kfifo_sync_from_device(ctx);
1585
1586 /*
1587 * in stream-end mode, the read pointer can overshoot the write pointer
1588 * by up to 512 bytes
1589 */
1590 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1591 if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
1592 kfifo_init(&ctx->bitstream_fifo,
1593 ctx->bitstream.vaddr, ctx->bitstream.size);
1594 }
1595
1596 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1597 src_fourcc = q_data_src->fourcc;
1598
1599 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1600 if (val != 1)
1601 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1602
1603 success = val & 0x1;
1604 if (!success)
1605 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1606
1607 if (src_fourcc == V4L2_PIX_FMT_H264) {
1608 if (val & (1 << 3))
1609 v4l2_err(&dev->v4l2_dev,
1610 "insufficient PS buffer space (%d bytes)\n",
1611 ctx->psbuf.size);
1612 if (val & (1 << 2))
1613 v4l2_err(&dev->v4l2_dev,
1614 "insufficient slice buffer space (%d bytes)\n",
1615 ctx->slicebuf.size);
1616 }
1617
1618 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1619 width = (val >> 16) & 0xffff;
1620 height = val & 0xffff;
1621
1622 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1623
1624 /* frame crop information */
1625 if (src_fourcc == V4L2_PIX_FMT_H264) {
1626 u32 left_right;
1627 u32 top_bottom;
1628
1629 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1630 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1631
1632 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1633 /* Keep current crop information */
1634 } else {
1635 struct v4l2_rect *rect = &q_data_dst->rect;
1636
1637 rect->left = left_right >> 16 & 0xffff;
1638 rect->top = top_bottom >> 16 & 0xffff;
1639 rect->width = width - rect->left -
1640 (left_right & 0xffff);
1641 rect->height = height - rect->top -
1642 (top_bottom & 0xffff);
1643 }
1644 } else {
1645 /* no cropping */
1646 }
1647
1648 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1649 if (err_mb > 0)
1650 v4l2_err(&dev->v4l2_dev,
1651 "errors in %d macroblocks\n", err_mb);
1652
1653 if (dev->devtype->product == CODA_7541) {
1654 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1655 if (val == 0) {
1656 /* not enough bitstream data */
1657 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1658 "prescan failed: %d\n", val);
1659 ctx->hold = true;
1660 return;
1661 }
1662 }
1663
1664 ctx->frm_dis_flg = coda_read(dev, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1665
1666 /*
1667 * The previous display frame was copied out by the rotator,
1668 * now it can be overwritten again
1669 */
1670 if (ctx->display_idx >= 0 &&
1671 ctx->display_idx < ctx->num_internal_frames) {
1672 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1673 coda_write(dev, ctx->frm_dis_flg,
1674 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1675 }
1676
1677 /*
1678 * The index of the last decoded frame, not necessarily in
1679 * display order, and the index of the next display frame.
1680 * The latter could have been decoded in a previous run.
1681 */
1682 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1683 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1684
1685 if (decoded_idx == -1) {
1686 /* no frame was decoded, but we might have a display frame */
1687 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1688 ctx->sequence_offset++;
1689 else if (ctx->display_idx < 0)
1690 ctx->hold = true;
1691 } else if (decoded_idx == -2) {
1692 /* no frame was decoded, we still return the remaining buffers */
1693 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
1694 v4l2_err(&dev->v4l2_dev,
1695 "decoded frame index out of range: %d\n", decoded_idx);
1696 } else {
1697 ts = list_first_entry(&ctx->timestamp_list,
1698 struct coda_timestamp, list);
1699 list_del(&ts->list);
1700 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
1701 val -= ctx->sequence_offset;
1702 if (val != (ts->sequence & 0xffff)) {
1703 v4l2_err(&dev->v4l2_dev,
1704 "sequence number mismatch (%d(%d) != %d)\n",
1705 val, ctx->sequence_offset, ts->sequence);
1706 }
1707 ctx->frame_timestamps[decoded_idx] = *ts;
1708 kfree(ts);
1709
1710 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
1711 if (val == 0)
1712 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
1713 else if (val == 1)
1714 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
1715 else
1716 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
1717
1718 ctx->frame_errors[decoded_idx] = err_mb;
1719 }
1720
1721 if (display_idx == -1) {
1722 /*
1723 * no more frames to be decoded, but there could still
1724 * be rotator output to dequeue
1725 */
1726 ctx->hold = true;
1727 } else if (display_idx == -3) {
1728 /* possibly prescan failure */
1729 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
1730 v4l2_err(&dev->v4l2_dev,
1731 "presentation frame index out of range: %d\n",
1732 display_idx);
1733 }
1734
1735 /* If a frame was copied out, return it */
1736 if (ctx->display_idx >= 0 &&
1737 ctx->display_idx < ctx->num_internal_frames) {
1738 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1739 dst_buf->v4l2_buf.sequence = ctx->osequence++;
1740
1741 dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
1742 V4L2_BUF_FLAG_PFRAME |
1743 V4L2_BUF_FLAG_BFRAME);
1744 dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
1745 ts = &ctx->frame_timestamps[ctx->display_idx];
1746 dst_buf->v4l2_buf.timecode = ts->timecode;
1747 dst_buf->v4l2_buf.timestamp = ts->timestamp;
1748
1749 vb2_set_plane_payload(dst_buf, 0, width * height * 3 / 2);
1750
1751 v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
1752 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
1753
1754 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1755 "job finished: decoding frame (%d) (%s)\n",
1756 dst_buf->v4l2_buf.sequence,
1757 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1758 "KEYFRAME" : "PFRAME");
1759 } else {
1760 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1761 "job finished: no frame decoded\n");
1762 }
1763
1764 /* The rotator will copy the current display frame next time */
1765 ctx->display_idx = display_idx;
1766}
1767
1768const struct coda_context_ops coda_bit_decode_ops = {
1769 .queue_init = coda_decoder_queue_init,
1770 .start_streaming = coda_start_decoding,
1771 .prepare_run = coda_prepare_decode,
1772 .finish_run = coda_finish_decode,
1773 .seq_end_work = coda_seq_end_work,
1774 .release = coda_bit_release,
1775};
1776
1777irqreturn_t coda_irq_handler(int irq, void *data)
1778{
1779 struct coda_dev *dev = data;
1780 struct coda_ctx *ctx;
1781
1782 /* read status register to attend the IRQ */
1783 coda_read(dev, CODA_REG_BIT_INT_STATUS);
1784 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1785 CODA_REG_BIT_INT_CLEAR);
1786
1787 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1788 if (ctx == NULL) {
1789 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
1790 mutex_unlock(&dev->coda_mutex);
1791 return IRQ_HANDLED;
1792 }
1793
1794 if (ctx->aborting) {
1795 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1796 "task has been aborted\n");
1797 }
1798
1799 if (coda_isbusy(ctx->dev)) {
1800 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1801 "coda is still busy!!!!\n");
1802 return IRQ_NONE;
1803 }
1804
1805 complete(&ctx->completion);
1806
1807 return IRQ_HANDLED;
1808}