blob: fe18a5d2d84bbb2fd13eaff90fab683ce7f31e43 [file] [log] [blame]
Lars-Peter Clausen9c8af882012-03-05 16:30:57 +01001/*
2 * Analog Devices ADV7511 HDMI transmitter driver
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9#ifndef __DRM_I2C_ADV7511_H__
10#define __DRM_I2C_ADV7511_H__
11
12#include <linux/hdmi.h>
Archit Taneja2437e7c2016-06-15 16:24:03 +053013#include <linux/i2c.h>
14#include <linux/regmap.h>
Archit Taneja5b06ba22017-01-11 12:22:27 +053015#include <linux/regulator/consumer.h>
Archit Taneja2437e7c2016-06-15 16:24:03 +053016
17#include <drm/drm_crtc_helper.h>
Archit Taneja1e4d58c2016-06-15 17:01:27 +053018#include <drm/drm_mipi_dsi.h>
Lars-Peter Clausen9c8af882012-03-05 16:30:57 +010019
20#define ADV7511_REG_CHIP_REVISION 0x00
21#define ADV7511_REG_N0 0x01
22#define ADV7511_REG_N1 0x02
23#define ADV7511_REG_N2 0x03
24#define ADV7511_REG_SPDIF_FREQ 0x04
25#define ADV7511_REG_CTS_AUTOMATIC1 0x05
26#define ADV7511_REG_CTS_AUTOMATIC2 0x06
27#define ADV7511_REG_CTS_MANUAL0 0x07
28#define ADV7511_REG_CTS_MANUAL1 0x08
29#define ADV7511_REG_CTS_MANUAL2 0x09
30#define ADV7511_REG_AUDIO_SOURCE 0x0a
31#define ADV7511_REG_AUDIO_CONFIG 0x0b
32#define ADV7511_REG_I2S_CONFIG 0x0c
33#define ADV7511_REG_I2S_WIDTH 0x0d
34#define ADV7511_REG_AUDIO_SUB_SRC0 0x0e
35#define ADV7511_REG_AUDIO_SUB_SRC1 0x0f
36#define ADV7511_REG_AUDIO_SUB_SRC2 0x10
37#define ADV7511_REG_AUDIO_SUB_SRC3 0x11
38#define ADV7511_REG_AUDIO_CFG1 0x12
39#define ADV7511_REG_AUDIO_CFG2 0x13
40#define ADV7511_REG_AUDIO_CFG3 0x14
41#define ADV7511_REG_I2C_FREQ_ID_CFG 0x15
42#define ADV7511_REG_VIDEO_INPUT_CFG1 0x16
43#define ADV7511_REG_CSC_UPPER(x) (0x18 + (x) * 2)
44#define ADV7511_REG_CSC_LOWER(x) (0x19 + (x) * 2)
45#define ADV7511_REG_SYNC_DECODER(x) (0x30 + (x))
46#define ADV7511_REG_DE_GENERATOR (0x35 + (x))
47#define ADV7511_REG_PIXEL_REPETITION 0x3b
48#define ADV7511_REG_VIC_MANUAL 0x3c
49#define ADV7511_REG_VIC_SEND 0x3d
50#define ADV7511_REG_VIC_DETECTED 0x3e
51#define ADV7511_REG_AUX_VIC_DETECTED 0x3f
52#define ADV7511_REG_PACKET_ENABLE0 0x40
53#define ADV7511_REG_POWER 0x41
54#define ADV7511_REG_STATUS 0x42
55#define ADV7511_REG_EDID_I2C_ADDR 0x43
56#define ADV7511_REG_PACKET_ENABLE1 0x44
57#define ADV7511_REG_PACKET_I2C_ADDR 0x45
58#define ADV7511_REG_DSD_ENABLE 0x46
59#define ADV7511_REG_VIDEO_INPUT_CFG2 0x48
60#define ADV7511_REG_INFOFRAME_UPDATE 0x4a
61#define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
62#define ADV7511_REG_AVI_INFOFRAME_VERSION 0x52
63#define ADV7511_REG_AVI_INFOFRAME_LENGTH 0x53
64#define ADV7511_REG_AVI_INFOFRAME_CHECKSUM 0x54
65#define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
66#define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x70
67#define ADV7511_REG_AUDIO_INFOFRAME_LENGTH 0x71
68#define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM 0x72
69#define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
70#define ADV7511_REG_INT_ENABLE(x) (0x94 + (x))
71#define ADV7511_REG_INT(x) (0x96 + (x))
72#define ADV7511_REG_INPUT_CLK_DIV 0x9d
73#define ADV7511_REG_PLL_STATUS 0x9e
74#define ADV7511_REG_HDMI_POWER 0xa1
75#define ADV7511_REG_HDCP_HDMI_CFG 0xaf
76#define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
77#define ADV7511_REG_HDCP_STATUS 0xb8
78#define ADV7511_REG_BCAPS 0xbe
79#define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
80#define ADV7511_REG_EDID_SEGMENT 0xc4
81#define ADV7511_REG_DDC_STATUS 0xc8
82#define ADV7511_REG_EDID_READ_CTRL 0xc9
83#define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
84#define ADV7511_REG_TIMING_GEN_SEQ 0xd0
85#define ADV7511_REG_POWER2 0xd6
86#define ADV7511_REG_HSYNC_PLACEMENT_MSB 0xfa
87
88#define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
89#define ADV7511_REG_TMDS_CLOCK_INV 0xde
90#define ADV7511_REG_ARC_CTRL 0xdf
91#define ADV7511_REG_CEC_I2C_ADDR 0xe1
92#define ADV7511_REG_CEC_CTRL 0xe2
93#define ADV7511_REG_CHIP_ID_HIGH 0xf5
94#define ADV7511_REG_CHIP_ID_LOW 0xf6
95
96#define ADV7511_CSC_ENABLE BIT(7)
97#define ADV7511_CSC_UPDATE_MODE BIT(5)
98
Wolfram Sang29ce4ed2016-01-04 03:33:47 +010099#define ADV7511_INT0_HPD BIT(7)
Lars-Peter Clausen9c8af882012-03-05 16:30:57 +0100100#define ADV7511_INT0_VSYNC BIT(5)
101#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
102#define ADV7511_INT0_EDID_READY BIT(2)
103#define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)
104
105#define ADV7511_INT1_DDC_ERROR BIT(7)
106#define ADV7511_INT1_BKSV BIT(6)
107#define ADV7511_INT1_CEC_TX_READY BIT(5)
108#define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4)
109#define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)
110#define ADV7511_INT1_CEC_RX_READY3 BIT(2)
111#define ADV7511_INT1_CEC_RX_READY2 BIT(1)
112#define ADV7511_INT1_CEC_RX_READY1 BIT(0)
113
114#define ADV7511_ARC_CTRL_POWER_DOWN BIT(0)
115
116#define ADV7511_CEC_CTRL_POWER_DOWN BIT(0)
117
118#define ADV7511_POWER_POWER_DOWN BIT(6)
119
120#define ADV7511_HDMI_CFG_MODE_MASK 0x2
121#define ADV7511_HDMI_CFG_MODE_DVI 0x0
122#define ADV7511_HDMI_CFG_MODE_HDMI 0x2
123
124#define ADV7511_AUDIO_SELECT_I2C 0x0
125#define ADV7511_AUDIO_SELECT_SPDIF 0x1
126#define ADV7511_AUDIO_SELECT_DSD 0x2
127#define ADV7511_AUDIO_SELECT_HBR 0x3
128#define ADV7511_AUDIO_SELECT_DST 0x4
129
130#define ADV7511_I2S_SAMPLE_LEN_16 0x2
131#define ADV7511_I2S_SAMPLE_LEN_20 0x3
132#define ADV7511_I2S_SAMPLE_LEN_18 0x4
133#define ADV7511_I2S_SAMPLE_LEN_22 0x5
134#define ADV7511_I2S_SAMPLE_LEN_19 0x8
135#define ADV7511_I2S_SAMPLE_LEN_23 0x9
136#define ADV7511_I2S_SAMPLE_LEN_24 0xb
137#define ADV7511_I2S_SAMPLE_LEN_17 0xc
138#define ADV7511_I2S_SAMPLE_LEN_21 0xd
139
140#define ADV7511_SAMPLE_FREQ_44100 0x0
141#define ADV7511_SAMPLE_FREQ_48000 0x2
142#define ADV7511_SAMPLE_FREQ_32000 0x3
143#define ADV7511_SAMPLE_FREQ_88200 0x8
144#define ADV7511_SAMPLE_FREQ_96000 0xa
145#define ADV7511_SAMPLE_FREQ_176400 0xc
146#define ADV7511_SAMPLE_FREQ_192000 0xe
147
148#define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7)
149#define ADV7511_STATUS_HPD BIT(6)
150#define ADV7511_STATUS_MONITOR_SENSE BIT(5)
151#define ADV7511_STATUS_I2S_32BIT_MODE BIT(3)
152
153#define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6)
154#define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)
155#define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
156#define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)
157#define ADV7511_PACKET_ENABLE_GC BIT(7)
158#define ADV7511_PACKET_ENABLE_SPD BIT(6)
159#define ADV7511_PACKET_ENABLE_MPEG BIT(5)
160#define ADV7511_PACKET_ENABLE_ACP BIT(4)
161#define ADV7511_PACKET_ENABLE_ISRC BIT(3)
162#define ADV7511_PACKET_ENABLE_GM BIT(2)
163#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
164#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
165
Wolfram Sang29ce4ed2016-01-04 03:33:47 +0100166#define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0
167#define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00
168#define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40
169#define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80
170#define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0
Lars-Peter Clausen9c8af882012-03-05 16:30:57 +0100171#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
172#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
173
174#define ADV7511_LOW_REFRESH_RATE_NONE 0x0
175#define ADV7511_LOW_REFRESH_RATE_24HZ 0x1
176#define ADV7511_LOW_REFRESH_RATE_25HZ 0x2
177#define ADV7511_LOW_REFRESH_RATE_30HZ 0x3
178
179#define ADV7511_AUDIO_CFG3_LEN_MASK 0x0f
180#define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK 0xf0
181
182#define ADV7511_AUDIO_SOURCE_I2S 0
183#define ADV7511_AUDIO_SOURCE_SPDIF 1
184
185#define ADV7511_I2S_FORMAT_I2S 0
186#define ADV7511_I2S_FORMAT_RIGHT_J 1
187#define ADV7511_I2S_FORMAT_LEFT_J 2
188
189#define ADV7511_PACKET(p, x) ((p) * 0x20 + (x))
190#define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x)
191#define ADV7511_PACKET_MPEG(x) ADV7511_PACKET(1, x)
192#define ADV7511_PACKET_ACP(x) ADV7511_PACKET(2, x)
193#define ADV7511_PACKET_ISRC1(x) ADV7511_PACKET(3, x)
194#define ADV7511_PACKET_ISRC2(x) ADV7511_PACKET(4, x)
195#define ADV7511_PACKET_GM(x) ADV7511_PACKET(5, x)
196#define ADV7511_PACKET_SPARE(x) ADV7511_PACKET(6, x)
197
198enum adv7511_input_clock {
199 ADV7511_INPUT_CLOCK_1X,
200 ADV7511_INPUT_CLOCK_2X,
201 ADV7511_INPUT_CLOCK_DDR,
202};
203
204enum adv7511_input_justification {
205 ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,
206 ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,
207 ADV7511_INPUT_JUSTIFICATION_LEFT = 2,
208};
209
210enum adv7511_input_sync_pulse {
211 ADV7511_INPUT_SYNC_PULSE_DE = 0,
212 ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,
213 ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,
214 ADV7511_INPUT_SYNC_PULSE_NONE = 3,
215};
216
217/**
218 * enum adv7511_sync_polarity - Polarity for the input sync signals
219 * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
220 * the currently configured mode.
221 * @ADV7511_SYNC_POLARITY_LOW: Sync polarity is low
222 * @ADV7511_SYNC_POLARITY_HIGH: Sync polarity is high
223 *
224 * If the polarity is set to either LOW or HIGH the driver will configure the
225 * ADV7511 to internally invert the sync signal if required to match the sync
226 * polarity setting for the currently selected output mode.
227 *
228 * If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal
229 * unchanged. This is used when the upstream graphics core already generates
230 * the sync signals with the correct polarity.
231 */
232enum adv7511_sync_polarity {
233 ADV7511_SYNC_POLARITY_PASSTHROUGH,
234 ADV7511_SYNC_POLARITY_LOW,
235 ADV7511_SYNC_POLARITY_HIGH,
236};
237
238/**
239 * struct adv7511_link_config - Describes adv7511 hardware configuration
240 * @input_color_depth: Number of bits per color component (8, 10 or 12)
241 * @input_colorspace: The input colorspace (RGB, YUV444, YUV422)
242 * @input_clock: The input video clock style (1x, 2x, DDR)
243 * @input_style: The input component arrangement variant
244 * @input_justification: Video input format bit justification
245 * @clock_delay: Clock delay for the input clock (in ps)
246 * @embedded_sync: Video input uses BT.656-style embedded sync
247 * @sync_pulse: Select the sync pulse
248 * @vsync_polarity: vsync input signal configuration
249 * @hsync_polarity: hsync input signal configuration
250 */
251struct adv7511_link_config {
252 unsigned int input_color_depth;
253 enum hdmi_colorspace input_colorspace;
254 enum adv7511_input_clock input_clock;
255 unsigned int input_style;
256 enum adv7511_input_justification input_justification;
257
258 int clock_delay;
259
260 bool embedded_sync;
261 enum adv7511_input_sync_pulse sync_pulse;
262 enum adv7511_sync_polarity vsync_polarity;
263 enum adv7511_sync_polarity hsync_polarity;
264};
265
266/**
267 * enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC
268 * @ADV7511_CSC_SCALING_1: CSC results are not scaled
269 * @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two
270 * @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four
271 */
272enum adv7511_csc_scaling {
273 ADV7511_CSC_SCALING_1 = 0,
274 ADV7511_CSC_SCALING_2 = 1,
275 ADV7511_CSC_SCALING_4 = 2,
276};
277
278/**
279 * struct adv7511_video_config - Describes adv7511 hardware configuration
280 * @csc_enable: Whether to enable color space conversion
281 * @csc_scaling_factor: Color space conversion scaling factor
282 * @csc_coefficents: Color space conversion coefficents
283 * @hdmi_mode: Whether to use HDMI or DVI output mode
284 * @avi_infoframe: HDMI infoframe
285 */
286struct adv7511_video_config {
287 bool csc_enable;
288 enum adv7511_csc_scaling csc_scaling_factor;
289 const uint16_t *csc_coefficents;
290
291 bool hdmi_mode;
292 struct hdmi_avi_infoframe avi_infoframe;
293};
294
Archit Taneja2437e7c2016-06-15 16:24:03 +0530295enum adv7511_type {
296 ADV7511,
297 ADV7533,
298};
299
300struct adv7511 {
301 struct i2c_client *i2c_main;
302 struct i2c_client *i2c_edid;
303 struct i2c_client *i2c_cec;
304
305 struct regmap *regmap;
306 struct regmap *regmap_cec;
307 enum drm_connector_status status;
308 bool powered;
309
Archit Taneja78fa4792016-06-15 17:03:12 +0530310 struct drm_display_mode curr_mode;
311
Archit Taneja2437e7c2016-06-15 16:24:03 +0530312 unsigned int f_tmds;
John Stultz53c515b2016-11-28 17:22:31 -0800313 unsigned int f_audio;
314 unsigned int audio_source;
Archit Taneja2437e7c2016-06-15 16:24:03 +0530315
316 unsigned int current_edid_segment;
317 uint8_t edid_buf[256];
318 bool edid_read;
319
320 wait_queue_head_t wq;
John Stultz518cb702017-01-16 16:52:47 -0800321 struct work_struct hpd_work;
322
Archit Taneja2437e7c2016-06-15 16:24:03 +0530323 struct drm_bridge bridge;
324 struct drm_connector connector;
325
326 bool embedded_sync;
327 enum adv7511_sync_polarity vsync_polarity;
328 enum adv7511_sync_polarity hsync_polarity;
329 bool rgb;
330
331 struct edid *edid;
332
333 struct gpio_desc *gpio_pd;
334
Archit Taneja5b06ba22017-01-11 12:22:27 +0530335 struct regulator_bulk_data *supplies;
336 unsigned int num_supplies;
337
Archit Taneja1e4d58c2016-06-15 17:01:27 +0530338 /* ADV7533 DSI RX related params */
339 struct device_node *host_node;
340 struct mipi_dsi_device *dsi;
341 u8 num_dsi_lanes;
Archit Taneja78fa4792016-06-15 17:03:12 +0530342 bool use_timing_gen;
Archit Taneja1e4d58c2016-06-15 17:01:27 +0530343
Archit Taneja2437e7c2016-06-15 16:24:03 +0530344 enum adv7511_type type;
John Stultz53c515b2016-11-28 17:22:31 -0800345 struct platform_device *audio_pdev;
Archit Taneja2437e7c2016-06-15 16:24:03 +0530346};
347
348#ifdef CONFIG_DRM_I2C_ADV7533
349void adv7533_dsi_power_on(struct adv7511 *adv);
350void adv7533_dsi_power_off(struct adv7511 *adv);
Archit Taneja62b2f022016-06-17 12:15:52 +0530351void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode);
Archit Taneja2437e7c2016-06-15 16:24:03 +0530352int adv7533_patch_registers(struct adv7511 *adv);
353void adv7533_uninit_cec(struct adv7511 *adv);
354int adv7533_init_cec(struct adv7511 *adv);
Archit Taneja1e4d58c2016-06-15 17:01:27 +0530355int adv7533_attach_dsi(struct adv7511 *adv);
356void adv7533_detach_dsi(struct adv7511 *adv);
357int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
Archit Taneja2437e7c2016-06-15 16:24:03 +0530358#else
359static inline void adv7533_dsi_power_on(struct adv7511 *adv)
360{
361}
362
363static inline void adv7533_dsi_power_off(struct adv7511 *adv)
364{
365}
366
Archit Taneja62b2f022016-06-17 12:15:52 +0530367static inline void adv7533_mode_set(struct adv7511 *adv,
368 struct drm_display_mode *mode)
369{
370}
371
Archit Taneja2437e7c2016-06-15 16:24:03 +0530372static inline int adv7533_patch_registers(struct adv7511 *adv)
373{
374 return -ENODEV;
375}
376
377static inline void adv7533_uninit_cec(struct adv7511 *adv)
378{
379}
380
381static inline int adv7533_init_cec(struct adv7511 *adv)
382{
383 return -ENODEV;
384}
Archit Taneja1e4d58c2016-06-15 17:01:27 +0530385
386static inline int adv7533_attach_dsi(struct adv7511 *adv)
387{
388 return -ENODEV;
389}
390
391static inline void adv7533_detach_dsi(struct adv7511 *adv)
392{
393}
394
395static inline int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv)
396{
397 return -ENODEV;
398}
Archit Taneja2437e7c2016-06-15 16:24:03 +0530399#endif
400
John Stultz53c515b2016-11-28 17:22:31 -0800401#ifdef CONFIG_DRM_I2C_ADV7511_AUDIO
402int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511);
403void adv7511_audio_exit(struct adv7511 *adv7511);
404#else /*CONFIG_DRM_I2C_ADV7511_AUDIO */
405static inline int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511)
406{
407 return 0;
408}
409static inline void adv7511_audio_exit(struct adv7511 *adv7511)
410{
411}
412#endif /* CONFIG_DRM_I2C_ADV7511_AUDIO */
413
Lars-Peter Clausen9c8af882012-03-05 16:30:57 +0100414#endif /* __DRM_I2C_ADV7511_H__ */