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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
Hyok S. Choi10c2df62006-03-27 10:21:34 +01005 * Copyright (C) 2004 Hyok S. Choi (MPU support)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/linkage.h>
12
13/*
14 * Debugging stuff
15 *
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
19 */
20#ifdef DEBUG
Russell King5cd0c342005-05-03 12:18:46 +010021
Russell King5cd0c342005-05-03 12:18:46 +010022#if defined(CONFIG_DEBUG_ICEDCC)
Tony Lindgren7d95ded2006-09-20 13:03:34 +010023
Stephen Boyddfad5492011-03-23 22:46:15 +010024#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
Tony Lindgren4e6d4882010-02-01 23:26:53 +010025 .macro loadsp, rb, tmp
Tony Lindgren7d95ded2006-09-20 13:03:34 +010026 .endm
27 .macro writeb, ch, rb
28 mcr p14, 0, \ch, c0, c5, 0
29 .endm
Jean-Christop PLAGNIOL-VILLARDc633c3c2009-02-25 04:20:40 +010030#elif defined(CONFIG_CPU_XSCALE)
Tony Lindgren4e6d4882010-02-01 23:26:53 +010031 .macro loadsp, rb, tmp
Jean-Christop PLAGNIOL-VILLARDc633c3c2009-02-25 04:20:40 +010032 .endm
33 .macro writeb, ch, rb
34 mcr p14, 0, \ch, c8, c0, 0
35 .endm
Tony Lindgren7d95ded2006-09-20 13:03:34 +010036#else
Tony Lindgren4e6d4882010-02-01 23:26:53 +010037 .macro loadsp, rb, tmp
Linus Torvalds1da177e2005-04-16 15:20:36 -070038 .endm
Russell King224b5be2005-11-16 14:59:51 +000039 .macro writeb, ch, rb
Uwe Kleine-König41a9e682007-12-13 09:31:34 +010040 mcr p14, 0, \ch, c1, c0, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070041 .endm
Tony Lindgren7d95ded2006-09-20 13:03:34 +010042#endif
43
Russell King5cd0c342005-05-03 12:18:46 +010044#else
Russell King224b5be2005-11-16 14:59:51 +000045
Russell Kinga09e64f2008-08-05 16:14:15 +010046#include <mach/debug-macro.S>
Russell King224b5be2005-11-16 14:59:51 +000047
Russell King5cd0c342005-05-03 12:18:46 +010048 .macro writeb, ch, rb
49 senduart \ch, \rb
50 .endm
51
Russell King224b5be2005-11-16 14:59:51 +000052#if defined(CONFIG_ARCH_SA1100)
Tony Lindgren4e6d4882010-02-01 23:26:53 +010053 .macro loadsp, rb, tmp
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 mov \rb, #0x80000000 @ physical base address
Russell King224b5be2005-11-16 14:59:51 +000055#ifdef CONFIG_DEBUG_LL_SER3
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 add \rb, \rb, #0x00050000 @ Ser3
Russell King224b5be2005-11-16 14:59:51 +000057#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 add \rb, \rb, #0x00010000 @ Ser1
Russell King224b5be2005-11-16 14:59:51 +000059#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 .endm
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#elif defined(CONFIG_ARCH_S3C2410)
Tony Lindgren4e6d4882010-02-01 23:26:53 +010062 .macro loadsp, rb, tmp
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 mov \rb, #0x50000000
Ben Dooksc7657842007-07-22 16:11:20 +010064 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 .endm
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#else
Tony Lindgren4e6d4882010-02-01 23:26:53 +010067 .macro loadsp, rb, tmp
68 addruart \rb, \tmp
Russell King224b5be2005-11-16 14:59:51 +000069 .endm
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#endif
71#endif
Russell King5cd0c342005-05-03 12:18:46 +010072#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74 .macro kputc,val
75 mov r0, \val
76 bl putc
77 .endm
78
79 .macro kphex,val,len
80 mov r0, \val
81 mov r1, #\len
82 bl phex
83 .endm
84
85 .macro debug_reloc_start
86#ifdef DEBUG
87 kputc #'\n'
88 kphex r6, 8 /* processor id */
89 kputc #':'
90 kphex r7, 8 /* architecture id */
Hyok S. Choif12d0d72006-09-26 17:36:37 +090091#ifdef CONFIG_CPU_CP15
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 kputc #':'
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
Hyok S. Choif12d0d72006-09-26 17:36:37 +090095#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 kputc #'\n'
97 kphex r5, 8 /* decompressed kernel start */
98 kputc #'-'
Russell Kingf4619022006-01-12 17:17:57 +000099 kphex r9, 8 /* decompressed kernel end */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 kputc #'>'
101 kphex r4, 8 /* kernel execution address */
102 kputc #'\n'
103#endif
104 .endm
105
106 .macro debug_reloc_end
107#ifdef DEBUG
108 kphex r5, 8 /* end of kernel */
109 kputc #'\n'
110 mov r0, r4
111 bl memdump /* dump 256 bytes at start of kernel */
112#endif
113 .endm
114
115 .section ".start", #alloc, #execinstr
116/*
117 * sort out different calling conventions
118 */
119 .align
Dave Martin26e5ca92010-11-29 19:43:27 +0100120 .arm @ Always enter in ARM state
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121start:
122 .type start,#function
Nicolas Pitreb11fe382011-02-12 22:25:27 +0100123 .rept 7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124 mov r0, r0
125 .endr
Nicolas Pitreb11fe382011-02-12 22:25:27 +0100126 ARM( mov r0, r0 )
127 ARM( b 1f )
128 THUMB( adr r12, BSYM(1f) )
129 THUMB( bx r12 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 .word 0x016f2818 @ Magic numbers to help the loader
132 .word start @ absolute load/run zImage address
133 .word _edata @ zImage end address
Dave Martin26e5ca92010-11-29 19:43:27 +0100134 THUMB( .thumb )
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351: mov r7, r1 @ save architecture ID
Russell Kingf4619022006-01-12 17:17:57 +0000136 mov r8, r2 @ save atags pointer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
138#ifndef __ARM_ARCH_2__
139 /*
140 * Booting from Angel - need to enter SVC mode and disable
141 * FIQs/IRQs (numeric definitions from angel arm.h source).
142 * We only do this if we were in user mode on entry.
143 */
144 mrs r2, cpsr @ get current mode
145 tst r2, #3 @ not user?
146 bne not_angel
147 mov r0, #0x17 @ angel_SWIreason_EnterSVC
Catalin Marinas0e056f22009-07-24 12:32:58 +0100148 ARM( swi 0x123456 ) @ angel_SWI_ARM
149 THUMB( svc 0xab ) @ angel_SWI_THUMB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150not_angel:
151 mrs r2, cpsr @ turn off interrupts to
152 orr r2, r2, #0xc0 @ prevent angel from running
153 msr cpsr_c, r2
154#else
155 teqp pc, #0x0c000003 @ turn off interrupts
156#endif
157
158 /*
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
161 */
162
163 /*
164 * some architecture specific code can be inserted
Russell Kingf4619022006-01-12 17:17:57 +0000165 * by the linker here, but it should preserve r7, r8, and r9.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 */
167
168 .text
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100169
Eric Miaoe69edc792010-07-05 15:56:50 +0200170#ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
Dave Martinbfa64c42010-11-29 19:43:26 +0100172 mov r4, pc
173 and r4, r4, #0xf8000000
Eric Miaoe69edc792010-07-05 15:56:50 +0200174 add r4, r4, #TEXT_OFFSET
175#else
Russell King9e84ed62010-09-09 22:39:41 +0100176 ldr r4, =zreladdr
Eric Miaoe69edc792010-07-05 15:56:50 +0200177#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100179 bl cache_on
180
181restart: adr r0, LC0
Nicolas Pitre34cc1a82011-04-19 15:42:43 -0400182 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
Nicolas Pitreadcc2592011-04-27 16:15:11 -0400183 ldr sp, [r0, #28]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184
185 /*
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100186 * We might be running at a different address. We need
187 * to fix up various pointers.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 */
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100189 sub r0, r0, r1 @ calculate the delta offset
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100190 add r6, r6, r0 @ _edata
Nicolas Pitre34cc1a82011-04-19 15:42:43 -0400191 add r10, r10, r0 @ inflated kernel size location
192
193 /*
194 * The kernel build system appends the size of the
195 * decompressed kernel at the end of the compressed data
196 * in little-endian form.
197 */
198 ldrb r9, [r10, #0]
199 ldrb lr, [r10, #1]
200 orr r9, r9, lr, lsl #8
201 ldrb lr, [r10, #2]
202 ldrb r10, [r10, #3]
203 orr r9, r9, lr, lsl #16
204 orr r9, r9, r10, lsl #24
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100205
206#ifndef CONFIG_ZBOOT_ROM
207 /* malloc space is above the relocated stack (64k max) */
208 add sp, sp, r0
209 add r10, sp, #0x10000
210#else
211 /*
212 * With ZBOOT_ROM the bss/stack is non relocatable,
213 * but someone could still run this code from RAM,
214 * in which case our reference is _edata.
215 */
216 mov r10, r6
217#endif
218
219/*
220 * Check to see if we will overwrite ourselves.
221 * r4 = final kernel address
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100222 * r9 = size of decompressed image
223 * r10 = end of this image, including bss/stack/malloc space if non XIP
224 * We basically want:
Nicolas Pitreea9df3b2011-04-21 22:52:06 -0400225 * r4 - 16k page directory >= r10 -> OK
Nicolas Pitreadcc2592011-04-27 16:15:11 -0400226 * r4 + image length <= current position (pc) -> OK
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100227 */
Nicolas Pitreea9df3b2011-04-21 22:52:06 -0400228 add r10, r10, #16384
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100229 cmp r4, r10
230 bhs wont_overwrite
231 add r10, r4, r9
Nicolas Pitreadcc2592011-04-27 16:15:11 -0400232 ARM( cmp r10, pc )
233 THUMB( mov lr, pc )
234 THUMB( cmp r10, lr )
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100235 bls wont_overwrite
236
237/*
238 * Relocate ourselves past the end of the decompressed kernel.
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100239 * r6 = _edata
240 * r10 = end of the decompressed kernel
241 * Because we always copy ahead, we need to do it from the end and go
242 * backward in case the source and destination overlap.
243 */
Nicolas Pitreadcc2592011-04-27 16:15:11 -0400244 /*
245 * Bump to the next 256-byte boundary with the size of
246 * the relocation code added. This avoids overwriting
247 * ourself when the offset is small.
248 */
249 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100250 bic r10, r10, #255
251
Nicolas Pitreadcc2592011-04-27 16:15:11 -0400252 /* Get start of code we want to copy and align it down. */
253 adr r5, restart
254 bic r5, r5, #31
255
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100256 sub r9, r6, r5 @ size to copy
257 add r9, r9, #31 @ rounded up to a multiple
258 bic r9, r9, #31 @ ... of 32 bytes
259 add r6, r9, r5
260 add r9, r9, r10
261
2621: ldmdb r6!, {r0 - r3, r10 - r12, lr}
263 cmp r6, r5
264 stmdb r9!, {r0 - r3, r10 - r12, lr}
265 bhi 1b
266
267 /* Preserve offset to relocated code. */
268 sub r6, r9, r6
269
Tony Lindgren7c2527f2011-04-26 05:37:46 -0700270#ifndef CONFIG_ZBOOT_ROM
271 /* cache_clean_flush may use the stack, so relocate it */
272 add sp, sp, r6
273#endif
274
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100275 bl cache_clean_flush
276
277 adr r0, BSYM(restart)
278 add r0, r0, r6
279 mov pc, r0
280
281wont_overwrite:
282/*
283 * If delta is zero, we are running at the address we were linked at.
284 * r0 = delta
285 * r2 = BSS start
286 * r3 = BSS end
287 * r4 = kernel execution address
288 * r7 = architecture ID
289 * r8 = atags pointer
290 * r11 = GOT start
291 * r12 = GOT end
292 * sp = stack pointer
293 */
294 teq r0, #0
295 beq not_relocated
Russell King98e12b52010-02-25 23:56:38 +0000296 add r11, r11, r0
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100297 add r12, r12, r0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298
299#ifndef CONFIG_ZBOOT_ROM
300 /*
301 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
302 * we need to fix up pointers into the BSS region.
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100303 * Note that the stack pointer has already been fixed up.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 */
305 add r2, r2, r0
306 add r3, r3, r0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307
308 /*
309 * Relocate all entries in the GOT table.
310 */
Russell King98e12b52010-02-25 23:56:38 +00003111: ldr r1, [r11, #0] @ relocate entries in the GOT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 add r1, r1, r0 @ table. This fixes up the
Russell King98e12b52010-02-25 23:56:38 +0000313 str r1, [r11], #4 @ C references.
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100314 cmp r11, r12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 blo 1b
316#else
317
318 /*
319 * Relocate entries in the GOT table. We only relocate
320 * the entries that are outside the (relocated) BSS region.
321 */
Russell King98e12b52010-02-25 23:56:38 +00003221: ldr r1, [r11, #0] @ relocate entries in the GOT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 cmp r1, r2 @ entry < bss_start ||
324 cmphs r3, r1 @ _end < entry
325 addlo r1, r1, r0 @ table. This fixes up the
Russell King98e12b52010-02-25 23:56:38 +0000326 str r1, [r11], #4 @ C references.
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100327 cmp r11, r12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 blo 1b
329#endif
330
331not_relocated: mov r0, #0
3321: str r0, [r2], #4 @ clear bss
333 str r0, [r2], #4
334 str r0, [r2], #4
335 str r0, [r2], #4
336 cmp r2, r3
337 blo 1b
338
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100339/*
340 * The C runtime environment should now be setup sufficiently.
341 * Set up some pointers, and start decompressing.
342 * r4 = kernel execution address
343 * r7 = architecture ID
344 * r8 = atags pointer
345 */
346 mov r0, r4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 mov r1, sp @ malloc space above stack
348 add r2, sp, #0x10000 @ 64k max
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 mov r3, r7
350 bl decompress_kernel
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 bl cache_clean_flush
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100352 bl cache_off
353 mov r0, #0 @ must be zero
354 mov r1, r7 @ restore architecture number
355 mov r2, r8 @ restore atags pointer
356 mov pc, r4 @ call kernel
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357
Catalin Marinas88987ef2009-07-24 12:32:52 +0100358 .align 2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 .type LC0, #object
360LC0: .word LC0 @ r1
361 .word __bss_start @ r2
362 .word _end @ r3
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100363 .word _edata @ r6
Nicolas Pitre34cc1a82011-04-19 15:42:43 -0400364 .word input_data_end - 4 @ r10 (inflated size location)
Russell King98e12b52010-02-25 23:56:38 +0000365 .word _got_start @ r11
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 .word _got_end @ ip
Nicolas Pitre8d7e4cc2011-04-27 14:54:39 -0400367 .word .L_user_stack_end @ sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368 .size LC0, . - LC0
369
370#ifdef CONFIG_ARCH_RPC
371 .globl params
Eric Miaodb7b2b42010-06-03 15:36:49 +0800372params: ldr r0, =0x10000100 @ params_phys for RPC
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 mov pc, lr
374 .ltorg
375 .align
376#endif
377
378/*
379 * Turn on the cache. We need to setup some page tables so that we
380 * can have both the I and D caches on.
381 *
382 * We place the page tables 16k down from the kernel execution address,
383 * and we hope that nothing else is using it. If we're using it, we
384 * will go pop!
385 *
386 * On entry,
387 * r4 = kernel execution address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 * r7 = architecture number
Russell Kingf4619022006-01-12 17:17:57 +0000389 * r8 = atags pointer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390 * On exit,
Uwe Kleine-König21b28412010-01-26 22:08:09 +0100391 * r0, r1, r2, r3, r9, r10, r12 corrupted
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 * This routine must preserve:
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100393 * r4, r7, r8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 */
395 .align 5
396cache_on: mov r3, #8 @ cache_on function
397 b call_cache_fn
398
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100399/*
400 * Initialize the highest priority protection region, PR7
401 * to cover all 32bit address and cacheable and bufferable.
402 */
403__armv4_mpu_cache_on:
404 mov r0, #0x3f @ 4G, the whole
405 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
406 mcr p15, 0, r0, c6, c7, 1
407
408 mov r0, #0x80 @ PR7
409 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
410 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
411 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
412
413 mov r0, #0xc000
414 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
415 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
416
417 mov r0, #0
418 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
419 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
420 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
421 mrc p15, 0, r0, c1, c0, 0 @ read control reg
422 @ ...I .... ..D. WC.M
423 orr r0, r0, #0x002d @ .... .... ..1. 11.1
424 orr r0, r0, #0x1000 @ ...1 .... .... ....
425
426 mcr p15, 0, r0, c1, c0, 0 @ write control reg
427
428 mov r0, #0
429 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
430 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
431 mov pc, lr
432
433__armv3_mpu_cache_on:
434 mov r0, #0x3f @ 4G, the whole
435 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
436
437 mov r0, #0x80 @ PR7
438 mcr p15, 0, r0, c2, c0, 0 @ cache on
439 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
440
441 mov r0, #0xc000
442 mcr p15, 0, r0, c5, c0, 0 @ access permission
443
444 mov r0, #0
445 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
Uwe Kleine-König4a8d57a2010-01-26 22:14:23 +0100446 /*
447 * ?? ARMv3 MMU does not allow reading the control register,
448 * does this really work on ARMv3 MPU?
449 */
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100450 mrc p15, 0, r0, c1, c0, 0 @ read control reg
451 @ .... .... .... WC.M
452 orr r0, r0, #0x000d @ .... .... .... 11.1
Uwe Kleine-König4a8d57a2010-01-26 22:14:23 +0100453 /* ?? this overwrites the value constructed above? */
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100454 mov r0, #0
455 mcr p15, 0, r0, c1, c0, 0 @ write control reg
456
Uwe Kleine-König4a8d57a2010-01-26 22:14:23 +0100457 /* ?? invalidate for the second time? */
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100458 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
459 mov pc, lr
460
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461__setup_mmu: sub r3, r4, #16384 @ Page directory size
462 bic r3, r3, #0xff @ Align the pointer
463 bic r3, r3, #0x3f00
464/*
465 * Initialise the page tables, turning on the cacheable and bufferable
466 * bits for the RAM area only.
467 */
468 mov r0, r3
Russell Kingf4619022006-01-12 17:17:57 +0000469 mov r9, r0, lsr #18
470 mov r9, r9, lsl #18 @ start of RAM
471 add r10, r9, #0x10000000 @ a reasonable RAM size
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 mov r1, #0x12
473 orr r1, r1, #3 << 10
474 add r2, r3, #16384
Nicolas Pitre265d5e42006-01-18 22:38:51 +00004751: cmp r1, r9 @ if virt > start of RAM
Mark A. Greeraf3e4fd2011-04-01 15:41:26 +0100476#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
477 orrhs r1, r1, #0x08 @ set cacheable
478#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 orrhs r1, r1, #0x0c @ set cacheable, bufferable
Mark A. Greeraf3e4fd2011-04-01 15:41:26 +0100480#endif
Russell Kingf4619022006-01-12 17:17:57 +0000481 cmp r1, r10 @ if virt > end of RAM
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482 bichs r1, r1, #0x0c @ clear cacheable, bufferable
483 str r1, [r0], #4 @ 1:1 mapping
484 add r1, r1, #1048576
485 teq r0, r2
486 bne 1b
487/*
488 * If ever we are running from Flash, then we surely want the cache
489 * to be enabled also for our execution instance... We map 2MB of it
490 * so there is no map overlap problem for up to 1 MB compressed kernel.
491 * If the execution is in RAM then we would only be duplicating the above.
492 */
493 mov r1, #0x1e
494 orr r1, r1, #3 << 10
Dave Martinbfa64c42010-11-29 19:43:26 +0100495 mov r2, pc
496 mov r2, r2, lsr #20
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 orr r1, r1, r2, lsl #20
498 add r0, r3, r2, lsl #2
499 str r1, [r0], #4
500 add r1, r1, #1048576
501 str r1, [r0]
502 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100503ENDPROC(__setup_mmu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504
Mark A. Greeraf3e4fd2011-04-01 15:41:26 +0100505__arm926ejs_mmu_cache_on:
506#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
507 mov r0, #4 @ put dcache in WT mode
508 mcr p15, 7, r0, c15, c0, 0
509#endif
510
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000511__armv4_mmu_cache_on:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512 mov r12, lr
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100513#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 bl __setup_mmu
515 mov r0, #0
516 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
517 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
518 mrc p15, 0, r0, c1, c0, 0 @ read control reg
519 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
520 orr r0, r0, #0x0030
Catalin Marinas26584852009-05-30 14:00:18 +0100521#ifdef CONFIG_CPU_ENDIAN_BE8
522 orr r0, r0, #1 << 25 @ big-endian page tables
523#endif
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000524 bl __common_mmu_cache_on
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 mov r0, #0
526 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100527#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 mov pc, r12
529
Catalin Marinas7d09e852007-06-01 17:14:53 +0100530__armv7_mmu_cache_on:
531 mov r12, lr
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100532#ifdef CONFIG_MMU
Catalin Marinas7d09e852007-06-01 17:14:53 +0100533 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
534 tst r11, #0xf @ VMSA
535 blne __setup_mmu
536 mov r0, #0
537 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
538 tst r11, #0xf @ VMSA
539 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100540#endif
Catalin Marinas7d09e852007-06-01 17:14:53 +0100541 mrc p15, 0, r0, c1, c0, 0 @ read control reg
542 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
543 orr r0, r0, #0x003c @ write buffer
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100544#ifdef CONFIG_MMU
Catalin Marinas26584852009-05-30 14:00:18 +0100545#ifdef CONFIG_CPU_ENDIAN_BE8
546 orr r0, r0, #1 << 25 @ big-endian page tables
547#endif
Catalin Marinas7d09e852007-06-01 17:14:53 +0100548 orrne r0, r0, #1 @ MMU enabled
549 movne r1, #-1
550 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
551 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100552#endif
Catalin Marinas7d09e852007-06-01 17:14:53 +0100553 mcr p15, 0, r0, c1, c0, 0 @ load control register
554 mrc p15, 0, r0, c1, c0, 0 @ and read it back
555 mov r0, #0
556 mcr p15, 0, r0, c7, c5, 4 @ ISB
557 mov pc, r12
558
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200559__fa526_cache_on:
560 mov r12, lr
561 bl __setup_mmu
562 mov r0, #0
563 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
564 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
565 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
566 mrc p15, 0, r0, c1, c0, 0 @ read control reg
567 orr r0, r0, #0x1000 @ I-cache enable
568 bl __common_mmu_cache_on
569 mov r0, #0
570 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
571 mov pc, r12
572
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000573__arm6_mmu_cache_on:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574 mov r12, lr
575 bl __setup_mmu
576 mov r0, #0
577 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
578 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
579 mov r0, #0x30
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000580 bl __common_mmu_cache_on
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581 mov r0, #0
582 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
583 mov pc, r12
584
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000585__common_mmu_cache_on:
Catalin Marinas0e056f22009-07-24 12:32:58 +0100586#ifndef CONFIG_THUMB2_KERNEL
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587#ifndef DEBUG
588 orr r0, r0, #0x000d @ Write buffer, mmu
589#endif
590 mov r1, #-1
591 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
592 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
Nicolas Pitre2dc76672006-07-01 21:29:32 +0100593 b 1f
594 .align 5 @ cache line aligned
5951: mcr p15, 0, r0, c1, c0, 0 @ load control register
596 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
597 sub pc, lr, r0, lsr #32 @ properly flush pipeline
Catalin Marinas0e056f22009-07-24 12:32:58 +0100598#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599
600/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 * Here follow the relocatable cache support functions for the
602 * various processors. This is a generic hook for locating an
603 * entry and jumping to an instruction at the specified offset
604 * from the start of the block. Please note this is all position
605 * independent code.
606 *
607 * r1 = corrupted
608 * r2 = corrupted
609 * r3 = block offset
Russell King98e12b52010-02-25 23:56:38 +0000610 * r9 = corrupted
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 * r12 = corrupted
612 */
613
614call_cache_fn: adr r12, proc_types
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900615#ifdef CONFIG_CPU_CP15
Russell King98e12b52010-02-25 23:56:38 +0000616 mrc p15, 0, r9, c0, c0 @ get processor ID
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900617#else
Russell King98e12b52010-02-25 23:56:38 +0000618 ldr r9, =CONFIG_PROCESSOR_ID
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900619#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07006201: ldr r1, [r12, #0] @ get value
621 ldr r2, [r12, #4] @ get mask
Russell King98e12b52010-02-25 23:56:38 +0000622 eor r1, r1, r9 @ (real ^ match)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 tst r1, r2 @ & mask
Catalin Marinas0e056f22009-07-24 12:32:58 +0100624 ARM( addeq pc, r12, r3 ) @ call cache function
625 THUMB( addeq r12, r3 )
626 THUMB( moveq pc, r12 ) @ call cache function
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 add r12, r12, #4*5
628 b 1b
629
630/*
631 * Table for cache operations. This is basically:
632 * - CPU ID match
633 * - CPU ID mask
634 * - 'cache on' method instruction
635 * - 'cache off' method instruction
636 * - 'cache flush' method instruction
637 *
638 * We match an entry using: ((real_id ^ match) & mask) == 0
639 *
640 * Writethrough caches generally only need 'on' and 'off'
641 * methods. Writeback caches _must_ have the flush method
642 * defined.
643 */
Catalin Marinas88987ef2009-07-24 12:32:52 +0100644 .align 2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 .type proc_types,#object
646proc_types:
647 .word 0x41560600 @ ARM6/610
648 .word 0xffffffe0
Catalin Marinas0e056f22009-07-24 12:32:58 +0100649 W(b) __arm6_mmu_cache_off @ works, but slow
650 W(b) __arm6_mmu_cache_off
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100652 THUMB( nop )
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000653@ b __arm6_mmu_cache_on @ untested
654@ b __arm6_mmu_cache_off
655@ b __armv3_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656
657 .word 0x00000000 @ old ARM ID
658 .word 0x0000f000
659 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100660 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100662 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100664 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665
666 .word 0x41007000 @ ARM7/710
667 .word 0xfff8fe00
Catalin Marinas0e056f22009-07-24 12:32:58 +0100668 W(b) __arm7_mmu_cache_off
669 W(b) __arm7_mmu_cache_off
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100671 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672
673 .word 0x41807200 @ ARM720T (writethrough)
674 .word 0xffffff00
Catalin Marinas0e056f22009-07-24 12:32:58 +0100675 W(b) __armv4_mmu_cache_on
676 W(b) __armv4_mmu_cache_off
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100678 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100680 .word 0x41007400 @ ARM74x
681 .word 0xff00ff00
Catalin Marinas0e056f22009-07-24 12:32:58 +0100682 W(b) __armv3_mpu_cache_on
683 W(b) __armv3_mpu_cache_off
684 W(b) __armv3_mpu_cache_flush
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100685
686 .word 0x41009400 @ ARM94x
687 .word 0xff00ff00
Catalin Marinas0e056f22009-07-24 12:32:58 +0100688 W(b) __armv4_mpu_cache_on
689 W(b) __armv4_mpu_cache_off
690 W(b) __armv4_mpu_cache_flush
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100691
Mark A. Greeraf3e4fd2011-04-01 15:41:26 +0100692 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
693 .word 0xff0ffff0
Nicolas Pitre720c60e2011-06-09 05:05:27 +0100694 W(b) __arm926ejs_mmu_cache_on
695 W(b) __armv4_mmu_cache_off
696 W(b) __armv5tej_mmu_cache_flush
Mark A. Greeraf3e4fd2011-04-01 15:41:26 +0100697
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 .word 0x00007000 @ ARM7 IDs
699 .word 0x0000f000
700 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100701 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100703 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100705 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706
707 @ Everything from here on will be the new ID system.
708
709 .word 0x4401a100 @ sa110 / sa1100
710 .word 0xffffffe0
Catalin Marinas0e056f22009-07-24 12:32:58 +0100711 W(b) __armv4_mmu_cache_on
712 W(b) __armv4_mmu_cache_off
713 W(b) __armv4_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714
715 .word 0x6901b110 @ sa1110
716 .word 0xfffffff0
Catalin Marinas0e056f22009-07-24 12:32:58 +0100717 W(b) __armv4_mmu_cache_on
718 W(b) __armv4_mmu_cache_off
719 W(b) __armv4_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720
Haojian Zhuang4157d312010-03-12 05:47:55 -0500721 .word 0x56056900
722 .word 0xffffff00 @ PXA9xx
Catalin Marinas0e056f22009-07-24 12:32:58 +0100723 W(b) __armv4_mmu_cache_on
724 W(b) __armv4_mmu_cache_off
725 W(b) __armv4_mmu_cache_flush
Eric Miao59c7bcd2008-11-29 21:42:39 +0800726
Eric Miao49cbe782009-01-20 14:15:18 +0800727 .word 0x56158000 @ PXA168
728 .word 0xfffff000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100729 W(b) __armv4_mmu_cache_on
730 W(b) __armv4_mmu_cache_off
731 W(b) __armv5tej_mmu_cache_flush
Eric Miao49cbe782009-01-20 14:15:18 +0800732
Nicolas Pitre2e2023f2008-06-03 23:06:21 +0200733 .word 0x56050000 @ Feroceon
734 .word 0xff0f0000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100735 W(b) __armv4_mmu_cache_on
736 W(b) __armv4_mmu_cache_off
737 W(b) __armv5tej_mmu_cache_flush
Nicolas Pitre3ebb5a22007-10-31 15:31:48 -0400738
Joonyoung Shim55879312009-06-16 20:05:57 +0900739#ifdef CONFIG_CPU_FEROCEON_OLD_ID
740 /* this conflicts with the standard ARMv5TE entry */
741 .long 0x41009260 @ Old Feroceon
742 .long 0xff00fff0
743 b __armv4_mmu_cache_on
744 b __armv4_mmu_cache_off
745 b __armv5tej_mmu_cache_flush
746#endif
747
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200748 .word 0x66015261 @ FA526
749 .word 0xff01fff1
Catalin Marinas0e056f22009-07-24 12:32:58 +0100750 W(b) __fa526_cache_on
751 W(b) __armv4_mmu_cache_off
752 W(b) __fa526_cache_flush
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200753
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 @ These match on the architecture ID
755
756 .word 0x00020000 @ ARMv4T
757 .word 0x000f0000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100758 W(b) __armv4_mmu_cache_on
759 W(b) __armv4_mmu_cache_off
760 W(b) __armv4_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761
762 .word 0x00050000 @ ARMv5TE
763 .word 0x000f0000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100764 W(b) __armv4_mmu_cache_on
765 W(b) __armv4_mmu_cache_off
766 W(b) __armv4_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767
768 .word 0x00060000 @ ARMv5TEJ
769 .word 0x000f0000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100770 W(b) __armv4_mmu_cache_on
771 W(b) __armv4_mmu_cache_off
Sascha Hauer75216852010-03-15 15:14:50 +0100772 W(b) __armv5tej_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773
Catalin Marinas45a7b9c2006-06-18 16:21:50 +0100774 .word 0x0007b000 @ ARMv6
Catalin Marinas7d09e852007-06-01 17:14:53 +0100775 .word 0x000ff000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100776 W(b) __armv4_mmu_cache_on
777 W(b) __armv4_mmu_cache_off
778 W(b) __armv6_mmu_cache_flush
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779
Catalin Marinas7d09e852007-06-01 17:14:53 +0100780 .word 0x000f0000 @ new CPU Id
781 .word 0x000f0000
Catalin Marinas0e056f22009-07-24 12:32:58 +0100782 W(b) __armv7_mmu_cache_on
783 W(b) __armv7_mmu_cache_off
784 W(b) __armv7_mmu_cache_flush
Catalin Marinas7d09e852007-06-01 17:14:53 +0100785
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 .word 0 @ unrecognised type
787 .word 0
788 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100789 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100791 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 mov pc, lr
Catalin Marinas0e056f22009-07-24 12:32:58 +0100793 THUMB( nop )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794
795 .size proc_types, . - proc_types
796
797/*
798 * Turn off the Cache and MMU. ARMv3 does not support
799 * reading the control register, but ARMv4 does.
800 *
Uwe Kleine-König21b28412010-01-26 22:08:09 +0100801 * On exit,
802 * r0, r1, r2, r3, r9, r12 corrupted
803 * This routine must preserve:
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100804 * r4, r7, r8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 */
806 .align 5
807cache_off: mov r3, #12 @ cache_off function
808 b call_cache_fn
809
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100810__armv4_mpu_cache_off:
811 mrc p15, 0, r0, c1, c0
812 bic r0, r0, #0x000d
813 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
814 mov r0, #0
815 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
816 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
817 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
818 mov pc, lr
819
820__armv3_mpu_cache_off:
821 mrc p15, 0, r0, c1, c0
822 bic r0, r0, #0x000d
823 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
824 mov r0, #0
825 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
826 mov pc, lr
827
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000828__armv4_mmu_cache_off:
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100829#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 mrc p15, 0, r0, c1, c0
831 bic r0, r0, #0x000d
832 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
833 mov r0, #0
834 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
835 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100836#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 mov pc, lr
838
Catalin Marinas7d09e852007-06-01 17:14:53 +0100839__armv7_mmu_cache_off:
840 mrc p15, 0, r0, c1, c0
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100841#ifdef CONFIG_MMU
Catalin Marinas7d09e852007-06-01 17:14:53 +0100842 bic r0, r0, #0x000d
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100843#else
844 bic r0, r0, #0x000c
845#endif
Catalin Marinas7d09e852007-06-01 17:14:53 +0100846 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
847 mov r12, lr
848 bl __armv7_mmu_cache_flush
849 mov r0, #0
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100850#ifdef CONFIG_MMU
Catalin Marinas7d09e852007-06-01 17:14:53 +0100851 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
Catalin Marinas8bdca0a2009-07-24 12:35:06 +0100852#endif
Catalin Marinasc30c2f92008-11-06 13:23:07 +0000853 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
854 mcr p15, 0, r0, c7, c10, 4 @ DSB
855 mcr p15, 0, r0, c7, c5, 4 @ ISB
Catalin Marinas7d09e852007-06-01 17:14:53 +0100856 mov pc, r12
857
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000858__arm6_mmu_cache_off:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 mov r0, #0x00000030 @ ARM6 control reg.
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000860 b __armv3_mmu_cache_off
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000862__arm7_mmu_cache_off:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 mov r0, #0x00000070 @ ARM7 control reg.
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000864 b __armv3_mmu_cache_off
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000866__armv3_mmu_cache_off:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
868 mov r0, #0
869 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
870 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
871 mov pc, lr
872
873/*
874 * Clean and flush the cache to maintain consistency.
875 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 * On exit,
Uwe Kleine-König21b28412010-01-26 22:08:09 +0100877 * r1, r2, r3, r9, r10, r11, r12 corrupted
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 * This routine must preserve:
Nicolas Pitre6d7d0ae2011-02-21 07:06:45 +0100879 * r4, r6, r7, r8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880 */
881 .align 5
882cache_clean_flush:
883 mov r3, #16
884 b call_cache_fn
885
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100886__armv4_mpu_cache_flush:
887 mov r2, #1
888 mov r3, #0
889 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
890 mov r1, #7 << 5 @ 8 segments
8911: orr r3, r1, #63 << 26 @ 64 entries
8922: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
893 subs r3, r3, #1 << 26
894 bcs 2b @ entries 63 to 0
895 subs r1, r1, #1 << 5
896 bcs 1b @ segments 7 to 0
897
898 teq r2, #0
899 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
900 mcr p15, 0, ip, c7, c10, 4 @ drain WB
901 mov pc, lr
902
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200903__fa526_cache_flush:
904 mov r1, #0
905 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
906 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
907 mcr p15, 0, r1, c7, c10, 4 @ drain WB
908 mov pc, lr
Hyok S. Choi10c2df62006-03-27 10:21:34 +0100909
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000910__armv6_mmu_cache_flush:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911 mov r1, #0
912 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
913 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
914 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
915 mcr p15, 0, r1, c7, c10, 4 @ drain WB
916 mov pc, lr
917
Catalin Marinas7d09e852007-06-01 17:14:53 +0100918__armv7_mmu_cache_flush:
919 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
920 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
Catalin Marinas7d09e852007-06-01 17:14:53 +0100921 mov r10, #0
Catalin Marinasc30c2f92008-11-06 13:23:07 +0000922 beq hierarchical
Catalin Marinas7d09e852007-06-01 17:14:53 +0100923 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
924 b iflush
925hierarchical:
Catalin Marinasc30c2f92008-11-06 13:23:07 +0000926 mcr p15, 0, r10, c7, c10, 5 @ DMB
Catalin Marinas0e056f22009-07-24 12:32:58 +0100927 stmfd sp!, {r0-r7, r9-r11}
Catalin Marinas7d09e852007-06-01 17:14:53 +0100928 mrc p15, 1, r0, c0, c0, 1 @ read clidr
929 ands r3, r0, #0x7000000 @ extract loc from clidr
930 mov r3, r3, lsr #23 @ left align loc bit field
931 beq finished @ if loc is 0, then no need to clean
932 mov r10, #0 @ start clean at cache level 0
933loop1:
934 add r2, r10, r10, lsr #1 @ work out 3x current cache level
935 mov r1, r0, lsr r2 @ extract cache type bits from clidr
936 and r1, r1, #7 @ mask of the bits for current cache only
937 cmp r1, #2 @ see what cache we have at this level
938 blt skip @ skip if no cache, or just i-cache
939 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
940 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
941 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
942 and r2, r1, #7 @ extract the length of the cache lines
943 add r2, r2, #4 @ add 4 (line length offset)
944 ldr r4, =0x3ff
945 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
Catalin Marinas000b5022008-10-03 11:09:10 +0100946 clz r5, r4 @ find bit position of way size increment
Catalin Marinas7d09e852007-06-01 17:14:53 +0100947 ldr r7, =0x7fff
948 ands r7, r7, r1, lsr #13 @ extract max number of the index size
949loop2:
950 mov r9, r4 @ create working copy of max way size
951loop3:
Catalin Marinas0e056f22009-07-24 12:32:58 +0100952 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
953 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
954 THUMB( lsl r6, r9, r5 )
955 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
956 THUMB( lsl r6, r7, r2 )
957 THUMB( orr r11, r11, r6 ) @ factor index number into r11
Catalin Marinas7d09e852007-06-01 17:14:53 +0100958 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
959 subs r9, r9, #1 @ decrement the way
960 bge loop3
961 subs r7, r7, #1 @ decrement the index
962 bge loop2
963skip:
964 add r10, r10, #2 @ increment cache number
965 cmp r3, r10
966 bgt loop1
967finished:
Catalin Marinas0e056f22009-07-24 12:32:58 +0100968 ldmfd sp!, {r0-r7, r9-r11}
Catalin Marinas7d09e852007-06-01 17:14:53 +0100969 mov r10, #0 @ swith back to cache level 0
970 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
Catalin Marinas7d09e852007-06-01 17:14:53 +0100971iflush:
Catalin Marinasc30c2f92008-11-06 13:23:07 +0000972 mcr p15, 0, r10, c7, c10, 4 @ DSB
Catalin Marinas7d09e852007-06-01 17:14:53 +0100973 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
Catalin Marinasc30c2f92008-11-06 13:23:07 +0000974 mcr p15, 0, r10, c7, c10, 4 @ DSB
975 mcr p15, 0, r10, c7, c5, 4 @ ISB
Catalin Marinas7d09e852007-06-01 17:14:53 +0100976 mov pc, lr
977
Nicolas Pitre15754bf2007-10-31 15:15:29 -0400978__armv5tej_mmu_cache_flush:
9791: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
980 bne 1b
981 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
982 mcr p15, 0, r0, c7, c10, 4 @ drain WB
983 mov pc, lr
984
Hyok S. Choic76b6b42006-03-24 09:53:18 +0000985__armv4_mmu_cache_flush:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 mov r2, #64*1024 @ default: 32K dcache size (*2)
987 mov r11, #32 @ default: 32 byte line size
988 mrc p15, 0, r3, c0, c0, 1 @ read cache type
Russell King98e12b52010-02-25 23:56:38 +0000989 teq r3, r9 @ cache ID register present?
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 beq no_cache_id
991 mov r1, r3, lsr #18
992 and r1, r1, #7
993 mov r2, #1024
994 mov r2, r2, lsl r1 @ base dcache size *2
995 tst r3, #1 << 14 @ test M bit
996 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
997 mov r3, r3, lsr #12
998 and r3, r3, #3
999 mov r11, #8
1000 mov r11, r11, lsl r3 @ cache line size in bytes
1001no_cache_id:
Catalin Marinas0e056f22009-07-24 12:32:58 +01001002 mov r1, pc
1003 bic r1, r1, #63 @ align to longest cache line
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 add r2, r1, r2
Catalin Marinas0e056f22009-07-24 12:32:58 +010010051:
1006 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1007 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1008 THUMB( add r1, r1, r11 )
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 teq r1, r2
1010 bne 1b
1011
1012 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1013 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1014 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1015 mov pc, lr
1016
Hyok S. Choic76b6b42006-03-24 09:53:18 +00001017__armv3_mmu_cache_flush:
Hyok S. Choi10c2df62006-03-27 10:21:34 +01001018__armv3_mpu_cache_flush:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019 mov r1, #0
Uwe Kleine-König63fa7182010-01-26 22:18:09 +01001020 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 mov pc, lr
1022
1023/*
1024 * Various debugging routines for printing hex characters and
1025 * memory, which again must be relocatable.
1026 */
1027#ifdef DEBUG
Catalin Marinas88987ef2009-07-24 12:32:52 +01001028 .align 2
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 .type phexbuf,#object
1030phexbuf: .space 12
1031 .size phexbuf, . - phexbuf
1032
Uwe Kleine-Königbe6f9f02010-01-26 22:22:20 +01001033@ phex corrupts {r0, r1, r2, r3}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034phex: adr r3, phexbuf
1035 mov r2, #0
1036 strb r2, [r3, r1]
10371: subs r1, r1, #1
1038 movmi r0, r3
1039 bmi puts
1040 and r2, r0, #15
1041 mov r0, r0, lsr #4
1042 cmp r2, #10
1043 addge r2, r2, #7
1044 add r2, r2, #'0'
1045 strb r2, [r3, r1]
1046 b 1b
1047
Uwe Kleine-Königbe6f9f02010-01-26 22:22:20 +01001048@ puts corrupts {r0, r1, r2, r3}
Tony Lindgren4e6d4882010-02-01 23:26:53 +01001049puts: loadsp r3, r1
Linus Torvalds1da177e2005-04-16 15:20:36 -070010501: ldrb r2, [r0], #1
1051 teq r2, #0
1052 moveq pc, lr
Russell King5cd0c342005-05-03 12:18:46 +010010532: writeb r2, r3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054 mov r1, #0x00020000
10553: subs r1, r1, #1
1056 bne 3b
1057 teq r2, #'\n'
1058 moveq r2, #'\r'
1059 beq 2b
1060 teq r0, #0
1061 bne 1b
1062 mov pc, lr
Uwe Kleine-Königbe6f9f02010-01-26 22:22:20 +01001063@ putc corrupts {r0, r1, r2, r3}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064putc:
1065 mov r2, r0
1066 mov r0, #0
Tony Lindgren4e6d4882010-02-01 23:26:53 +01001067 loadsp r3, r1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 b 2b
1069
Uwe Kleine-Königbe6f9f02010-01-26 22:22:20 +01001070@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071memdump: mov r12, r0
1072 mov r10, lr
1073 mov r11, #0
10742: mov r0, r11, lsl #2
1075 add r0, r0, r12
1076 mov r1, #8
1077 bl phex
1078 mov r0, #':'
1079 bl putc
10801: mov r0, #' '
1081 bl putc
1082 ldr r0, [r12, r11, lsl #2]
1083 mov r1, #8
1084 bl phex
1085 and r0, r11, #7
1086 teq r0, #3
1087 moveq r0, #' '
1088 bleq putc
1089 and r0, r11, #7
1090 add r11, r11, #1
1091 teq r0, #7
1092 bne 1b
1093 mov r0, #'\n'
1094 bl putc
1095 cmp r11, #64
1096 blt 2b
1097 mov pc, r10
1098#endif
1099
Catalin Marinas92c83ff12007-06-22 14:27:50 +01001100 .ltorg
Nicolas Pitreadcc2592011-04-27 16:15:11 -04001101reloc_code_end:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102
1103 .align
Russell Kingb0c4d4e2010-11-22 12:00:59 +00001104 .section ".stack", "aw", %nobits
Nicolas Pitre8d7e4cc2011-04-27 14:54:39 -04001105.L_user_stack: .space 4096
1106.L_user_stack_end: