blob: a1f3c1cf8f74652e541daa991786915eab708578 [file] [log] [blame]
Marc Zyngier9dddc2d2016-01-05 18:42:49 +00001/*
2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <asm/kvm_asm.h>
19#include "hyp.h"
20
21__asm__(".arch_extension virt");
22
23/*
24 * Activate the traps, saving the host's fpexc register before
25 * overwriting it. We'll restore it on VM exit.
26 */
27static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host)
28{
29 u32 val;
30
31 /*
32 * We are about to set HCPTR.TCP10/11 to trap all floating point
33 * register accesses to HYP, however, the ARM ARM clearly states that
34 * traps are only taken to HYP if the operation would not otherwise
35 * trap to SVC. Therefore, always make sure that for 32-bit guests,
36 * we set FPEXC.EN to prevent traps to SVC, when setting the TCP bits.
37 */
38 val = read_sysreg(VFP_FPEXC);
39 *fpexc_host = val;
40 if (!(val & FPEXC_EN)) {
41 write_sysreg(val | FPEXC_EN, VFP_FPEXC);
42 isb();
43 }
44
45 write_sysreg(vcpu->arch.hcr | vcpu->arch.irq_lines, HCR);
46 /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
47 write_sysreg(HSTR_T(15), HSTR);
48 write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR);
49 val = read_sysreg(HDCR);
50 write_sysreg(val | HDCR_TPM | HDCR_TPMCR, HDCR);
51}
52
53static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
54{
55 u32 val;
56
57 write_sysreg(0, HCR);
58 write_sysreg(0, HSTR);
59 val = read_sysreg(HDCR);
60 write_sysreg(val & ~(HDCR_TPM | HDCR_TPMCR), HDCR);
61 write_sysreg(0, HCPTR);
62}
63
64static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
65{
66 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
67 write_sysreg(kvm->arch.vttbr, VTTBR);
68 write_sysreg(vcpu->arch.midr, VPIDR);
69}
70
71static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
72{
73 write_sysreg(0, VTTBR);
74 write_sysreg(read_sysreg(MIDR), VPIDR);
75}
76
77static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
78{
79 __vgic_v2_save_state(vcpu);
80}
81
82static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
83{
84 __vgic_v2_restore_state(vcpu);
85}
86
87static int __hyp_text __guest_run(struct kvm_vcpu *vcpu)
88{
89 struct kvm_cpu_context *host_ctxt;
90 struct kvm_cpu_context *guest_ctxt;
91 bool fp_enabled;
92 u64 exit_code;
93 u32 fpexc;
94
95 vcpu = kern_hyp_va(vcpu);
96 write_sysreg(vcpu, HTPIDR);
97
98 host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
99 guest_ctxt = &vcpu->arch.ctxt;
100
101 __sysreg_save_state(host_ctxt);
102 __banked_save_state(host_ctxt);
103
104 __activate_traps(vcpu, &fpexc);
105 __activate_vm(vcpu);
106
107 __vgic_restore_state(vcpu);
108 __timer_restore_state(vcpu);
109
110 __sysreg_restore_state(guest_ctxt);
111 __banked_restore_state(guest_ctxt);
112
113 /* Jump in the fire! */
114 exit_code = __guest_enter(vcpu, host_ctxt);
115 /* And we're baaack! */
116
117 fp_enabled = __vfp_enabled();
118
119 __banked_save_state(guest_ctxt);
120 __sysreg_save_state(guest_ctxt);
121 __timer_save_state(vcpu);
122 __vgic_save_state(vcpu);
123
124 __deactivate_traps(vcpu);
125 __deactivate_vm(vcpu);
126
127 __banked_restore_state(host_ctxt);
128 __sysreg_restore_state(host_ctxt);
129
130 if (fp_enabled) {
131 __vfp_save_state(&guest_ctxt->vfp);
132 __vfp_restore_state(&host_ctxt->vfp);
133 }
134
135 write_sysreg(fpexc, VFP_FPEXC);
136
137 return exit_code;
138}
139
140__alias(__guest_run) int __weak __kvm_vcpu_run(struct kvm_vcpu *vcpu);