blob: 0fac6ea5f906959cc25bdb3acf6f9fd50dfc5836 [file] [log] [blame]
Rob Clarka7d3c952014-05-30 14:47:38 -04001/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/* For debugging crashes, userspace can:
19 *
20 * tail -f /sys/kernel/debug/dri/<minor>/rd > logfile.rd
21 *
Rob Clark2165e2b2017-09-15 09:04:52 -040022 * to log the cmdstream in a format that is understood by freedreno/cffdump
Rob Clarka7d3c952014-05-30 14:47:38 -040023 * utility. By comparing the last successfully completed fence #, to the
24 * cmdstream for the next fence, you can narrow down which process and submit
25 * caused the gpu crash/lockup.
26 *
Rob Clark2165e2b2017-09-15 09:04:52 -040027 * Additionally:
28 *
29 * tail -f /sys/kernel/debug/dri/<minor>/hangrd > logfile.rd
30 *
31 * will capture just the cmdstream from submits which triggered a GPU hang.
32 *
Rob Clarka7d3c952014-05-30 14:47:38 -040033 * This bypasses drm_debugfs_create_files() mainly because we need to use
34 * our own fops for a bit more control. In particular, we don't want to
35 * do anything if userspace doesn't have the debugfs file open.
Rob Clark79c21182016-06-16 11:54:41 -040036 *
37 * The module-param "rd_full", which defaults to false, enables snapshotting
38 * all (non-written) buffers in the submit, rather than just cmdstream bo's.
39 * This is useful to capture the contents of (for example) vbo's or textures,
40 * or shader programs (if not emitted inline in cmdstream).
Rob Clarka7d3c952014-05-30 14:47:38 -040041 */
42
43#ifdef CONFIG_DEBUG_FS
44
45#include <linux/kfifo.h>
46#include <linux/debugfs.h>
47#include <linux/circ_buf.h>
48#include <linux/wait.h>
49
50#include "msm_drv.h"
51#include "msm_gpu.h"
52#include "msm_gem.h"
53
Rob Clark79c21182016-06-16 11:54:41 -040054static bool rd_full = false;
55MODULE_PARM_DESC(rd_full, "If true, $debugfs/.../rd will snapshot all buffer contents");
56module_param_named(rd_full, rd_full, bool, 0600);
57
Rob Clarka7d3c952014-05-30 14:47:38 -040058enum rd_sect_type {
59 RD_NONE,
60 RD_TEST, /* ascii text */
61 RD_CMD, /* ascii text */
62 RD_GPUADDR, /* u32 gpuaddr, u32 size */
63 RD_CONTEXT, /* raw dump */
64 RD_CMDSTREAM, /* raw dump */
65 RD_CMDSTREAM_ADDR, /* gpu addr of cmdstream */
66 RD_PARAM, /* u32 param_type, u32 param_val, u32 bitlen */
67 RD_FLUSH, /* empty, clear previous params */
68 RD_PROGRAM, /* shader program, raw dump */
69 RD_VERT_SHADER,
70 RD_FRAG_SHADER,
71 RD_BUFFER_CONTENTS,
72 RD_GPU_ID,
73};
74
75#define BUF_SZ 512 /* should be power of 2 */
76
77/* space used: */
78#define circ_count(circ) \
79 (CIRC_CNT((circ)->head, (circ)->tail, BUF_SZ))
80#define circ_count_to_end(circ) \
81 (CIRC_CNT_TO_END((circ)->head, (circ)->tail, BUF_SZ))
82/* space available: */
83#define circ_space(circ) \
84 (CIRC_SPACE((circ)->head, (circ)->tail, BUF_SZ))
85#define circ_space_to_end(circ) \
86 (CIRC_SPACE_TO_END((circ)->head, (circ)->tail, BUF_SZ))
87
88struct msm_rd_state {
89 struct drm_device *dev;
90
91 bool open;
92
Rob Clarka7d3c952014-05-30 14:47:38 -040093 /* current submit to read out: */
94 struct msm_gem_submit *submit;
95
96 /* fifo access is synchronized on the producer side by
97 * struct_mutex held by submit code (otherwise we could
98 * end up w/ cmds logged in different order than they
99 * were executed). And read_lock synchronizes the reads
100 */
101 struct mutex read_lock;
102
103 wait_queue_head_t fifo_event;
104 struct circ_buf fifo;
105
106 char buf[BUF_SZ];
107};
108
109static void rd_write(struct msm_rd_state *rd, const void *buf, int sz)
110{
111 struct circ_buf *fifo = &rd->fifo;
112 const char *ptr = buf;
113
114 while (sz > 0) {
115 char *fptr = &fifo->buf[fifo->head];
116 int n;
117
118 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0);
119
120 n = min(sz, circ_space_to_end(&rd->fifo));
121 memcpy(fptr, ptr, n);
122
123 fifo->head = (fifo->head + n) & (BUF_SZ - 1);
124 sz -= n;
125 ptr += n;
126
127 wake_up_all(&rd->fifo_event);
128 }
129}
130
131static void rd_write_section(struct msm_rd_state *rd,
132 enum rd_sect_type type, const void *buf, int sz)
133{
134 rd_write(rd, &type, 4);
135 rd_write(rd, &sz, 4);
136 rd_write(rd, buf, sz);
137}
138
139static ssize_t rd_read(struct file *file, char __user *buf,
140 size_t sz, loff_t *ppos)
141{
142 struct msm_rd_state *rd = file->private_data;
143 struct circ_buf *fifo = &rd->fifo;
144 const char *fptr = &fifo->buf[fifo->tail];
145 int n = 0, ret = 0;
146
147 mutex_lock(&rd->read_lock);
148
149 ret = wait_event_interruptible(rd->fifo_event,
150 circ_count(&rd->fifo) > 0);
151 if (ret)
152 goto out;
153
154 n = min_t(int, sz, circ_count_to_end(&rd->fifo));
Dan Carpenter5745d212016-07-13 13:35:29 +0300155 if (copy_to_user(buf, fptr, n)) {
156 ret = -EFAULT;
Rob Clarka7d3c952014-05-30 14:47:38 -0400157 goto out;
Dan Carpenter5745d212016-07-13 13:35:29 +0300158 }
Rob Clarka7d3c952014-05-30 14:47:38 -0400159
160 fifo->tail = (fifo->tail + n) & (BUF_SZ - 1);
161 *ppos += n;
162
163 wake_up_all(&rd->fifo_event);
164
165out:
166 mutex_unlock(&rd->read_lock);
167 if (ret)
168 return ret;
169 return n;
170}
171
172static int rd_open(struct inode *inode, struct file *file)
173{
174 struct msm_rd_state *rd = inode->i_private;
175 struct drm_device *dev = rd->dev;
176 struct msm_drm_private *priv = dev->dev_private;
177 struct msm_gpu *gpu = priv->gpu;
178 uint64_t val;
179 uint32_t gpu_id;
180 int ret = 0;
181
182 mutex_lock(&dev->struct_mutex);
183
184 if (rd->open || !gpu) {
185 ret = -EBUSY;
186 goto out;
187 }
188
189 file->private_data = rd;
190 rd->open = true;
191
192 /* the parsing tools need to know gpu-id to know which
193 * register database to load.
194 */
195 gpu->funcs->get_param(gpu, MSM_PARAM_GPU_ID, &val);
196 gpu_id = val;
197
198 rd_write_section(rd, RD_GPU_ID, &gpu_id, sizeof(gpu_id));
199
200out:
201 mutex_unlock(&dev->struct_mutex);
202 return ret;
203}
204
205static int rd_release(struct inode *inode, struct file *file)
206{
207 struct msm_rd_state *rd = inode->i_private;
208 rd->open = false;
209 return 0;
210}
211
212
213static const struct file_operations rd_debugfs_fops = {
214 .owner = THIS_MODULE,
215 .open = rd_open,
216 .read = rd_read,
217 .llseek = no_llseek,
218 .release = rd_release,
219};
220
Rob Clark2165e2b2017-09-15 09:04:52 -0400221
222static void rd_cleanup(struct msm_rd_state *rd)
Rob Clarka7d3c952014-05-30 14:47:38 -0400223{
Rob Clark2165e2b2017-09-15 09:04:52 -0400224 if (!rd)
225 return;
226
227 mutex_destroy(&rd->read_lock);
228 kfree(rd);
229}
230
231static struct msm_rd_state *rd_init(struct drm_minor *minor, const char *name)
232{
Rob Clarka7d3c952014-05-30 14:47:38 -0400233 struct msm_rd_state *rd;
Noralf Trønnes81895b52017-01-26 23:56:11 +0100234 struct dentry *ent;
Rob Clark2165e2b2017-09-15 09:04:52 -0400235 int ret = 0;
Rob Clarka7d3c952014-05-30 14:47:38 -0400236
237 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
238 if (!rd)
Rob Clark2165e2b2017-09-15 09:04:52 -0400239 return ERR_PTR(-ENOMEM);
Rob Clarka7d3c952014-05-30 14:47:38 -0400240
241 rd->dev = minor->dev;
242 rd->fifo.buf = rd->buf;
243
244 mutex_init(&rd->read_lock);
Rob Clarka7d3c952014-05-30 14:47:38 -0400245
246 init_waitqueue_head(&rd->fifo_event);
247
Rob Clark2165e2b2017-09-15 09:04:52 -0400248 ent = debugfs_create_file(name, S_IFREG | S_IRUGO,
Rob Clarka7d3c952014-05-30 14:47:38 -0400249 minor->debugfs_root, rd, &rd_debugfs_fops);
Noralf Trønnes81895b52017-01-26 23:56:11 +0100250 if (!ent) {
Rob Clark2165e2b2017-09-15 09:04:52 -0400251 DRM_ERROR("Cannot create /sys/kernel/debug/dri/%pd/%s\n",
252 minor->debugfs_root, name);
253 ret = -ENOMEM;
Rob Clarka7d3c952014-05-30 14:47:38 -0400254 goto fail;
255 }
256
Rob Clark2165e2b2017-09-15 09:04:52 -0400257 return rd;
258
259fail:
260 rd_cleanup(rd);
261 return ERR_PTR(ret);
262}
263
264int msm_rd_debugfs_init(struct drm_minor *minor)
265{
266 struct msm_drm_private *priv = minor->dev->dev_private;
267 struct msm_rd_state *rd;
268 int ret;
269
270 /* only create on first minor: */
271 if (priv->rd)
272 return 0;
273
274 rd = rd_init(minor, "rd");
275 if (IS_ERR(rd)) {
276 ret = PTR_ERR(rd);
277 goto fail;
278 }
279
280 priv->rd = rd;
281
282 rd = rd_init(minor, "hangrd");
283 if (IS_ERR(rd)) {
284 ret = PTR_ERR(rd);
285 goto fail;
286 }
287
288 priv->hangrd = rd;
289
Rob Clarka7d3c952014-05-30 14:47:38 -0400290 return 0;
291
292fail:
Noralf Trønnes85eac472017-03-07 21:49:22 +0100293 msm_rd_debugfs_cleanup(priv);
Rob Clark2165e2b2017-09-15 09:04:52 -0400294 return ret;
Rob Clarka7d3c952014-05-30 14:47:38 -0400295}
296
Noralf Trønnes85eac472017-03-07 21:49:22 +0100297void msm_rd_debugfs_cleanup(struct msm_drm_private *priv)
Rob Clarka7d3c952014-05-30 14:47:38 -0400298{
Rob Clark2165e2b2017-09-15 09:04:52 -0400299 rd_cleanup(priv->rd);
Rob Clarka7d3c952014-05-30 14:47:38 -0400300 priv->rd = NULL;
Rob Clark2165e2b2017-09-15 09:04:52 -0400301
302 rd_cleanup(priv->hangrd);
303 priv->hangrd = NULL;
Rob Clarka7d3c952014-05-30 14:47:38 -0400304}
305
Rob Clark6507e792016-06-16 11:49:09 -0400306static void snapshot_buf(struct msm_rd_state *rd,
307 struct msm_gem_submit *submit, int idx,
Rob Clarkd0651fe2016-11-11 11:08:45 -0500308 uint64_t iova, uint32_t size)
Rob Clark6507e792016-06-16 11:49:09 -0400309{
310 struct msm_gem_object *obj = submit->bos[idx].obj;
311 const char *buf;
312
Rob Clark79c21182016-06-16 11:54:41 -0400313 if (iova) {
314 buf += iova - submit->bos[idx].iova;
315 } else {
316 iova = submit->bos[idx].iova;
317 size = obj->base.size;
318 }
Rob Clark6507e792016-06-16 11:49:09 -0400319
Jordan Crouse78b8e5b2017-10-20 11:07:03 -0600320 /*
321 * Always write the GPUADDR header so can get a complete list of all the
322 * buffers in the cmd
323 */
Rob Clark6507e792016-06-16 11:49:09 -0400324 rd_write_section(rd, RD_GPUADDR,
Rob Clarkd0651fe2016-11-11 11:08:45 -0500325 (uint32_t[3]){ iova, size, iova >> 32 }, 12);
Jordan Crouse78b8e5b2017-10-20 11:07:03 -0600326
327 /* But only dump the contents of buffers marked READ */
328 if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ))
329 return;
330
Rob Clarkfad33f42017-09-15 08:38:20 -0400331 buf = msm_gem_get_vaddr_active(&obj->base);
Jordan Crouse78b8e5b2017-10-20 11:07:03 -0600332 if (IS_ERR(buf))
333 return;
334
Rob Clark6507e792016-06-16 11:49:09 -0400335 rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
336
Sushmita Susheelendra0e082702017-06-13 16:52:54 -0600337 msm_gem_put_vaddr(&obj->base);
Rob Clark6507e792016-06-16 11:49:09 -0400338}
339
Rob Clarka7d3c952014-05-30 14:47:38 -0400340/* called under struct_mutex */
Rob Clark2165e2b2017-09-15 09:04:52 -0400341void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit)
Rob Clarka7d3c952014-05-30 14:47:38 -0400342{
343 struct drm_device *dev = submit->dev;
Rob Clark2165e2b2017-09-15 09:04:52 -0400344 struct task_struct *task;
Rob Clarka7d3c952014-05-30 14:47:38 -0400345 char msg[128];
346 int i, n;
347
348 if (!rd->open)
349 return;
350
351 /* writing into fifo is serialized by caller, and
352 * rd->read_lock is used to serialize the reads
353 */
354 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
355
Rob Clark2165e2b2017-09-15 09:04:52 -0400356 rcu_read_lock();
357 task = pid_task(submit->pid, PIDTYPE_PID);
358 if (task) {
359 n = snprintf(msg, sizeof(msg), "%.*s/%d: fence=%u",
360 TASK_COMM_LEN, task->comm,
361 pid_nr(submit->pid), submit->seqno);
362 } else {
363 n = snprintf(msg, sizeof(msg), "???/%d: fence=%u",
364 pid_nr(submit->pid), submit->seqno);
365 }
366 rcu_read_unlock();
Rob Clarka7d3c952014-05-30 14:47:38 -0400367
368 rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4));
369
Jordan Crouse78b8e5b2017-10-20 11:07:03 -0600370 for (i = 0; rd_full && i < submit->nr_bos; i++)
371 snapshot_buf(rd, submit, i, 0, 0);
Rob Clarka7d3c952014-05-30 14:47:38 -0400372
373 for (i = 0; i < submit->nr_cmds; i++) {
Jordan Crouse22dd5c12017-03-07 09:50:30 -0700374 uint64_t iova = submit->cmd[i].iova;
Rob Clarka7d3c952014-05-30 14:47:38 -0400375 uint32_t szd = submit->cmd[i].size; /* in dwords */
Rob Clarka7d3c952014-05-30 14:47:38 -0400376
Rob Clark79c21182016-06-16 11:54:41 -0400377 /* snapshot cmdstream bo's (if we haven't already): */
378 if (!rd_full) {
379 snapshot_buf(rd, submit, submit->cmd[i].idx,
380 submit->cmd[i].iova, szd * 4);
381 }
Rob Clarka7d3c952014-05-30 14:47:38 -0400382
383 switch (submit->cmd[i].type) {
384 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
385 /* ignore IB-targets, we've logged the buffer, the
386 * parser tool will follow the IB based on the logged
387 * buffer/gpuaddr, so nothing more to do.
388 */
389 break;
390 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
391 case MSM_SUBMIT_CMD_BUF:
392 rd_write_section(rd, RD_CMDSTREAM_ADDR,
Jordan Crouse22dd5c12017-03-07 09:50:30 -0700393 (uint32_t[3]){ iova, szd, iova >> 32 }, 12);
Rob Clarka7d3c952014-05-30 14:47:38 -0400394 break;
395 }
Rob Clarka7d3c952014-05-30 14:47:38 -0400396 }
397}
398#endif