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Colin Crossce1e3262010-05-24 17:07:46 -07001/*
Colin Crossce1e3262010-05-24 17:07:46 -07002 * Copyright (c) 2010 Google, Inc
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _MACH_TEGRA_POWERGATE_H_
19#define _MACH_TEGRA_POWERGATE_H_
20
Stephen Warrena25186e2012-10-04 13:50:56 -060021struct clk;
Stephen Warren80b28792013-11-06 15:45:46 -070022struct reset_control;
Stephen Warrena25186e2012-10-04 13:50:56 -060023
Colin Crossce1e3262010-05-24 17:07:46 -070024#define TEGRA_POWERGATE_CPU 0
25#define TEGRA_POWERGATE_3D 1
26#define TEGRA_POWERGATE_VENC 2
27#define TEGRA_POWERGATE_PCIE 3
28#define TEGRA_POWERGATE_VDEC 4
29#define TEGRA_POWERGATE_L2 5
30#define TEGRA_POWERGATE_MPE 6
Peter De Schrijver6cafa972012-02-10 01:47:48 +020031#define TEGRA_POWERGATE_HEG 7
32#define TEGRA_POWERGATE_SATA 8
33#define TEGRA_POWERGATE_CPU1 9
34#define TEGRA_POWERGATE_CPU2 10
35#define TEGRA_POWERGATE_CPU3 11
36#define TEGRA_POWERGATE_CELP 12
37#define TEGRA_POWERGATE_3D1 13
Thierry Redingbd6a9dd2013-10-16 19:19:02 +020038#define TEGRA_POWERGATE_CPU0 14
39#define TEGRA_POWERGATE_C0NC 15
40#define TEGRA_POWERGATE_C1NC 16
Thierry Reding9a7165792013-12-13 17:31:03 +010041#define TEGRA_POWERGATE_SOR 17
Thierry Redingbd6a9dd2013-10-16 19:19:02 +020042#define TEGRA_POWERGATE_DIS 18
43#define TEGRA_POWERGATE_DISB 19
44#define TEGRA_POWERGATE_XUSBA 20
45#define TEGRA_POWERGATE_XUSBB 21
46#define TEGRA_POWERGATE_XUSBC 22
Thierry Reding9a7165792013-12-13 17:31:03 +010047#define TEGRA_POWERGATE_VIC 23
48#define TEGRA_POWERGATE_IRAM 24
Peter De Schrijver6cafa972012-02-10 01:47:48 +020049
Peter De Schrijver6cafa972012-02-10 01:47:48 +020050#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
Colin Crossce1e3262010-05-24 17:07:46 -070051
Thierry Reding9886e1f2013-11-25 11:49:47 -070052#ifdef CONFIG_ARCH_TEGRA
Peter De Schrijver6ac8cb52012-02-10 01:47:47 +020053int tegra_powergate_is_powered(int id);
Colin Crossce1e3262010-05-24 17:07:46 -070054int tegra_powergate_power_on(int id);
55int tegra_powergate_power_off(int id);
Colin Crossce1e3262010-05-24 17:07:46 -070056int tegra_powergate_remove_clamping(int id);
57
58/* Must be called with clk disabled, and returns with clk enabled */
Stephen Warren80b28792013-11-06 15:45:46 -070059int tegra_powergate_sequence_power_up(int id, struct clk *clk,
60 struct reset_control *rst);
Thierry Reding9886e1f2013-11-25 11:49:47 -070061#else
62static inline int tegra_powergate_is_powered(int id)
63{
64 return -ENOSYS;
65}
66
67static inline int tegra_powergate_power_on(int id)
68{
69 return -ENOSYS;
70}
71
72static inline int tegra_powergate_power_off(int id)
73{
74 return -ENOSYS;
75}
76
77static inline int tegra_powergate_remove_clamping(int id)
78{
79 return -ENOSYS;
80}
81
Stephen Warren80b28792013-11-06 15:45:46 -070082static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
83 struct reset_control *rst);
Thierry Reding9886e1f2013-11-25 11:49:47 -070084{
85 return -ENOSYS;
86}
87#endif
Colin Crossce1e3262010-05-24 17:07:46 -070088
89#endif /* _MACH_TEGRA_POWERGATE_H_ */