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gerrit-public.fairphone.software / kernel / msm-5.4 / c8a16c68ef4eb7817e41759c7105678ebc155377 / . / drivers / net / wireless / ath / carl9170 / wlan.h
blob: 48ead2268f505308eb623f081eeb2c320ae04a48 [file] [log] [blame]
Christian Lamparteraae9af62010-09-06 01:06:57 +0200[diff] [blame]1/*
2 * Shared Atheros AR9170 Header
3 *
4 * RX/TX meta descriptor format
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38
39#ifndef __CARL9170_SHARED_WLAN_H
40#define __CARL9170_SHARED_WLAN_H
41
42#include "fwcmd.h"
43
44#define AR9170_RX_PHY_RATE_CCK_1M 0x0a
45#define AR9170_RX_PHY_RATE_CCK_2M 0x14
46#define AR9170_RX_PHY_RATE_CCK_5M 0x37
47#define AR9170_RX_PHY_RATE_CCK_11M 0x6e
48
49#define AR9170_ENC_ALG_NONE 0x0
50#define AR9170_ENC_ALG_WEP64 0x1
51#define AR9170_ENC_ALG_TKIP 0x2
52#define AR9170_ENC_ALG_AESCCMP 0x4
53#define AR9170_ENC_ALG_WEP128 0x5
54#define AR9170_ENC_ALG_WEP256 0x6
55#define AR9170_ENC_ALG_CENC 0x7
56
57#define AR9170_RX_ENC_SOFTWARE 0x8
58
59#define AR9170_RX_STATUS_MODULATION 0x03
60#define AR9170_RX_STATUS_MODULATION_S 0
61#define AR9170_RX_STATUS_MODULATION_CCK 0x00
62#define AR9170_RX_STATUS_MODULATION_OFDM 0x01
63#define AR9170_RX_STATUS_MODULATION_HT 0x02
64#define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
65
66/* depends on modulation */
67#define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
68#define AR9170_RX_STATUS_GREENFIELD 0x08
69
70#define AR9170_RX_STATUS_MPDU 0x30
71#define AR9170_RX_STATUS_MPDU_S 4
72#define AR9170_RX_STATUS_MPDU_SINGLE 0x00
73#define AR9170_RX_STATUS_MPDU_FIRST 0x20
74#define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
75#define AR9170_RX_STATUS_MPDU_LAST 0x10
76
77#define AR9170_RX_ERROR_RXTO 0x01
78#define AR9170_RX_ERROR_OVERRUN 0x02
79#define AR9170_RX_ERROR_DECRYPT 0x04
80#define AR9170_RX_ERROR_FCS 0x08
81#define AR9170_RX_ERROR_WRONG_RA 0x10
82#define AR9170_RX_ERROR_PLCP 0x20
83#define AR9170_RX_ERROR_MMIC 0x40
84#define AR9170_RX_ERROR_FATAL 0x80
85
86/* these are either-or */
87#define AR9170_TX_MAC_PROT_RTS 0x0001
88#define AR9170_TX_MAC_PROT_CTS 0x0002
89#define AR9170_TX_MAC_PROT 0x0003
90
91#define AR9170_TX_MAC_NO_ACK 0x0004
92/* if unset, MAC will only do SIFS space before frame */
93#define AR9170_TX_MAC_BACKOFF 0x0008
94#define AR9170_TX_MAC_BURST 0x0010
95#define AR9170_TX_MAC_AGGR 0x0020
96
97/* encryption is a two-bit field */
98#define AR9170_TX_MAC_ENCR_NONE 0x0000
99#define AR9170_TX_MAC_ENCR_RC4 0x0040
100#define AR9170_TX_MAC_ENCR_CENC 0x0080
101#define AR9170_TX_MAC_ENCR_AES 0x00c0
102
103#define AR9170_TX_MAC_MMIC 0x0100
104#define AR9170_TX_MAC_HW_DURATION 0x0200
105#define AR9170_TX_MAC_QOS_S 10
106#define AR9170_TX_MAC_QOS 0x0c00
107#define AR9170_TX_MAC_DISABLE_TXOP 0x1000
108#define AR9170_TX_MAC_TXOP_RIFS 0x2000
109#define AR9170_TX_MAC_IMM_BA 0x4000
110
111/* either-or */
112#define AR9170_TX_PHY_MOD_CCK 0x00000000
113#define AR9170_TX_PHY_MOD_OFDM 0x00000001
114#define AR9170_TX_PHY_MOD_HT 0x00000002
115
116/* depends on modulation */
117#define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
118#define AR9170_TX_PHY_GREENFIELD 0x00000004
119
120#define AR9170_TX_PHY_BW_S 3
121#define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT)
122#define AR9170_TX_PHY_BW_20MHZ 0
123#define AR9170_TX_PHY_BW_40MHZ 2
124#define AR9170_TX_PHY_BW_40MHZ_DUP 3
125
126#define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6
127#define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \
128 AR9170_TX_PHY_TX_HEAVY_CLIP_S)
129
130#define AR9170_TX_PHY_TX_PWR_S 9
131#define AR9170_TX_PHY_TX_PWR (0x3f << \
132 AR9170_TX_PHY_TX_PWR_S)
133
134#define AR9170_TX_PHY_TXCHAIN_S 15
135#define AR9170_TX_PHY_TXCHAIN (7 << \
136 AR9170_TX_PHY_TXCHAIN_S)
137#define AR9170_TX_PHY_TXCHAIN_1 1
138/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
139#define AR9170_TX_PHY_TXCHAIN_2 5
140
141#define AR9170_TX_PHY_MCS_S 18
142#define AR9170_TX_PHY_MCS (0x7f << \
143 AR9170_TX_PHY_MCS_S)
144
145#define AR9170_TX_PHY_RATE_CCK_1M 0x0
146#define AR9170_TX_PHY_RATE_CCK_2M 0x1
147#define AR9170_TX_PHY_RATE_CCK_5M 0x2
148#define AR9170_TX_PHY_RATE_CCK_11M 0x3
149
150/* same as AR9170_RX_PHY_RATE */
151#define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb
152#define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf
153#define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
154#define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe
155#define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9
156#define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd
157#define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8
158#define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc
159
160#define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0
161#define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1
162#define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2
163#define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3
164#define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4
165#define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5
166#define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6
167#define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7
168#define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8
169#define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9
170#define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
171#define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb
172#define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc
173#define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd
174#define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe
175#define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf
176
177#define AR9170_TX_PHY_SHORT_GI 0x80000000
178
179#ifdef __CARL9170FW__
180struct ar9170_tx_hw_mac_control {
181 union {
182 struct {
183 /*
184 * Beware of compiler bugs in all gcc pre 4.4!
185 */
186
187 u8 erp_prot:2;
188 u8 no_ack:1;
189 u8 backoff:1;
190 u8 burst:1;
191 u8 ampdu:1;
192
193 u8 enc_mode:2;
194
195 u8 hw_mmic:1;
196 u8 hw_duration:1;
197
198 u8 qos_queue:2;
199
200 u8 disable_txop:1;
201 u8 txop_rifs:1;
202
203 u8 ba_end:1;
204 u8 probe:1;
205 } __packed;
206
207 __le16 set;
208 } __packed;
209} __packed;
210
211struct ar9170_tx_hw_phy_control {
212 union {
213 struct {
214 /*
215 * Beware of compiler bugs in all gcc pre 4.4!
216 */
217
218 u8 modulation:2;
219 u8 preamble:1;
220 u8 bandwidth:2;
221 u8:1;
222 u8 heavy_clip:3;
223 u8 tx_power:6;
224 u8 chains:3;
225 u8 mcs:7;
226 u8:6;
227 u8 short_gi:1;
228 } __packed;
229
230 __le32 set;
231 } __packed;
232} __packed;
233
234struct ar9170_tx_rate_info {
235 u8 tries:3;
236 u8 erp_prot:2;
237 u8 ampdu:1;
238 u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
239} __packed;
240
241struct carl9170_tx_superdesc {
242 __le16 len;
243 u8 rix;
244 u8 cnt;
245 u8 cookie;
246 u8 ampdu_density:3;
247 u8 ampdu_factor:2;
248 u8 ampdu_commit_density:1;
249 u8 ampdu_commit_factor:1;
250 u8 ampdu_unused_bit:1;
251 u8 queue:2;
252 u8 reserved:1;
253 u8 vif_id:3;
254 u8 fill_in_tsf:1;
255 u8 cab:1;
256 u8 padding2;
257 struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES];
258 struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
259} __packed;
260
261struct ar9170_tx_hwdesc {
262 __le16 length;
263 struct ar9170_tx_hw_mac_control mac;
264 struct ar9170_tx_hw_phy_control phy;
265} __packed;
266
267struct ar9170_tx_frame {
268 struct ar9170_tx_hwdesc hdr;
269
270 union {
271 struct ieee80211_hdr i3e;
272 u8 payload[0];
273 } data;
274} __packed;
275
276struct carl9170_tx_superframe {
277 struct carl9170_tx_superdesc s;
278 struct ar9170_tx_frame f;
279} __packed;
280
281#endif /* __CARL9170FW__ */
282
283struct _ar9170_tx_hwdesc {
284 __le16 length;
285 __le16 mac_control;
286 __le32 phy_control;
287} __packed;
288
289#define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0
290#define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7
291#define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18
292#define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3
293#define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20
294#define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5
295#define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40
296#define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6
297
298#define CARL9170_TX_SUPER_MISC_QUEUE 0x3
299#define CARL9170_TX_SUPER_MISC_QUEUE_S 0
300#define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
301#define CARL9170_TX_SUPER_MISC_VIF_ID_S 3
302#define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
303#define CARL9170_TX_SUPER_MISC_CAB 0x80
304
305#define CARL9170_TX_SUPER_RI_TRIES 0x7
306#define CARL9170_TX_SUPER_RI_TRIES_S 0
307#define CARL9170_TX_SUPER_RI_ERP_PROT 0x18
308#define CARL9170_TX_SUPER_RI_ERP_PROT_S 3
309#define CARL9170_TX_SUPER_RI_AMPDU 0x20
310#define CARL9170_TX_SUPER_RI_AMPDU_S 5
311
312struct _carl9170_tx_superdesc {
313 __le16 len;
314 u8 rix;
315 u8 cnt;
316 u8 cookie;
317 u8 ampdu_settings;
318 u8 misc;
319 u8 padding;
320 u8 ri[CARL9170_TX_MAX_RATES];
321 __le32 rr[CARL9170_TX_MAX_RETRY_RATES];
322} __packed;
323
324struct _carl9170_tx_superframe {
325 struct _carl9170_tx_superdesc s;
326 struct _ar9170_tx_hwdesc f;
327 u8 frame_data[0];
328} __packed;
329
330#define CARL9170_TX_SUPERDESC_LEN 24
331#define AR9170_TX_HWDESC_LEN 8
332#define AR9170_TX_SUPERFRAME_LEN (CARL9170_TX_HWDESC_LEN + \
333 AR9170_TX_SUPERDESC_LEN)
334
335struct ar9170_rx_head {
336 u8 plcp[12];
337} __packed;
338
339struct ar9170_rx_phystatus {
340 union {
341 struct {
342 u8 rssi_ant0, rssi_ant1, rssi_ant2,
343 rssi_ant0x, rssi_ant1x, rssi_ant2x,
344 rssi_combined;
345 } __packed;
346 u8 rssi[7];
347 } __packed;
348
349 u8 evm_stream0[6], evm_stream1[6];
350 u8 phy_err;
351} __packed;
352
353struct ar9170_rx_macstatus {
354 u8 SAidx, DAidx;
355 u8 error;
356 u8 status;
357} __packed;
358
359struct ar9170_rx_frame_single {
360 struct ar9170_rx_head phy_head;
361 struct ieee80211_hdr i3e;
362 struct ar9170_rx_phystatus phy_tail;
363 struct ar9170_rx_macstatus macstatus;
364} __packed;
365
366struct ar9170_rx_frame_head {
367 struct ar9170_rx_head phy_head;
368 struct ieee80211_hdr i3e;
369 struct ar9170_rx_macstatus macstatus;
370} __packed;
371
372struct ar9170_rx_frame_middle {
373 struct ieee80211_hdr i3e;
374 struct ar9170_rx_macstatus macstatus;
375} __packed;
376
377struct ar9170_rx_frame_tail {
378 struct ieee80211_hdr i3e;
379 struct ar9170_rx_phystatus phy_tail;
380 struct ar9170_rx_macstatus macstatus;
381} __packed;
382
383struct ar9170_rx_frame {
384 union {
385 struct ar9170_rx_frame_single single;
386 struct ar9170_rx_frame_head head;
387 struct ar9170_rx_frame_middle middle;
388 struct ar9170_rx_frame_tail tail;
389 } __packed;
390} __packed;
391
392static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
393{
394 return (t->SAidx & 0xc0) >> 4 |
395 (t->DAidx & 0xc0) >> 6;
396}
397
398enum ar9170_txq {
399 AR9170_TXQ_BE,
400
401 AR9170_TXQ_VI,
402 AR9170_TXQ_VO,
403 AR9170_TXQ_BK,
404
405 __AR9170_NUM_TXQ,
406};
407
408static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };
409
410#define AR9170_TXQ_DEPTH 32
411
412#endif /* __CARL9170_SHARED_WLAN_H */