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gerrit-public.fairphone.software / kernel / msm-5.4 / f1550a1ce79f1424beca55e78122e594f5ef9094 / . / arch / arm / boot / dts / imx53.dtsi
blob: a9a3adde4e5af1ba1ef1526fe166812b2d7f2e98 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]29 };
30
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
36 };
37
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ckil {
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
45 };
46
47 ckih1 {
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
50 };
51
52 ckih2 {
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
55 };
56
57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
68 ranges;
69
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]70 ipu: ipu@18000000 {
71 #crtc-cells = <1>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
74 interrupts = <11 10>;
75 };
76
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]77 aips@50000000 { /* AIPS1 */
78 compatible = "fsl,aips-bus", "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x50000000 0x10000000>;
82 ranges;
83
84 spba@50000000 {
85 compatible = "fsl,spba-bus", "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x50000000 0x40000>;
89 ranges;
90
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]91 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>;
94 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]97 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]98 status = "disabled";
99 };
100
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]101 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]102 compatible = "fsl,imx53-esdhc";
103 reg = <0x50008000 0x4000>;
104 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]105 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
106 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]107 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]108 status = "disabled";
109 };
110
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]111 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]112 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
113 reg = <0x5000c000 0x4000>;
114 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]115 clocks = <&clks 32>, <&clks 33>;
116 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]117 status = "disabled";
118 };
119
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]120 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
124 reg = <0x50010000 0x4000>;
125 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]126 clocks = <&clks 51>, <&clks 52>;
127 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]128 status = "disabled";
129 };
130
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]131 ssi2: ssi@50014000 {
132 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
133 reg = <0x50014000 0x4000>;
134 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]135 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]136 fsl,fifo-depth = <15>;
137 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
138 status = "disabled";
139 };
140
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]141 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]142 compatible = "fsl,imx53-esdhc";
143 reg = <0x50020000 0x4000>;
144 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]145 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
146 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]147 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]148 status = "disabled";
149 };
150
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]151 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]152 compatible = "fsl,imx53-esdhc";
153 reg = <0x50024000 0x4000>;
154 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]155 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
156 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]157 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]158 status = "disabled";
159 };
160 };
161
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]162 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]163 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
164 reg = <0x53f80000 0x0200>;
165 interrupts = <18>;
166 status = "disabled";
167 };
168
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]169 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]170 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
171 reg = <0x53f80200 0x0200>;
172 interrupts = <14>;
173 status = "disabled";
174 };
175
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]176 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]177 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
178 reg = <0x53f80400 0x0200>;
179 interrupts = <16>;
180 status = "disabled";
181 };
182
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]183 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
185 reg = <0x53f80600 0x0200>;
186 interrupts = <17>;
187 status = "disabled";
188 };
189
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]190 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]191 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]192 reg = <0x53f84000 0x4000>;
193 interrupts = <50 51>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]197 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]198 };
199
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]200 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]201 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]202 reg = <0x53f88000 0x4000>;
203 interrupts = <52 53>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]207 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]208 };
209
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]210 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]211 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]212 reg = <0x53f8c000 0x4000>;
213 interrupts = <54 55>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]217 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]218 };
219
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]220 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]221 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]222 reg = <0x53f90000 0x4000>;
223 interrupts = <56 57>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]227 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]228 };
229
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]230 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]231 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
232 reg = <0x53f98000 0x4000>;
233 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]234 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]235 };
236
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]237 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]238 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
239 reg = <0x53f9c000 0x4000>;
240 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]241 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]242 status = "disabled";
243 };
244
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]245 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]246 compatible = "fsl,imx53-iomuxc";
247 reg = <0x53fa8000 0x4000>;
248
249 audmux {
250 pinctrl_audmux_1: audmuxgrp-1 {
251 fsl,pins = <
252 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
253 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
254 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
255 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
256 >;
257 };
258 };
259
260 fec {
261 pinctrl_fec_1: fecgrp-1 {
262 fsl,pins = <
263 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
264 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
265 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
266 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
267 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
268 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
269 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
270 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
271 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
272 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
273 >;
274 };
275 };
276
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]277 csi {
278 pinctrl_csi_1: csigrp-1 {
279 fsl,pins = <
280 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
281 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
282 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
283 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
284 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
285 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
286 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
287 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
288 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
289 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
290 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
291 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
292 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
293 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
294 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
295 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
296 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
297 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
298 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
299 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
300 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
301 >;
302 };
303 };
304
305 cspi {
306 pinctrl_cspi_1: cspigrp-1 {
307 fsl,pins = <
308 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
309 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
310 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
311 >;
312 };
313 };
314
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]315 ecspi1 {
316 pinctrl_ecspi1_1: ecspi1grp-1 {
317 fsl,pins = <
318 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
319 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
320 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
321 >;
322 };
323 };
324
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]325 esdhc1 {
326 pinctrl_esdhc1_1: esdhc1grp-1 {
327 fsl,pins = <
328 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
329 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
330 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
331 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
332 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
333 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
334 >;
335 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]336
337 pinctrl_esdhc1_2: esdhc1grp-2 {
338 fsl,pins = <
339 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
340 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
341 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
342 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
343 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
344 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
345 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
346 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
347 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
348 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
349 >;
350 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]351 };
352
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]353 esdhc2 {
354 pinctrl_esdhc2_1: esdhc2grp-1 {
355 fsl,pins = <
356 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
357 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
358 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
359 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
360 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
361 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
362 >;
363 };
364 };
365
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]366 esdhc3 {
367 pinctrl_esdhc3_1: esdhc3grp-1 {
368 fsl,pins = <
369 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
370 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
371 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
372 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
373 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
374 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
375 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
376 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
377 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
378 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
379 >;
380 };
381 };
382
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]383 can1 {
384 pinctrl_can1_1: can1grp-1 {
385 fsl,pins = <
386 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
387 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
388 >;
389 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]390
391 pinctrl_can1_2: can1grp-2 {
392 fsl,pins = <
393 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
394 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
395 >;
396 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]397 };
398
399 can2 {
400 pinctrl_can2_1: can2grp-1 {
401 fsl,pins = <
402 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
403 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
404 >;
405 };
406 };
407
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]408 i2c1 {
409 pinctrl_i2c1_1: i2c1grp-1 {
410 fsl,pins = <
411 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
412 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
413 >;
414 };
415 };
416
417 i2c2 {
418 pinctrl_i2c2_1: i2c2grp-1 {
419 fsl,pins = <
420 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
421 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
422 >;
423 };
424 };
425
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]426 i2c3 {
427 pinctrl_i2c3_1: i2c3grp-1 {
428 fsl,pins = <
429 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
430 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
431 >;
432 };
433 };
434
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]435 uart1 {
436 pinctrl_uart1_1: uart1grp-1 {
437 fsl,pins = <
438 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
439 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
440 >;
441 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]442
443 pinctrl_uart1_2: uart1grp-2 {
444 fsl,pins = <
445 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
446 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
447 >;
448 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]449 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]450
451 uart2 {
452 pinctrl_uart2_1: uart2grp-1 {
453 fsl,pins = <
454 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
455 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
456 >;
457 };
458 };
459
460 uart3 {
461 pinctrl_uart3_1: uart3grp-1 {
462 fsl,pins = <
463 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
464 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
465 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
466 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
467 >;
468 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]469
470 pinctrl_uart3_2: uart3grp-2 {
471 fsl,pins = <
472 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
473 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
474 >;
475 };
476
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]477 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]478
479 uart4 {
480 pinctrl_uart4_1: uart4grp-1 {
481 fsl,pins = <
482 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
483 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
484 >;
485 };
486 };
487
488 uart5 {
489 pinctrl_uart5_1: uart5grp-1 {
490 fsl,pins = <
491 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
492 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
493 >;
494 };
495 };
496
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]497 };
498
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]499 pwm1: pwm@53fb4000 {
500 #pwm-cells = <2>;
501 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
502 reg = <0x53fb4000 0x4000>;
503 clocks = <&clks 37>, <&clks 38>;
504 clock-names = "ipg", "per";
505 interrupts = <61>;
506 };
507
508 pwm2: pwm@53fb8000 {
509 #pwm-cells = <2>;
510 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
511 reg = <0x53fb8000 0x4000>;
512 clocks = <&clks 39>, <&clks 40>;
513 clock-names = "ipg", "per";
514 interrupts = <94>;
515 };
516
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]517 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]518 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
519 reg = <0x53fbc000 0x4000>;
520 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]521 clocks = <&clks 28>, <&clks 29>;
522 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]523 status = "disabled";
524 };
525
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]526 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]527 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
528 reg = <0x53fc0000 0x4000>;
529 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]530 clocks = <&clks 30>, <&clks 31>;
531 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]532 status = "disabled";
533 };
534
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]535 can1: can@53fc8000 {
536 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
537 reg = <0x53fc8000 0x4000>;
538 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]539 clocks = <&clks 158>, <&clks 157>;
540 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]541 status = "disabled";
542 };
543
544 can2: can@53fcc000 {
545 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
546 reg = <0x53fcc000 0x4000>;
547 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]548 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]549 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]550 status = "disabled";
551 };
552
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]553 clks: ccm@53fd4000{
554 compatible = "fsl,imx53-ccm";
555 reg = <0x53fd4000 0x4000>;
556 interrupts = <0 71 0x04 0 72 0x04>;
557 #clock-cells = <1>;
558 };
559
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]560 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]561 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]562 reg = <0x53fdc000 0x4000>;
563 interrupts = <103 104>;
564 gpio-controller;
565 #gpio-cells = <2>;
566 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]567 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]568 };
569
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]570 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]571 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]572 reg = <0x53fe0000 0x4000>;
573 interrupts = <105 106>;
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]577 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]578 };
579
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]580 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]581 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]582 reg = <0x53fe4000 0x4000>;
583 interrupts = <107 108>;
584 gpio-controller;
585 #gpio-cells = <2>;
586 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]587 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]588 };
589
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]590 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]591 #address-cells = <1>;
592 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]593 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]594 reg = <0x53fec000 0x4000>;
595 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]596 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]597 status = "disabled";
598 };
599
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]600 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]601 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
602 reg = <0x53ff0000 0x4000>;
603 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]604 clocks = <&clks 65>, <&clks 66>;
605 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]606 status = "disabled";
607 };
608 };
609
610 aips@60000000 { /* AIPS2 */
611 compatible = "fsl,aips-bus", "simple-bus";
612 #address-cells = <1>;
613 #size-cells = <1>;
614 reg = <0x60000000 0x10000000>;
615 ranges;
616
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]617 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]618 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
619 reg = <0x63f90000 0x4000>;
620 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]621 clocks = <&clks 67>, <&clks 68>;
622 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]623 status = "disabled";
624 };
625
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]626 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]627 #address-cells = <1>;
628 #size-cells = <0>;
629 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
630 reg = <0x63fac000 0x4000>;
631 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]632 clocks = <&clks 53>, <&clks 54>;
633 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]634 status = "disabled";
635 };
636
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]637 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]638 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
639 reg = <0x63fb0000 0x4000>;
640 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]641 clocks = <&clks 56>, <&clks 56>;
642 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]643 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]644 };
645
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]646 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]647 #address-cells = <1>;
648 #size-cells = <0>;
649 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
650 reg = <0x63fc0000 0x4000>;
651 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]652 clocks = <&clks 55>, <&clks 0>;
653 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]654 status = "disabled";
655 };
656
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]657 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]658 #address-cells = <1>;
659 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]660 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]661 reg = <0x63fc4000 0x4000>;
662 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]663 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]664 status = "disabled";
665 };
666
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]667 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]668 #address-cells = <1>;
669 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]670 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]671 reg = <0x63fc8000 0x4000>;
672 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]673 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]674 status = "disabled";
675 };
676
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]677 ssi1: ssi@63fcc000 {
678 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
679 reg = <0x63fcc000 0x4000>;
680 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]681 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]682 fsl,fifo-depth = <15>;
683 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
684 status = "disabled";
685 };
686
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]687 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]688 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
689 reg = <0x63fd0000 0x4000>;
690 status = "disabled";
691 };
692
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]693 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]694 compatible = "fsl,imx53-nand";
695 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
696 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]697 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]698 status = "disabled";
699 };
700
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]701 ssi3: ssi@63fe8000 {
702 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
703 reg = <0x63fe8000 0x4000>;
704 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]705 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]706 fsl,fifo-depth = <15>;
707 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
708 status = "disabled";
709 };
710
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]711 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]712 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
713 reg = <0x63fec000 0x4000>;
714 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]715 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
716 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]717 status = "disabled";
718 };
719 };
720 };
721};