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Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*
2 * PHY functions
3 *
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03004 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
Nick Kossifidis33a31822009-02-09 06:00:34 +02005 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03006 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02007 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
Jiri Slabyfa1c1142007-08-12 17:33:16 +02008 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020025
26#include "ath5k.h"
27#include "reg.h"
28#include "base.h"
Nick Kossifidis33a31822009-02-09 06:00:34 +020029#include "rfbuffer.h"
30#include "rfgain.h"
Jiri Slabyfa1c1142007-08-12 17:33:16 +020031
Nick Kossifidis9320b5c42010-11-23 20:36:45 +020032
33/******************\
34* Helper functions *
35\******************/
36
37/*
38 * Get the PHY Chip revision
39 */
40u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
41{
42 unsigned int i;
43 u32 srev;
44 u16 ret;
45
46 /*
47 * Set the radio chip access register
48 */
49 switch (chan) {
50 case CHANNEL_2GHZ:
51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
52 break;
53 case CHANNEL_5GHZ:
54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
55 break;
56 default:
57 return 0;
58 }
59
60 mdelay(2);
61
62 /* ...wait until PHY is ready and read the selected radio revision */
63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
64
65 for (i = 0; i < 8; i++)
66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
67
68 if (ah->ah_version == AR5K_AR5210) {
69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
71 } else {
72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
74 ((srev & 0x0f) << 4), 8);
75 }
76
77 /* Reset to the 5GHz mode */
78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
79
80 return ret;
81}
82
83/*
84 * Check if a channel is supported
85 */
86bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
87{
88 /* Check if the channel is in our supported range */
89 if (flags & CHANNEL_2GHZ) {
90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
92 return true;
93 } else if (flags & CHANNEL_5GHZ)
94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
96 return true;
97
98 return false;
99}
100
101bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
102 struct ieee80211_channel *channel)
103{
104 u8 refclk_freq;
105
106 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) ||
108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
109 refclk_freq = 40;
110 else
111 refclk_freq = 32;
112
113 if ((channel->center_freq % refclk_freq != 0) &&
114 ((channel->center_freq % refclk_freq < 10) ||
115 (channel->center_freq % refclk_freq > 22)))
116 return true;
117 else
118 return false;
119}
120
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200121/*
122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
123 */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200124static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
125 const struct ath5k_rf_reg *rf_regs,
126 u32 val, u8 reg_id, bool set)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200127{
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200128 const struct ath5k_rf_reg *rfreg = NULL;
129 u8 offset, bank, num_bits, col, position;
130 u16 entry;
131 u32 mask, data, last_bit, bits_shifted, first_bit;
132 u32 *rfb;
133 s32 bits_left;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200134 int i;
135
136 data = 0;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200137 rfb = ah->ah_rf_banks;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200138
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200139 for (i = 0; i < ah->ah_rf_regs_count; i++) {
140 if (rf_regs[i].index == reg_id) {
141 rfreg = &rf_regs[i];
142 break;
143 }
144 }
145
146 if (rfb == NULL || rfreg == NULL) {
147 ATH5K_PRINTF("Rf register not found!\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200148 /* should not happen */
149 return 0;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200150 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200151
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200152 bank = rfreg->bank;
153 num_bits = rfreg->field.len;
154 first_bit = rfreg->field.pos;
155 col = rfreg->field.col;
156
157 /* first_bit is an offset from bank's
158 * start. Since we have all banks on
159 * the same array, we use this offset
160 * to mark each bank's start */
161 offset = ah->ah_offset[bank];
162
163 /* Boundary check */
164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200165 ATH5K_PRINTF("invalid values at offset %u\n", offset);
166 return 0;
167 }
168
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200169 entry = ((first_bit - 1) / 8) + offset;
170 position = (first_bit - 1) % 8;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200171
Joe Perchese9010e22008-03-07 14:21:16 -0800172 if (set)
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200173 data = ath5k_hw_bitswap(val, num_bits);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200174
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
176 position = 0, entry++) {
177
178 last_bit = (position + bits_left > 8) ? 8 :
179 position + bits_left;
180
181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
182 (col * 8);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200183
Joe Perchese9010e22008-03-07 14:21:16 -0800184 if (set) {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200185 rfb[entry] &= ~mask;
186 rfb[entry] |= ((data << position) << (col * 8)) & mask;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200187 data >>= (8 - position);
188 } else {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
190 << bits_shifted;
191 bits_shifted += last_bit - position;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200192 }
193
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200194 bits_left -= 8 - position;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200195 }
196
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200198
199 return data;
200}
201
Nick Kossifidis9320b5c42010-11-23 20:36:45 +0200202/**
203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
204 *
205 * @ah: the &struct ath5k_hw
206 * @channel: the currently set channel upon reset
207 *
208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
210 *
211 * Since delta slope is floating point we split it on its exponent and
212 * mantissa and provide these values on hw.
213 *
214 * For more infos i think this patent is related
215 * http://www.freepatentsonline.com/7184495.html
216 */
217static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
218 struct ieee80211_channel *channel)
219{
220 /* Get exponent and mantissa and set it */
221 u32 coef_scaled, coef_exp, coef_man,
222 ds_coef_exp, ds_coef_man, clock;
223
224 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
225 !(channel->hw_value & CHANNEL_OFDM));
226
227 /* Get coefficient
228 * ALGO: coef = (5 * clock / carrier_freq) / 2
229 * we scale coef by shifting clock value by 24 for
230 * better precision since we use integers */
Nick Kossifidis73a06a62010-11-23 21:48:32 +0200231 switch (ah->ah_bwmode) {
232 case AR5K_BWMODE_40MHZ:
233 clock = 40 * 2;
234 break;
235 case AR5K_BWMODE_10MHZ:
236 clock = 40 / 2;
237 break;
238 case AR5K_BWMODE_5MHZ:
239 clock = 40 / 4;
240 break;
241 default:
242 clock = 40;
243 break;
244 }
Nick Kossifidis9320b5c42010-11-23 20:36:45 +0200245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
246
247 /* Get exponent
248 * ALGO: coef_exp = 14 - highest set bit position */
249 coef_exp = ilog2(coef_scaled);
250
251 /* Doesn't make sense if it's zero*/
252 if (!coef_scaled || !coef_exp)
253 return -EINVAL;
254
255 /* Note: we've shifted coef_scaled by 24 */
256 coef_exp = 14 - (coef_exp - 24);
257
258
259 /* Get mantissa (significant digits)
260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
261 coef_man = coef_scaled +
262 (1 << (24 - coef_exp - 1));
263
264 /* Calculate delta slope coefficient exponent
265 * and mantissa (remove scaling) and set them on hw */
266 ds_coef_man = coef_man >> (24 - coef_exp);
267 ds_coef_exp = coef_exp - 16;
268
269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
273
274 return 0;
275}
276
277int ath5k_hw_phy_disable(struct ath5k_hw *ah)
278{
279 /*Just a try M.F.*/
280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
281
282 return 0;
283}
284
285
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200286/**********************\
287* RF Gain optimization *
288\**********************/
289
290/*
Bob Copelanda180a132010-08-15 13:03:12 -0400291 * This code is used to optimize RF gain on different environments
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200292 * (temperature mostly) based on feedback from a power detector.
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200293 *
294 * It's only used on RF5111 and RF5112, later RF chips seem to have
295 * auto adjustment on hw -notice they have a much smaller BANK 7 and
296 * no gain optimization ladder-.
297 *
298 * For more infos check out this patent doc
299 * http://www.freepatentsonline.com/7400691.html
300 *
301 * This paper describes power drops as seen on the receiver due to
302 * probe packets
303 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
304 * %20of%20Power%20Control.pdf
305 *
306 * And this is the MadWiFi bug entry related to the above
307 * http://madwifi-project.org/ticket/1659
308 * with various measurements and diagrams
309 *
310 * TODO: Deal with power drops due to probes by setting an apropriate
311 * tx power on the probe packets ! Make this part of the calibration process.
312 */
313
314/* Initialize ah_gain durring attach */
315int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
316{
317 /* Initialize the gain optimization values */
318 switch (ah->ah_radio) {
319 case AR5K_RF5111:
320 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
321 ah->ah_gain.g_low = 20;
322 ah->ah_gain.g_high = 35;
323 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
324 break;
325 case AR5K_RF5112:
326 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
327 ah->ah_gain.g_low = 20;
328 ah->ah_gain.g_high = 85;
329 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
330 break;
331 default:
332 return -EINVAL;
333 }
334
335 return 0;
336}
337
338/* Schedule a gain probe check on the next transmited packet.
339 * That means our next packet is going to be sent with lower
340 * tx power and a Peak to Average Power Detector (PAPD) will try
341 * to measure the gain.
342 *
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200343 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
344 * just after we enable the probe so that we don't mess with
345 * standard traffic ? Maybe it's time to use sw interrupts and
346 * a probe tasklet !!!
347 */
348static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
349{
350
351 /* Skip if gain calibration is inactive or
352 * we already handle a probe request */
353 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
354 return;
355
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200356 /* Send the packet with 2dB below max power as
357 * patent doc suggest */
Nick Kossifidisa0823812009-04-30 15:55:44 -0400358 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200359 AR5K_PHY_PAPD_PROBE_TXPOWER) |
360 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
361
362 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
363
364}
365
366/* Calculate gain_F measurement correction
367 * based on the current step for RF5112 rev. 2 */
368static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200369{
370 u32 mix, step;
371 u32 *rf;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200372 const struct ath5k_gain_opt *go;
373 const struct ath5k_gain_opt_step *g_step;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200374 const struct ath5k_rf_reg *rf_regs;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200375
376 /* Only RF5112 Rev. 2 supports it */
377 if ((ah->ah_radio != AR5K_RF5112) ||
378 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
379 return 0;
380
381 go = &rfgain_opt_5112;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200382 rf_regs = rf_regs_5112a;
383 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200384
385 g_step = &go->go_step[ah->ah_gain.g_step_idx];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200386
387 if (ah->ah_rf_banks == NULL)
388 return 0;
389
390 rf = ah->ah_rf_banks;
391 ah->ah_gain.g_f_corr = 0;
392
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200393 /* No VGA (Variable Gain Amplifier) override, skip */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200394 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200395 return 0;
396
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200397 /* Mix gain stepping */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200398 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200399
400 /* Mix gain override */
401 mix = g_step->gos_param[0];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200402
403 switch (mix) {
404 case 3:
405 ah->ah_gain.g_f_corr = step * 2;
406 break;
407 case 2:
408 ah->ah_gain.g_f_corr = (step - 5) * 2;
409 break;
410 case 1:
411 ah->ah_gain.g_f_corr = step;
412 break;
413 default:
414 ah->ah_gain.g_f_corr = 0;
415 break;
416 }
417
418 return ah->ah_gain.g_f_corr;
419}
420
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200421/* Check if current gain_F measurement is in the range of our
422 * power detector windows. If we get a measurement outside range
423 * we know it's not accurate (detectors can't measure anything outside
424 * their detection window) so we must ignore it */
425static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200426{
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200427 const struct ath5k_rf_reg *rf_regs;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200428 u32 step, mix_ovr, level[4];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200429 u32 *rf;
430
431 if (ah->ah_rf_banks == NULL)
432 return false;
433
434 rf = ah->ah_rf_banks;
435
436 if (ah->ah_radio == AR5K_RF5111) {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200437
438 rf_regs = rf_regs_5111;
439 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
440
441 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
442 false);
443
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200444 level[0] = 0;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200445 level[1] = (step == 63) ? 50 : step + 4;
446 level[2] = (step != 63) ? 64 : level[0];
447 level[3] = level[2] + 50 ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200448
449 ah->ah_gain.g_high = level[3] -
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200450 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200451 ah->ah_gain.g_low = level[0] +
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200452 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200453 } else {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200454
455 rf_regs = rf_regs_5112;
456 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
457
458 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
459 false);
460
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200461 level[0] = level[2] = 0;
462
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200463 if (mix_ovr == 1) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200464 level[1] = level[3] = 83;
465 } else {
466 level[1] = level[3] = 107;
467 ah->ah_gain.g_high = 55;
468 }
469 }
470
471 return (ah->ah_gain.g_current >= level[0] &&
472 ah->ah_gain.g_current <= level[1]) ||
473 (ah->ah_gain.g_current >= level[2] &&
474 ah->ah_gain.g_current <= level[3]);
475}
476
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200477/* Perform gain_F adjustment by choosing the right set
Bob Copelanda180a132010-08-15 13:03:12 -0400478 * of parameters from RF gain optimization ladder */
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200479static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200480{
481 const struct ath5k_gain_opt *go;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200482 const struct ath5k_gain_opt_step *g_step;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200483 int ret = 0;
484
485 switch (ah->ah_radio) {
486 case AR5K_RF5111:
487 go = &rfgain_opt_5111;
488 break;
489 case AR5K_RF5112:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200490 go = &rfgain_opt_5112;
491 break;
492 default:
493 return 0;
494 }
495
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200496 g_step = &go->go_step[ah->ah_gain.g_step_idx];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200497
498 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200499
500 /* Reached maximum */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200501 if (ah->ah_gain.g_step_idx == 0)
502 return -1;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200503
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200504 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
505 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
506 ah->ah_gain.g_step_idx > 0;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200507 g_step = &go->go_step[ah->ah_gain.g_step_idx])
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200508 ah->ah_gain.g_target -= 2 *
509 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200510 g_step->gos_gain);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200511
512 ret = 1;
513 goto done;
514 }
515
516 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200517
518 /* Reached minimum */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200519 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
520 return -2;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200521
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200522 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
523 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
524 ah->ah_gain.g_step_idx < go->go_steps_count-1;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200525 g_step = &go->go_step[ah->ah_gain.g_step_idx])
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200526 ah->ah_gain.g_target -= 2 *
527 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200528 g_step->gos_gain);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200529
530 ret = 2;
531 goto done;
532 }
533
534done:
535 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
536 "ret %d, gain step %u, current gain %u, target gain %u\n",
537 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
538 ah->ah_gain.g_target);
539
540 return ret;
541}
542
Bob Copelanda180a132010-08-15 13:03:12 -0400543/* Main callback for thermal RF gain calibration engine
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200544 * Check for a new gain reading and schedule an adjustment
545 * if needed.
546 *
547 * TODO: Use sw interrupt to schedule reset if gain_F needs
548 * adjustment */
549enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
550{
551 u32 data, type;
552 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
553
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200554 if (ah->ah_rf_banks == NULL ||
555 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
556 return AR5K_RFGAIN_INACTIVE;
557
558 /* No check requested, either engine is inactive
559 * or an adjustment is already requested */
560 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
561 goto done;
562
563 /* Read the PAPD (Peak to Average Power Detector)
564 * register */
565 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
566
567 /* No probe is scheduled, read gain_F measurement */
568 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
569 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
570 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
571
572 /* If tx packet is CCK correct the gain_F measurement
573 * by cck ofdm gain delta */
574 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
575 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
576 ah->ah_gain.g_current +=
577 ee->ee_cck_ofdm_gain_delta;
578 else
579 ah->ah_gain.g_current +=
580 AR5K_GAIN_CCK_PROBE_CORR;
581 }
582
583 /* Further correct gain_F measurement for
584 * RF5112A radios */
585 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
586 ath5k_hw_rf_gainf_corr(ah);
587 ah->ah_gain.g_current =
588 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
589 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
590 0;
591 }
592
593 /* Check if measurement is ok and if we need
594 * to adjust gain, schedule a gain adjustment,
595 * else switch back to the acive state */
596 if (ath5k_hw_rf_check_gainf_readback(ah) &&
597 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
598 ath5k_hw_rf_gainf_adjust(ah)) {
599 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
600 } else {
601 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
602 }
603 }
604
605done:
606 return ah->ah_gain.g_state;
607}
608
Bob Copelanda180a132010-08-15 13:03:12 -0400609/* Write initial RF gain table to set the RF sensitivity
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200610 * this one works on all RF chips and has nothing to do
611 * with gain_F calibration */
Bruno Randolf26a51ad2010-12-21 17:30:37 +0900612static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200613{
614 const struct ath5k_ini_rfgain *ath5k_rfg;
Bruno Randolf26a51ad2010-12-21 17:30:37 +0900615 unsigned int i, size, index;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200616
617 switch (ah->ah_radio) {
618 case AR5K_RF5111:
619 ath5k_rfg = rfgain_5111;
620 size = ARRAY_SIZE(rfgain_5111);
621 break;
622 case AR5K_RF5112:
623 ath5k_rfg = rfgain_5112;
624 size = ARRAY_SIZE(rfgain_5112);
625 break;
626 case AR5K_RF2413:
627 ath5k_rfg = rfgain_2413;
628 size = ARRAY_SIZE(rfgain_2413);
629 break;
630 case AR5K_RF2316:
631 ath5k_rfg = rfgain_2316;
632 size = ARRAY_SIZE(rfgain_2316);
633 break;
634 case AR5K_RF5413:
635 ath5k_rfg = rfgain_5413;
636 size = ARRAY_SIZE(rfgain_5413);
637 break;
638 case AR5K_RF2317:
639 case AR5K_RF2425:
640 ath5k_rfg = rfgain_2425;
641 size = ARRAY_SIZE(rfgain_2425);
642 break;
643 default:
644 return -EINVAL;
645 }
646
Bruno Randolf26a51ad2010-12-21 17:30:37 +0900647 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200648
649 for (i = 0; i < size; i++) {
650 AR5K_REG_WAIT(i);
Bruno Randolf26a51ad2010-12-21 17:30:37 +0900651 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200652 (u32)ath5k_rfg[i].rfg_register);
653 }
654
655 return 0;
656}
657
658
659
660/********************\
661* RF Registers setup *
662\********************/
663
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200664/*
Bob Copelanda180a132010-08-15 13:03:12 -0400665 * Setup RF registers by writing RF buffer on hw
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200666 */
Nick Kossifidis9320b5c42010-11-23 20:36:45 +0200667static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
668 struct ieee80211_channel *channel, unsigned int mode)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200669{
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200670 const struct ath5k_rf_reg *rf_regs;
671 const struct ath5k_ini_rfbuffer *ini_rfb;
672 const struct ath5k_gain_opt *go = NULL;
673 const struct ath5k_gain_opt_step *g_step;
674 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
675 u8 ee_mode = 0;
676 u32 *rfb;
677 int i, obdb = -1, bank = -1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200678
679 switch (ah->ah_radio) {
680 case AR5K_RF5111:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200681 rf_regs = rf_regs_5111;
682 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
683 ini_rfb = rfb_5111;
684 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
685 go = &rfgain_opt_5111;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200686 break;
687 case AR5K_RF5112:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200688 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
689 rf_regs = rf_regs_5112a;
690 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
691 ini_rfb = rfb_5112a;
692 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
693 } else {
694 rf_regs = rf_regs_5112;
695 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
696 ini_rfb = rfb_5112;
697 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
698 }
699 go = &rfgain_opt_5112;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200700 break;
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500701 case AR5K_RF2413:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200702 rf_regs = rf_regs_2413;
703 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
704 ini_rfb = rfb_2413;
705 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
706 break;
707 case AR5K_RF2316:
708 rf_regs = rf_regs_2316;
709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
710 ini_rfb = rfb_2316;
711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
712 break;
713 case AR5K_RF5413:
714 rf_regs = rf_regs_5413;
715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
716 ini_rfb = rfb_5413;
717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
718 break;
719 case AR5K_RF2317:
720 rf_regs = rf_regs_2425;
721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
722 ini_rfb = rfb_2317;
723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500724 break;
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300725 case AR5K_RF2425:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200726 rf_regs = rf_regs_2425;
727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
728 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
729 ini_rfb = rfb_2425;
730 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
731 } else {
732 ini_rfb = rfb_2417;
733 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
734 }
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300735 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200736 default:
737 return -EINVAL;
738 }
739
Bob Copelanda180a132010-08-15 13:03:12 -0400740 /* If it's the first time we set RF buffer, allocate
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200741 * ah->ah_rf_banks based on ah->ah_rf_banks_size
742 * we set above */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200743 if (ah->ah_rf_banks == NULL) {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200744 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
745 GFP_KERNEL);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200746 if (ah->ah_rf_banks == NULL) {
747 ATH5K_ERR(ah->ah_sc, "out of memory\n");
748 return -ENOMEM;
749 }
750 }
751
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200752 /* Copy values to modify them */
753 rfb = ah->ah_rf_banks;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200754
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200755 for (i = 0; i < ah->ah_rf_banks_size; i++) {
756 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
757 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
758 return -EINVAL;
759 }
760
761 /* Bank changed, write down the offset */
762 if (bank != ini_rfb[i].rfb_bank) {
763 bank = ini_rfb[i].rfb_bank;
764 ah->ah_offset[bank] = i;
765 }
766
767 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
768 }
769
770 /* Set Output and Driver bias current (OB/DB) */
771 if (channel->hw_value & CHANNEL_2GHZ) {
772
773 if (channel->hw_value & CHANNEL_CCK)
774 ee_mode = AR5K_EEPROM_MODE_11B;
775 else
776 ee_mode = AR5K_EEPROM_MODE_11G;
777
778 /* For RF511X/RF211X combination we
779 * use b_OB and b_DB parameters stored
780 * in eeprom on ee->ee_ob[ee_mode][0]
781 *
782 * For all other chips we use OB/DB for 2Ghz
783 * stored in the b/g modal section just like
784 * 802.11a on ee->ee_ob[ee_mode][1] */
785 if ((ah->ah_radio == AR5K_RF5111) ||
786 (ah->ah_radio == AR5K_RF5112))
787 obdb = 0;
788 else
789 obdb = 1;
790
791 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
792 AR5K_RF_OB_2GHZ, true);
793
794 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
795 AR5K_RF_DB_2GHZ, true);
796
797 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
798 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
799 (ah->ah_radio == AR5K_RF5111)) {
800
801 /* For 11a, Turbo and XR we need to choose
802 * OB/DB based on frequency range */
803 ee_mode = AR5K_EEPROM_MODE_11A;
804 obdb = channel->center_freq >= 5725 ? 3 :
805 (channel->center_freq >= 5500 ? 2 :
806 (channel->center_freq >= 5260 ? 1 :
807 (channel->center_freq > 4000 ? 0 : -1)));
808
809 if (obdb < 0)
810 return -EINVAL;
811
812 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
813 AR5K_RF_OB_5GHZ, true);
814
815 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
816 AR5K_RF_DB_5GHZ, true);
817 }
818
819 g_step = &go->go_step[ah->ah_gain.g_step_idx];
820
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200821 /* Set turbo mode (N/A on RF5413) */
822 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
823 (ah->ah_radio != AR5K_RF5413))
824 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
825
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200826 /* Bank Modifications (chip-specific) */
827 if (ah->ah_radio == AR5K_RF5111) {
828
829 /* Set gain_F settings according to current step */
830 if (channel->hw_value & CHANNEL_OFDM) {
831
832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
833 AR5K_PHY_FRAME_CTL_TX_CLIP,
834 g_step->gos_param[0]);
835
836 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
837 AR5K_RF_PWD_90, true);
838
839 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
840 AR5K_RF_PWD_84, true);
841
842 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
843 AR5K_RF_RFGAIN_SEL, true);
844
845 /* We programmed gain_F parameters, switch back
846 * to active state */
847 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
848
849 }
850
851 /* Bank 6/7 setup */
852
853 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
854 AR5K_RF_PWD_XPD, true);
855
856 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
857 AR5K_RF_XPD_GAIN, true);
858
859 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
860 AR5K_RF_GAIN_I, true);
861
862 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
863 AR5K_RF_PLO_SEL, true);
864
Nick Kossifidisb2b4c692010-11-23 21:26:13 +0200865 /* Tweak power detectors for half/quarter rate support */
866 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
867 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
868 u8 wait_i;
869
870 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
871 AR5K_RF_WAIT_S, true);
872
873 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
874 0x1f : 0x10;
875
876 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
877 AR5K_RF_WAIT_I, true);
878 ath5k_hw_rfb_op(ah, rf_regs, 3,
879 AR5K_RF_MAX_TIME, true);
880
881 }
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200882 }
883
884 if (ah->ah_radio == AR5K_RF5112) {
885
886 /* Set gain_F settings according to current step */
887 if (channel->hw_value & CHANNEL_OFDM) {
888
889 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
890 AR5K_RF_MIXGAIN_OVR, true);
891
892 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
893 AR5K_RF_PWD_138, true);
894
895 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
896 AR5K_RF_PWD_137, true);
897
898 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
899 AR5K_RF_PWD_136, true);
900
901 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
902 AR5K_RF_PWD_132, true);
903
904 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
905 AR5K_RF_PWD_131, true);
906
907 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
908 AR5K_RF_PWD_130, true);
909
910 /* We programmed gain_F parameters, switch back
911 * to active state */
912 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
913 }
914
915 /* Bank 6/7 setup */
916
917 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
918 AR5K_RF_XPD_SEL, true);
919
920 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
921 /* Rev. 1 supports only one xpd */
922 ath5k_hw_rfb_op(ah, rf_regs,
923 ee->ee_x_gain[ee_mode],
924 AR5K_RF_XPD_GAIN, true);
925
926 } else {
Nick Kossifidisd1cb0bd2009-08-10 03:27:59 +0300927 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
928 if (ee->ee_pd_gains[ee_mode] > 1) {
929 ath5k_hw_rfb_op(ah, rf_regs,
930 pdg_curve_to_idx[0],
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200931 AR5K_RF_PD_GAIN_LO, true);
Nick Kossifidisd1cb0bd2009-08-10 03:27:59 +0300932 ath5k_hw_rfb_op(ah, rf_regs,
933 pdg_curve_to_idx[1],
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200934 AR5K_RF_PD_GAIN_HI, true);
Nick Kossifidisd1cb0bd2009-08-10 03:27:59 +0300935 } else {
936 ath5k_hw_rfb_op(ah, rf_regs,
937 pdg_curve_to_idx[0],
938 AR5K_RF_PD_GAIN_LO, true);
939 ath5k_hw_rfb_op(ah, rf_regs,
940 pdg_curve_to_idx[0],
941 AR5K_RF_PD_GAIN_HI, true);
942 }
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200943
944 /* Lower synth voltage on Rev 2 */
945 ath5k_hw_rfb_op(ah, rf_regs, 2,
946 AR5K_RF_HIGH_VC_CP, true);
947
948 ath5k_hw_rfb_op(ah, rf_regs, 2,
949 AR5K_RF_MID_VC_CP, true);
950
951 ath5k_hw_rfb_op(ah, rf_regs, 2,
952 AR5K_RF_LOW_VC_CP, true);
953
954 ath5k_hw_rfb_op(ah, rf_regs, 2,
955 AR5K_RF_PUSH_UP, true);
956
957 /* Decrease power consumption on 5213+ BaseBand */
958 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
959 ath5k_hw_rfb_op(ah, rf_regs, 1,
960 AR5K_RF_PAD2GND, true);
961
962 ath5k_hw_rfb_op(ah, rf_regs, 1,
963 AR5K_RF_XB2_LVL, true);
964
965 ath5k_hw_rfb_op(ah, rf_regs, 1,
966 AR5K_RF_XB5_LVL, true);
967
968 ath5k_hw_rfb_op(ah, rf_regs, 1,
969 AR5K_RF_PWD_167, true);
970
971 ath5k_hw_rfb_op(ah, rf_regs, 1,
972 AR5K_RF_PWD_166, true);
973 }
974 }
975
976 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
977 AR5K_RF_GAIN_I, true);
978
Nick Kossifidisb2b4c692010-11-23 21:26:13 +0200979 /* Tweak power detector for half/quarter rates */
980 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
981 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
982 u8 pd_delay;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200983
Nick Kossifidisb2b4c692010-11-23 21:26:13 +0200984 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
985 0xf : 0x8;
986
987 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
988 AR5K_RF_PD_PERIOD_A, true);
989 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
990 AR5K_RF_PD_DELAY_A, true);
991
992 }
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200993 }
994
995 if (ah->ah_radio == AR5K_RF5413 &&
996 channel->hw_value & CHANNEL_2GHZ) {
997
998 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
999 true);
1000
1001 /* Set optimum value for early revisions (on pci-e chips) */
1002 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1003 ah->ah_mac_srev < AR5K_SREV_AR5413)
1004 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1005 AR5K_RF_PWD_ICLOBUF_2G, true);
1006
1007 }
1008
1009 /* Write RF banks on hw */
1010 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1011 AR5K_REG_WAIT(i);
1012 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1013 }
1014
1015 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001016}
1017
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001018
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001019/**************************\
1020 PHY/RF channel functions
1021\**************************/
1022
1023/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001024 * Convertion needed for RF5110
1025 */
1026static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1027{
1028 u32 athchan;
1029
1030 /*
1031 * Convert IEEE channel/MHz to an internal channel value used
1032 * by the AR5210 chipset. This has not been verified with
1033 * newer chipsets like the AR5212A who have a completely
1034 * different RF/PHY part.
1035 */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001036 athchan = (ath5k_hw_bitswap(
1037 (ieee80211_frequency_to_channel(
1038 channel->center_freq) - 24) / 2, 5)
1039 << 1) | (1 << 6) | 0x1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001040 return athchan;
1041}
1042
1043/*
1044 * Set channel on RF5110
1045 */
1046static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1047 struct ieee80211_channel *channel)
1048{
1049 u32 data;
1050
1051 /*
1052 * Set the channel and wait
1053 */
1054 data = ath5k_hw_rf5110_chan2athchan(channel);
1055 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1056 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1057 mdelay(1);
1058
1059 return 0;
1060}
1061
1062/*
1063 * Convertion needed for 5111
1064 */
1065static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1066 struct ath5k_athchan_2ghz *athchan)
1067{
1068 int channel;
1069
1070 /* Cast this value to catch negative channel numbers (>= -19) */
1071 channel = (int)ieee;
1072
1073 /*
1074 * Map 2GHz IEEE channel to 5GHz Atheros channel
1075 */
1076 if (channel <= 13) {
1077 athchan->a2_athchan = 115 + channel;
1078 athchan->a2_flags = 0x46;
1079 } else if (channel == 14) {
1080 athchan->a2_athchan = 124;
1081 athchan->a2_flags = 0x44;
1082 } else if (channel >= 15 && channel <= 26) {
1083 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1084 athchan->a2_flags = 0x46;
1085 } else
1086 return -EINVAL;
1087
1088 return 0;
1089}
1090
1091/*
1092 * Set channel on 5111
1093 */
1094static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1095 struct ieee80211_channel *channel)
1096{
1097 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001098 unsigned int ath5k_channel =
1099 ieee80211_frequency_to_channel(channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001100 u32 data0, data1, clock;
1101 int ret;
1102
1103 /*
1104 * Set the channel on the RF5111 radio
1105 */
1106 data0 = data1 = 0;
1107
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001108 if (channel->hw_value & CHANNEL_2GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001109 /* Map 2GHz channel to 5GHz Atheros channel ID */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001110 ret = ath5k_hw_rf5111_chan2athchan(
1111 ieee80211_frequency_to_channel(channel->center_freq),
1112 &ath5k_channel_2ghz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001113 if (ret)
1114 return ret;
1115
1116 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1117 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1118 << 5) | (1 << 4);
1119 }
1120
1121 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1122 clock = 1;
1123 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1124 (clock << 1) | (1 << 10) | 1;
1125 } else {
1126 clock = 0;
1127 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1128 << 2) | (clock << 1) | (1 << 10) | 1;
1129 }
1130
1131 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1132 AR5K_RF_BUFFER);
1133 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1134 AR5K_RF_BUFFER_CONTROL_3);
1135
1136 return 0;
1137}
1138
1139/*
1140 * Set channel on 5112 and newer
1141 */
1142static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1143 struct ieee80211_channel *channel)
1144{
1145 u32 data, data0, data1, data2;
1146 u16 c;
1147
1148 data = data0 = data1 = data2 = 0;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001149 c = channel->center_freq;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001150
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001151 if (c < 4800) {
1152 if (!((c - 2224) % 5)) {
1153 data0 = ((2 * (c - 704)) - 3040) / 10;
1154 data1 = 1;
1155 } else if (!((c - 2192) % 5)) {
1156 data0 = ((2 * (c - 672)) - 3040) / 10;
1157 data1 = 0;
1158 } else
1159 return -EINVAL;
1160
1161 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
Bob Copeland1968cc72010-04-07 23:55:56 -04001162 } else if ((c % 5) != 2 || c > 5435) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001163 if (!(c % 20) && c >= 5120) {
1164 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1165 data2 = ath5k_hw_bitswap(3, 2);
1166 } else if (!(c % 10)) {
1167 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1168 data2 = ath5k_hw_bitswap(2, 2);
1169 } else if (!(c % 5)) {
1170 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1171 data2 = ath5k_hw_bitswap(1, 2);
1172 } else
1173 return -EINVAL;
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001174 } else {
Bob Copeland1968cc72010-04-07 23:55:56 -04001175 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001176 data2 = ath5k_hw_bitswap(0, 2);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001177 }
1178
1179 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1180
1181 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1182 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1183
1184 return 0;
1185}
1186
1187/*
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001188 * Set the channel on the RF2425
1189 */
1190static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1191 struct ieee80211_channel *channel)
1192{
1193 u32 data, data0, data2;
1194 u16 c;
1195
1196 data = data0 = data2 = 0;
1197 c = channel->center_freq;
1198
1199 if (c < 4800) {
1200 data0 = ath5k_hw_bitswap((c - 2272), 8);
1201 data2 = 0;
1202 /* ? 5GHz ? */
Bob Copeland1968cc72010-04-07 23:55:56 -04001203 } else if ((c % 5) != 2 || c > 5435) {
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001204 if (!(c % 20) && c < 5120)
1205 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1206 else if (!(c % 10))
1207 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1208 else if (!(c % 5))
1209 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1210 else
1211 return -EINVAL;
1212 data2 = ath5k_hw_bitswap(1, 2);
1213 } else {
Bob Copeland1968cc72010-04-07 23:55:56 -04001214 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001215 data2 = ath5k_hw_bitswap(0, 2);
1216 }
1217
1218 data = (data0 << 4) | data2 << 2 | 0x1001;
1219
1220 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1221 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1222
1223 return 0;
1224}
1225
1226/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001227 * Set a channel on the radio chip
1228 */
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001229static int ath5k_hw_channel(struct ath5k_hw *ah,
1230 struct ieee80211_channel *channel)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001231{
1232 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001233 /*
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001234 * Check bounds supported by the PHY (we don't care about regultory
1235 * restrictions at this point). Note: hw_value already has the band
1236 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1237 * of the band by that */
1238 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001239 ATH5K_ERR(ah->ah_sc,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001240 "channel frequency (%u MHz) out of supported "
1241 "band range\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001242 channel->center_freq);
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001243 return -EINVAL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001244 }
1245
1246 /*
1247 * Set the channel and wait
1248 */
1249 switch (ah->ah_radio) {
1250 case AR5K_RF5110:
1251 ret = ath5k_hw_rf5110_channel(ah, channel);
1252 break;
1253 case AR5K_RF5111:
1254 ret = ath5k_hw_rf5111_channel(ah, channel);
1255 break;
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001256 case AR5K_RF2425:
1257 ret = ath5k_hw_rf2425_channel(ah, channel);
1258 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001259 default:
1260 ret = ath5k_hw_rf5112_channel(ah, channel);
1261 break;
1262 }
1263
1264 if (ret)
1265 return ret;
1266
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001267 /* Set JAPAN setting for channel 14 */
1268 if (channel->center_freq == 2484) {
1269 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1270 AR5K_PHY_CCKTXCTL_JAPAN);
1271 } else {
1272 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1273 AR5K_PHY_CCKTXCTL_WORLD);
1274 }
1275
Bob Copeland46026e82009-06-10 22:22:20 -04001276 ah->ah_current_channel = channel;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001277
1278 return 0;
1279}
1280
1281/*****************\
1282 PHY calibration
1283\*****************/
1284
Bob Copelande5e26472009-10-14 14:16:30 -04001285static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1286{
1287 s32 val;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001288
Bob Copelande5e26472009-10-14 14:16:30 -04001289 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
Andreas Herrmann7919a572010-08-30 19:04:01 +00001290 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
Bob Copelande5e26472009-10-14 14:16:30 -04001291}
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001292
Bob Copelande5e26472009-10-14 14:16:30 -04001293void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1294{
1295 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001296
Bob Copelande5e26472009-10-14 14:16:30 -04001297 ah->ah_nfcal_hist.index = 0;
1298 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1299 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1300}
1301
1302static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1303{
1304 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1305 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1306 hist->nfval[hist->index] = noise_floor;
1307}
1308
1309static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1310{
1311 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1312 s16 tmp;
1313 int i, j;
1314
1315 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1316 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1317 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1318 if (sort[j] > sort[j-1]) {
1319 tmp = sort[j];
1320 sort[j] = sort[j-1];
1321 sort[j-1] = tmp;
1322 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001323 }
1324 }
Bob Copelande5e26472009-10-14 14:16:30 -04001325 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1326 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1327 "cal %d:%d\n", i, sort[i]);
1328 }
1329 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1330}
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001331
Bob Copelande5e26472009-10-14 14:16:30 -04001332/*
1333 * When we tell the hardware to perform a noise floor calibration
1334 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1335 * sample-and-hold the minimum noise level seen at the antennas.
1336 * This value is then stored in a ring buffer of recently measured
1337 * noise floor values so we have a moving window of the last few
1338 * samples.
1339 *
1340 * The median of the values in the history is then loaded into the
1341 * hardware for its own use for RSSI and CCA measurements.
1342 */
Bruno Randolf9e04a7e2010-05-19 10:31:00 +09001343void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
Bob Copelande5e26472009-10-14 14:16:30 -04001344{
1345 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1346 u32 val;
1347 s16 nf, threshold;
1348 u8 ee_mode;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001349
Bob Copelande5e26472009-10-14 14:16:30 -04001350 /* keep last value if calibration hasn't completed */
1351 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1352 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1353 "NF did not complete in calibration window\n");
1354
1355 return;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001356 }
1357
Bruno Randolf0207c0c2010-12-21 17:30:43 +09001358 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
Bob Copelande5e26472009-10-14 14:16:30 -04001359
1360 /* completed NF calibration, test threshold */
1361 nf = ath5k_hw_read_measured_noise_floor(ah);
1362 threshold = ee->ee_noise_floor_thr[ee_mode];
1363
1364 if (nf > threshold) {
1365 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1366 "noise floor failure detected; "
1367 "read %d, threshold %d\n",
1368 nf, threshold);
1369
1370 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1371 }
1372
1373 ath5k_hw_update_nfcal_hist(ah, nf);
1374 nf = ath5k_hw_get_median_noise_floor(ah);
1375
1376 /* load noise floor (in .5 dBm) so the hardware will use it */
1377 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1378 val |= (nf * 2) & AR5K_PHY_NF_M;
1379 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1380
1381 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1382 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1383
1384 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1385 0, false);
1386
1387 /*
1388 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1389 * so that we're not capped by the median we just loaded.
1390 * This will be used as the initial value for the next noise
1391 * floor calibration.
1392 */
1393 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1394 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1395 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1396 AR5K_PHY_AGCCTL_NF_EN |
1397 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1398 AR5K_PHY_AGCCTL_NF);
1399
1400 ah->ah_noise_floor = nf;
1401
1402 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1403 "noise floor calibrated: %d\n", nf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001404}
1405
1406/*
1407 * Perform a PHY calibration on RF5110
1408 * -Fix BPSK/QAM Constellation (I/Q correction)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001409 */
1410static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1411 struct ieee80211_channel *channel)
1412{
1413 u32 phy_sig, phy_agc, phy_sat, beacon;
1414 int ret;
1415
1416 /*
1417 * Disable beacons and RX/TX queues, wait
1418 */
1419 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
Bruno Randolfeada7ca2010-09-27 13:02:40 +09001420 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001421 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1422 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1423
Nick Kossifidis84e463f2008-09-17 03:33:19 +03001424 mdelay(2);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001425
1426 /*
1427 * Set the channel (with AGC turned off)
1428 */
1429 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1430 udelay(10);
1431 ret = ath5k_hw_channel(ah, channel);
1432
1433 /*
1434 * Activate PHY and wait
1435 */
1436 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1437 mdelay(1);
1438
1439 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1440
1441 if (ret)
1442 return ret;
1443
1444 /*
1445 * Calibrate the radio chip
1446 */
1447
1448 /* Remember normal state */
1449 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1450 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1451 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1452
1453 /* Update radio registers */
1454 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1455 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1456
1457 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1458 AR5K_PHY_AGCCOARSE_LO)) |
1459 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1460 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1461
1462 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1463 AR5K_PHY_ADCSAT_THR)) |
1464 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1465 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1466
1467 udelay(20);
1468
1469 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1470 udelay(10);
1471 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1472 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1473
1474 mdelay(1);
1475
1476 /*
1477 * Enable calibration and wait until completion
1478 */
1479 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1480
1481 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1482 AR5K_PHY_AGCCTL_CAL, 0, false);
1483
1484 /* Reset to normal state */
1485 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1486 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1487 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1488
1489 if (ret) {
1490 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001491 channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001492 return ret;
1493 }
1494
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001495 /*
1496 * Re-enable RX/TX and beacons
1497 */
1498 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
Bruno Randolfeada7ca2010-09-27 13:02:40 +09001499 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001500 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1501
1502 return 0;
1503}
1504
1505/*
Bruno Randolf9e04a7e2010-05-19 10:31:00 +09001506 * Perform I/Q calibration on RF5111/5112 and newer chips
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001507 */
Bruno Randolf9e04a7e2010-05-19 10:31:00 +09001508static int
1509ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001510{
1511 u32 i_pwr, q_pwr;
1512 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001513 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001514
Joe Perchese9010e22008-03-07 14:21:16 -08001515 if (!ah->ah_calibration ||
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001516 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
Bruno Randolf9e04a7e2010-05-19 10:31:00 +09001517 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001518
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001519 /* Calibration has finished, get the results and re-run */
Bruno Randolf86415d42010-03-09 16:56:05 +09001520 /* work around empty results which can apparently happen on 5212 */
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001521 for (i = 0; i <= 10; i++) {
1522 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1523 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1524 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
Bruno Randolf86415d42010-03-09 16:56:05 +09001525 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1526 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1527 if (i_pwr && q_pwr)
1528 break;
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001529 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001530
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001531 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
Bruno Randolf49a85d22010-03-09 16:56:15 +09001532
1533 if (ah->ah_version == AR5K_AR5211)
1534 q_coffd = q_pwr >> 6;
1535 else
1536 q_coffd = q_pwr >> 7;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001537
Bruno Randolf86415d42010-03-09 16:56:05 +09001538 /* protect against divide by 0 and loss of sign bits */
1539 if (i_coffd == 0 || q_coffd < 2)
Fabio Rossi516c6e12010-09-08 22:37:41 +02001540 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001541
Bruno Randolf86415d42010-03-09 16:56:05 +09001542 i_coff = (-iq_corr) / i_coffd;
1543 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001544
John W. Linvilleace5d5d2010-04-08 16:34:49 -04001545 if (ah->ah_version == AR5K_AR5211)
1546 q_coff = (i_pwr / q_coffd) - 64;
1547 else
1548 q_coff = (i_pwr / q_coffd) - 128;
Bruno Randolf86415d42010-03-09 16:56:05 +09001549 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001550
Bruno Randolf86415d42010-03-09 16:56:05 +09001551 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1552 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1553 i_coff, q_coff, i_coffd, q_coffd);
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001554
Bruno Randolf86415d42010-03-09 16:56:05 +09001555 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1556 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1557 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1558 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001559
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001560 /* Re-enable calibration -if we don't we'll commit
1561 * the same values again and again */
1562 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1563 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1564 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1565
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001566 return 0;
1567}
1568
1569/*
1570 * Perform a PHY calibration
1571 */
1572int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1573 struct ieee80211_channel *channel)
1574{
1575 int ret;
1576
1577 if (ah->ah_radio == AR5K_RF5110)
1578 ret = ath5k_hw_rf5110_calibrate(ah, channel);
Bruno Randolf9e04a7e2010-05-19 10:31:00 +09001579 else {
1580 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1581 ath5k_hw_request_rfgain_probe(ah);
1582 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001583
1584 return ret;
1585}
1586
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001587
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001588/***************************\
1589* Spur mitigation functions *
1590\***************************/
1591
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001592static void
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001593ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1594 struct ieee80211_channel *channel)
1595{
1596 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1597 u32 mag_mask[4] = {0, 0, 0, 0};
1598 u32 pilot_mask[2] = {0, 0};
1599 /* Note: fbin values are scaled up by 2 */
1600 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1601 s32 spur_delta_phase, spur_freq_sigma_delta;
1602 s32 spur_offset, num_symbols_x16;
1603 u8 num_symbol_offsets, i, freq_band;
1604
1605 /* Convert current frequency to fbin value (the same way channels
1606 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1607 * up by 2 so we can compare it later */
1608 if (channel->hw_value & CHANNEL_2GHZ) {
1609 chan_fbin = (channel->center_freq - 2300) * 10;
1610 freq_band = AR5K_EEPROM_BAND_2GHZ;
1611 } else {
1612 chan_fbin = (channel->center_freq - 4900) * 10;
1613 freq_band = AR5K_EEPROM_BAND_5GHZ;
1614 }
1615
1616 /* Check if any spur_chan_fbin from EEPROM is
1617 * within our current channel's spur detection range */
1618 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1619 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1620 /* XXX: Half/Quarter channels ?*/
Nick Kossifidisa2677fe2010-11-23 21:28:15 +02001621 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001622 spur_detection_window *= 2;
1623
1624 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1625 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1626
1627 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1628 * so it's zero if we got nothing from EEPROM */
1629 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1630 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1631 break;
1632 }
1633
1634 if ((chan_fbin - spur_detection_window <=
1635 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1636 (chan_fbin + spur_detection_window >=
1637 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1638 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1639 break;
1640 }
1641 }
1642
1643 /* We need to enable spur filter for this channel */
1644 if (spur_chan_fbin) {
1645 spur_offset = spur_chan_fbin - chan_fbin;
1646 /*
1647 * Calculate deltas:
1648 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1649 * spur_delta_phase -> spur_offset / chip_freq << 11
Nick Kossifidisa2677fe2010-11-23 21:28:15 +02001650 * Note: Both values have 100Hz resolution
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001651 */
Nick Kossifidisa2677fe2010-11-23 21:28:15 +02001652 switch (ah->ah_bwmode) {
1653 case AR5K_BWMODE_40MHZ:
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001654 /* Both sample_freq and chip_freq are 80MHz */
1655 spur_delta_phase = (spur_offset << 16) / 25;
1656 spur_freq_sigma_delta = (spur_delta_phase >> 10);
Nick Kossifidisa2677fe2010-11-23 21:28:15 +02001657 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001658 break;
Nick Kossifidisa2677fe2010-11-23 21:28:15 +02001659 case AR5K_BWMODE_10MHZ:
1660 /* Both sample_freq and chip_freq are 20MHz (?) */
1661 spur_delta_phase = (spur_offset << 18) / 25;
1662 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1663 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1664 case AR5K_BWMODE_5MHZ:
1665 /* Both sample_freq and chip_freq are 10MHz (?) */
1666 spur_delta_phase = (spur_offset << 19) / 25;
1667 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1668 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001669 default:
Nick Kossifidisa2677fe2010-11-23 21:28:15 +02001670 if (channel->hw_value == CHANNEL_A) {
1671 /* Both sample_freq and chip_freq are 40MHz */
1672 spur_delta_phase = (spur_offset << 17) / 25;
1673 spur_freq_sigma_delta =
1674 (spur_delta_phase >> 10);
1675 symbol_width =
1676 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1677 } else {
1678 /* sample_freq -> 40MHz chip_freq -> 44MHz
1679 * (for b compatibility) */
1680 spur_delta_phase = (spur_offset << 17) / 25;
1681 spur_freq_sigma_delta =
1682 (spur_offset << 8) / 55;
1683 symbol_width =
1684 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1685 }
1686 break;
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001687 }
1688
1689 /* Calculate pilot and magnitude masks */
1690
1691 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1692 * and divide by symbol_width to find how many symbols we have
1693 * Note: number of symbols is scaled up by 16 */
1694 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1695
1696 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1697 if (!(num_symbols_x16 & 0xF))
1698 /* _X_ */
1699 num_symbol_offsets = 3;
1700 else
1701 /* _xx_ */
1702 num_symbol_offsets = 4;
1703
1704 for (i = 0; i < num_symbol_offsets; i++) {
1705
1706 /* Calculate pilot mask */
1707 s32 curr_sym_off =
1708 (num_symbols_x16 / 16) + i + 25;
1709
1710 /* Pilot magnitude mask seems to be a way to
1711 * declare the boundaries for our detection
1712 * window or something, it's 2 for the middle
1713 * value(s) where the symbol is expected to be
1714 * and 1 on the boundary values */
1715 u8 plt_mag_map =
1716 (i == 0 || i == (num_symbol_offsets - 1))
1717 ? 1 : 2;
1718
1719 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1720 if (curr_sym_off <= 25)
1721 pilot_mask[0] |= 1 << curr_sym_off;
1722 else if (curr_sym_off >= 27)
1723 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1724 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1725 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1726
1727 /* Calculate magnitude mask (for viterbi decoder) */
1728 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1729 mag_mask[0] |=
1730 plt_mag_map << (curr_sym_off + 1) * 2;
1731 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1732 mag_mask[1] |=
1733 plt_mag_map << (curr_sym_off - 15) * 2;
1734 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1735 mag_mask[2] |=
1736 plt_mag_map << (curr_sym_off - 31) * 2;
Bob Copeland53b1cf82010-08-24 21:37:14 -04001737 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001738 mag_mask[3] |=
1739 plt_mag_map << (curr_sym_off - 47) * 2;
1740
1741 }
1742
1743 /* Write settings on hw to enable spur filter */
1744 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1745 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1746 /* XXX: Self correlator also ? */
1747 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1748 AR5K_PHY_IQ_PILOT_MASK_EN |
1749 AR5K_PHY_IQ_CHAN_MASK_EN |
1750 AR5K_PHY_IQ_SPUR_FILT_EN);
1751
1752 /* Set delta phase and freq sigma delta */
1753 ath5k_hw_reg_write(ah,
1754 AR5K_REG_SM(spur_delta_phase,
1755 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1756 AR5K_REG_SM(spur_freq_sigma_delta,
1757 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1758 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1759 AR5K_PHY_TIMING_11);
1760
1761 /* Write pilot masks */
1762 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1763 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1764 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1765 pilot_mask[1]);
1766
1767 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1768 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1769 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1770 pilot_mask[1]);
1771
1772 /* Write magnitude masks */
1773 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1774 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1775 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1776 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1777 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1778 mag_mask[3]);
1779
1780 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1781 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1782 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1783 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1784 AR5K_PHY_BIN_MASK2_4_MASK_4,
1785 mag_mask[3]);
1786
1787 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1788 AR5K_PHY_IQ_SPUR_FILT_EN) {
1789 /* Clean up spur mitigation settings and disable fliter */
1790 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1791 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1792 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1793 AR5K_PHY_IQ_PILOT_MASK_EN |
1794 AR5K_PHY_IQ_CHAN_MASK_EN |
1795 AR5K_PHY_IQ_SPUR_FILT_EN);
1796 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1797
1798 /* Clear pilot masks */
1799 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1800 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1801 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1802 0);
1803
1804 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1805 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1806 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1807 0);
1808
1809 /* Clear magnitude masks */
1810 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1811 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1812 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1814 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1815 0);
1816
1817 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1818 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1819 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1820 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1821 AR5K_PHY_BIN_MASK2_4_MASK_4,
1822 0);
1823 }
1824}
1825
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001826
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001827/*****************\
1828* Antenna control *
1829\*****************/
1830
Pavel Roskin626ede62010-02-18 20:28:02 -05001831static void /*TODO:Boundary check*/
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001832ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001833{
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001834 if (ah->ah_version != AR5K_AR5210)
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001835 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001836}
1837
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001838/*
1839 * Enable/disable fast rx antenna diversity
1840 */
1841static void
1842ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1843{
1844 switch (ee_mode) {
1845 case AR5K_EEPROM_MODE_11G:
1846 /* XXX: This is set to
1847 * disabled on initvals !!! */
1848 case AR5K_EEPROM_MODE_11A:
1849 if (enable)
1850 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1851 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1852 else
1853 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1854 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1855 break;
1856 case AR5K_EEPROM_MODE_11B:
1857 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1858 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1859 break;
1860 default:
1861 return;
1862 }
1863
1864 if (enable) {
1865 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
Bruno Randolf6665b542010-06-28 11:01:48 +09001866 AR5K_PHY_RESTART_DIV_GC, 4);
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001867
1868 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1869 AR5K_PHY_FAST_ANT_DIV_EN);
1870 } else {
1871 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
Bruno Randolf39d5b2c2010-06-07 13:11:25 +09001872 AR5K_PHY_RESTART_DIV_GC, 0);
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001873
1874 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1875 AR5K_PHY_FAST_ANT_DIV_EN);
1876 }
1877}
1878
Bruno Randolf0ca74022010-06-07 13:11:30 +09001879void
1880ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1881{
1882 u8 ant0, ant1;
1883
1884 /*
1885 * In case a fixed antenna was set as default
1886 * use the same switch table twice.
1887 */
1888 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1889 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1890 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1891 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1892 else {
1893 ant0 = AR5K_ANT_SWTABLE_A;
1894 ant1 = AR5K_ANT_SWTABLE_B;
1895 }
1896
1897 /* Set antenna idle switch table */
1898 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1899 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1900 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1901 AR5K_PHY_ANT_CTL_TXRX_EN));
1902
1903 /* Set antenna switch tables */
1904 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1905 AR5K_PHY_ANT_SWITCH_TABLE_0);
1906 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1907 AR5K_PHY_ANT_SWITCH_TABLE_1);
1908}
1909
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001910/*
1911 * Set antenna operating mode
1912 */
1913void
1914ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1915{
Bob Copeland46026e82009-06-10 22:22:20 -04001916 struct ieee80211_channel *channel = ah->ah_current_channel;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001917 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1918 bool use_def_for_sg;
Dan Carpentera8851d12011-01-03 08:46:29 +03001919 int ee_mode;
1920 u8 def_ant, tx_ant;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001921 u32 sta_id1 = 0;
1922
Bruno Randolf436c1092010-06-07 13:11:19 +09001923 /* if channel is not initialized yet we can't set the antennas
1924 * so just store the mode. it will be set on the next reset */
1925 if (channel == NULL) {
1926 ah->ah_ant_mode = ant_mode;
1927 return;
1928 }
1929
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001930 def_ant = ah->ah_def_ant;
1931
Bruno Randolf0207c0c2010-12-21 17:30:43 +09001932 ee_mode = ath5k_eeprom_mode_from_channel(channel);
1933 if (ee_mode < 0) {
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001934 ATH5K_ERR(ah->ah_sc,
1935 "invalid channel: %d\n", channel->center_freq);
1936 return;
1937 }
1938
1939 switch (ant_mode) {
1940 case AR5K_ANTMODE_DEFAULT:
1941 tx_ant = 0;
1942 use_def_for_tx = false;
1943 update_def_on_tx = false;
1944 use_def_for_rts = false;
1945 use_def_for_sg = false;
1946 fast_div = true;
1947 break;
1948 case AR5K_ANTMODE_FIXED_A:
1949 def_ant = 1;
Bruno Randolf8bd8bea2010-03-09 16:55:23 +09001950 tx_ant = 1;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001951 use_def_for_tx = true;
1952 update_def_on_tx = false;
1953 use_def_for_rts = true;
1954 use_def_for_sg = true;
1955 fast_div = false;
1956 break;
1957 case AR5K_ANTMODE_FIXED_B:
1958 def_ant = 2;
Bruno Randolf8bd8bea2010-03-09 16:55:23 +09001959 tx_ant = 2;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001960 use_def_for_tx = true;
1961 update_def_on_tx = false;
1962 use_def_for_rts = true;
1963 use_def_for_sg = true;
1964 fast_div = false;
1965 break;
1966 case AR5K_ANTMODE_SINGLE_AP:
1967 def_ant = 1; /* updated on tx */
1968 tx_ant = 0;
1969 use_def_for_tx = true;
1970 update_def_on_tx = true;
1971 use_def_for_rts = true;
1972 use_def_for_sg = true;
1973 fast_div = true;
1974 break;
1975 case AR5K_ANTMODE_SECTOR_AP:
1976 tx_ant = 1; /* variable */
1977 use_def_for_tx = false;
1978 update_def_on_tx = false;
1979 use_def_for_rts = true;
1980 use_def_for_sg = false;
1981 fast_div = false;
1982 break;
1983 case AR5K_ANTMODE_SECTOR_STA:
1984 tx_ant = 1; /* variable */
1985 use_def_for_tx = true;
1986 update_def_on_tx = false;
1987 use_def_for_rts = true;
1988 use_def_for_sg = false;
1989 fast_div = true;
1990 break;
1991 case AR5K_ANTMODE_DEBUG:
1992 def_ant = 1;
1993 tx_ant = 2;
1994 use_def_for_tx = false;
1995 update_def_on_tx = false;
1996 use_def_for_rts = false;
1997 use_def_for_sg = false;
1998 fast_div = false;
1999 break;
2000 default:
2001 return;
2002 }
2003
2004 ah->ah_tx_ant = tx_ant;
2005 ah->ah_ant_mode = ant_mode;
Bruno Randolfcaec9112010-03-09 16:55:28 +09002006 ah->ah_def_ant = def_ant;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04002007
2008 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2009 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2010 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2011 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2012
2013 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2014
2015 if (sta_id1)
2016 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2017
Bruno Randolf0ca74022010-06-07 13:11:30 +09002018 ath5k_hw_set_antenna_switch(ah, ee_mode);
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04002019 /* Note: set diversity before default antenna
2020 * because it won't work correctly */
2021 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2022 ath5k_hw_set_def_antenna(ah, def_ant);
2023}
2024
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002025
2026/****************\
2027* TX power setup *
2028\****************/
2029
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002030/*
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002031 * Helper functions
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002032 */
2033
2034/*
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002035 * Do linear interpolation between two given (x, y) points
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002036 */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002037static s16
2038ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2039 s16 y_left, s16 y_right)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002040{
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002041 s16 ratio, result;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002042
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002043 /* Avoid divide by zero and skip interpolation
2044 * if we have the same point */
2045 if ((x_left == x_right) || (y_left == y_right))
2046 return y_left;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002047
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002048 /*
2049 * Since we use ints and not fps, we need to scale up in
2050 * order to get a sane ratio value (or else we 'll eg. get
2051 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2052 * to have some accuracy both for 0.5 and 0.25 steps.
2053 */
2054 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002055
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002056 /* Now scale down to be in range */
2057 result = y_left + (ratio * (target - x_left) / 100);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002058
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002059 return result;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002060}
2061
2062/*
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002063 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2064 *
2065 * Since we have the top of the curve and we draw the line below
2066 * until we reach 1 (1 pcdac step) we need to know which point
2067 * (x value) that is so that we don't go below y axis and have negative
2068 * pcdac values when creating the curve, or fill the table with zeroes.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002069 */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002070static s16
2071ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2072 const s16 *pwrL, const s16 *pwrR)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002073{
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002074 s8 tmp;
2075 s16 min_pwrL, min_pwrR;
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02002076 s16 pwr_i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002077
Nick Kossifidisd1cb0bd2009-08-10 03:27:59 +03002078 /* Some vendors write the same pcdac value twice !!! */
2079 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2080 return max(pwrL[0], pwrR[0]);
Bob Copeland9c8b3ed2009-05-19 23:37:31 -04002081
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02002082 if (pwrL[0] == pwrL[1])
2083 min_pwrL = pwrL[0];
2084 else {
2085 pwr_i = pwrL[0];
2086 do {
2087 pwr_i--;
2088 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2089 pwrL[0], pwrL[1],
2090 stepL[0], stepL[1]);
2091 } while (tmp > 1);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002092
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02002093 min_pwrL = pwr_i;
2094 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002095
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02002096 if (pwrR[0] == pwrR[1])
2097 min_pwrR = pwrR[0];
2098 else {
2099 pwr_i = pwrR[0];
2100 do {
2101 pwr_i--;
2102 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2103 pwrR[0], pwrR[1],
2104 stepR[0], stepR[1]);
2105 } while (tmp > 1);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002106
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02002107 min_pwrR = pwr_i;
2108 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002109
2110 /* Keep the right boundary so that it works for both curves */
2111 return max(min_pwrL, min_pwrR);
2112}
2113
2114/*
2115 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2116 * Power to PCDAC curve.
2117 *
2118 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2119 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2120 * PCDAC/PDADC step for each curve is 64 but we can write more than
2121 * one curves on hw so we can go up to 128 (which is the max step we
2122 * can write on the final table).
2123 *
2124 * We write y values (PCDAC/PDADC steps) on hw.
2125 */
2126static void
2127ath5k_create_power_curve(s16 pmin, s16 pmax,
2128 const s16 *pwr, const u8 *vpd,
2129 u8 num_points,
2130 u8 *vpd_table, u8 type)
2131{
2132 u8 idx[2] = { 0, 1 };
2133 s16 pwr_i = 2*pmin;
2134 int i;
2135
2136 if (num_points < 2)
2137 return;
2138
2139 /* We want the whole line, so adjust boundaries
2140 * to cover the entire power range. Note that
2141 * power values are already 0.25dB so no need
2142 * to multiply pwr_i by 2 */
2143 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2144 pwr_i = pmin;
2145 pmin = 0;
2146 pmax = 63;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002147 }
2148
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002149 /* Find surrounding turning points (TPs)
2150 * and interpolate between them */
2151 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2152 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2153
2154 /* We passed the right TP, move to the next set of TPs
2155 * if we pass the last TP, extrapolate above using the last
2156 * two TPs for ratio */
2157 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2158 idx[0]++;
2159 idx[1]++;
2160 }
2161
2162 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2163 pwr[idx[0]], pwr[idx[1]],
2164 vpd[idx[0]], vpd[idx[1]]);
2165
2166 /* Increase by 0.5dB
2167 * (0.25 dB units) */
2168 pwr_i += 2;
2169 }
2170}
2171
2172/*
2173 * Get the surrounding per-channel power calibration piers
2174 * for a given frequency so that we can interpolate between
2175 * them and come up with an apropriate dataset for our current
2176 * channel.
2177 */
2178static void
2179ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2180 struct ieee80211_channel *channel,
2181 struct ath5k_chan_pcal_info **pcinfo_l,
2182 struct ath5k_chan_pcal_info **pcinfo_r)
2183{
2184 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2185 struct ath5k_chan_pcal_info *pcinfo;
2186 u8 idx_l, idx_r;
2187 u8 mode, max, i;
2188 u32 target = channel->center_freq;
2189
2190 idx_l = 0;
2191 idx_r = 0;
2192
2193 if (!(channel->hw_value & CHANNEL_OFDM)) {
2194 pcinfo = ee->ee_pwr_cal_b;
2195 mode = AR5K_EEPROM_MODE_11B;
2196 } else if (channel->hw_value & CHANNEL_2GHZ) {
2197 pcinfo = ee->ee_pwr_cal_g;
2198 mode = AR5K_EEPROM_MODE_11G;
2199 } else {
2200 pcinfo = ee->ee_pwr_cal_a;
2201 mode = AR5K_EEPROM_MODE_11A;
2202 }
2203 max = ee->ee_n_piers[mode] - 1;
2204
2205 /* Frequency is below our calibrated
2206 * range. Use the lowest power curve
2207 * we have */
2208 if (target < pcinfo[0].freq) {
2209 idx_l = idx_r = 0;
2210 goto done;
2211 }
2212
2213 /* Frequency is above our calibrated
2214 * range. Use the highest power curve
2215 * we have */
2216 if (target > pcinfo[max].freq) {
2217 idx_l = idx_r = max;
2218 goto done;
2219 }
2220
2221 /* Frequency is inside our calibrated
2222 * channel range. Pick the surrounding
2223 * calibration piers so that we can
2224 * interpolate */
2225 for (i = 0; i <= max; i++) {
2226
2227 /* Frequency matches one of our calibration
2228 * piers, no need to interpolate, just use
2229 * that calibration pier */
2230 if (pcinfo[i].freq == target) {
2231 idx_l = idx_r = i;
2232 goto done;
2233 }
2234
2235 /* We found a calibration pier that's above
2236 * frequency, use this pier and the previous
2237 * one to interpolate */
2238 if (target < pcinfo[i].freq) {
2239 idx_r = i;
2240 idx_l = idx_r - 1;
2241 goto done;
2242 }
2243 }
2244
2245done:
2246 *pcinfo_l = &pcinfo[idx_l];
2247 *pcinfo_r = &pcinfo[idx_r];
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002248}
2249
2250/*
2251 * Get the surrounding per-rate power calibration data
2252 * for a given frequency and interpolate between power
2253 * values to set max target power supported by hw for
2254 * each rate.
2255 */
2256static void
2257ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2258 struct ieee80211_channel *channel,
2259 struct ath5k_rate_pcal_info *rates)
2260{
2261 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2262 struct ath5k_rate_pcal_info *rpinfo;
2263 u8 idx_l, idx_r;
2264 u8 mode, max, i;
2265 u32 target = channel->center_freq;
2266
2267 idx_l = 0;
2268 idx_r = 0;
2269
2270 if (!(channel->hw_value & CHANNEL_OFDM)) {
2271 rpinfo = ee->ee_rate_tpwr_b;
2272 mode = AR5K_EEPROM_MODE_11B;
2273 } else if (channel->hw_value & CHANNEL_2GHZ) {
2274 rpinfo = ee->ee_rate_tpwr_g;
2275 mode = AR5K_EEPROM_MODE_11G;
2276 } else {
2277 rpinfo = ee->ee_rate_tpwr_a;
2278 mode = AR5K_EEPROM_MODE_11A;
2279 }
2280 max = ee->ee_rate_target_pwr_num[mode] - 1;
2281
2282 /* Get the surrounding calibration
2283 * piers - same as above */
2284 if (target < rpinfo[0].freq) {
2285 idx_l = idx_r = 0;
2286 goto done;
2287 }
2288
2289 if (target > rpinfo[max].freq) {
2290 idx_l = idx_r = max;
2291 goto done;
2292 }
2293
2294 for (i = 0; i <= max; i++) {
2295
2296 if (rpinfo[i].freq == target) {
2297 idx_l = idx_r = i;
2298 goto done;
2299 }
2300
2301 if (target < rpinfo[i].freq) {
2302 idx_r = i;
2303 idx_l = idx_r - 1;
2304 goto done;
2305 }
2306 }
2307
2308done:
2309 /* Now interpolate power value, based on the frequency */
2310 rates->freq = target;
2311
2312 rates->target_power_6to24 =
2313 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2314 rpinfo[idx_r].freq,
2315 rpinfo[idx_l].target_power_6to24,
2316 rpinfo[idx_r].target_power_6to24);
2317
2318 rates->target_power_36 =
2319 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2320 rpinfo[idx_r].freq,
2321 rpinfo[idx_l].target_power_36,
2322 rpinfo[idx_r].target_power_36);
2323
2324 rates->target_power_48 =
2325 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2326 rpinfo[idx_r].freq,
2327 rpinfo[idx_l].target_power_48,
2328 rpinfo[idx_r].target_power_48);
2329
2330 rates->target_power_54 =
2331 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2332 rpinfo[idx_r].freq,
2333 rpinfo[idx_l].target_power_54,
2334 rpinfo[idx_r].target_power_54);
2335}
2336
2337/*
2338 * Get the max edge power for this channel if
2339 * we have such data from EEPROM's Conformance Test
2340 * Limits (CTL), and limit max power if needed.
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002341 */
2342static void
2343ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2344 struct ieee80211_channel *channel)
2345{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002346 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002347 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2348 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2349 u8 *ctl_val = ee->ee_ctl;
2350 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2351 s16 edge_pwr = 0;
2352 u8 rep_idx;
2353 u8 i, ctl_mode;
2354 u8 ctl_idx = 0xFF;
2355 u32 target = channel->center_freq;
2356
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002357 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
Bob Copeland6752ee92009-04-30 15:55:51 -04002358
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002359 switch (channel->hw_value & CHANNEL_MODES) {
2360 case CHANNEL_A:
Nick Kossifidisacb091d2010-11-23 21:49:53 +02002361 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2362 ctl_mode |= AR5K_CTL_TURBO;
2363 else
2364 ctl_mode |= AR5K_CTL_11A;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002365 break;
2366 case CHANNEL_G:
Nick Kossifidisacb091d2010-11-23 21:49:53 +02002367 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2368 ctl_mode |= AR5K_CTL_TURBOG;
2369 else
2370 ctl_mode |= AR5K_CTL_11G;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002371 break;
2372 case CHANNEL_B:
Bob Copeland6752ee92009-04-30 15:55:51 -04002373 ctl_mode |= AR5K_CTL_11B;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002374 break;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002375 case CHANNEL_XR:
2376 /* Fall through */
2377 default:
2378 return;
2379 }
Nick Kossifidis903b4742008-02-28 14:50:50 -05002380
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002381 for (i = 0; i < ee->ee_ctls; i++) {
2382 if (ctl_val[i] == ctl_mode) {
2383 ctl_idx = i;
2384 break;
2385 }
2386 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002387
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002388 /* If we have a CTL dataset available grab it and find the
2389 * edge power for our frequency */
2390 if (ctl_idx == 0xFF)
2391 return;
2392
2393 /* Edge powers are sorted by frequency from lower
2394 * to higher. Each CTL corresponds to 8 edge power
2395 * measurements. */
2396 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2397
2398 /* Don't do boundaries check because we
2399 * might have more that one bands defined
2400 * for this mode */
2401
2402 /* Get the edge power that's closer to our
2403 * frequency */
2404 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2405 rep_idx += i;
2406 if (target <= rep[rep_idx].freq)
2407 edge_pwr = (s16) rep[rep_idx].edge;
2408 }
2409
2410 if (edge_pwr)
2411 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2412}
2413
2414
2415/*
2416 * Power to PCDAC table functions
2417 */
2418
2419/*
2420 * Fill Power to PCDAC table on RF5111
2421 *
2422 * No further processing is needed for RF5111, the only thing we have to
2423 * do is fill the values below and above calibration range since eeprom data
2424 * may not cover the entire PCDAC table.
2425 */
2426static void
2427ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2428 s16 *table_max)
2429{
2430 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2431 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2432 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2433 s16 min_pwr, max_pwr;
2434
2435 /* Get table boundaries */
2436 min_pwr = table_min[0];
2437 pcdac_0 = pcdac_tmp[0];
2438
2439 max_pwr = table_max[0];
2440 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2441
2442 /* Extrapolate below minimum using pcdac_0 */
2443 pcdac_i = 0;
2444 for (i = 0; i < min_pwr; i++)
2445 pcdac_out[pcdac_i++] = pcdac_0;
2446
2447 /* Copy values from pcdac_tmp */
2448 pwr_idx = min_pwr;
2449 for (i = 0 ; pwr_idx <= max_pwr &&
2450 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2451 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2452 pwr_idx++;
2453 }
2454
2455 /* Extrapolate above maximum */
2456 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2457 pcdac_out[pcdac_i++] = pcdac_n;
2458
2459}
2460
2461/*
2462 * Combine available XPD Curves and fill Linear Power to PCDAC table
2463 * on RF5112
2464 *
2465 * RFX112 can have up to 2 curves (one for low txpower range and one for
2466 * higher txpower range). We need to put them both on pcdac_out and place
2467 * them in the correct location. In case we only have one curve available
2468 * just fit it on pcdac_out (it's supposed to cover the entire range of
2469 * available pwr levels since it's always the higher power curve). Extrapolate
2470 * below and above final table if needed.
2471 */
2472static void
2473ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2474 s16 *table_max, u8 pdcurves)
2475{
2476 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2477 u8 *pcdac_low_pwr;
2478 u8 *pcdac_high_pwr;
2479 u8 *pcdac_tmp;
2480 u8 pwr;
2481 s16 max_pwr_idx;
2482 s16 min_pwr_idx;
2483 s16 mid_pwr_idx = 0;
2484 /* Edge flag turs on the 7nth bit on the PCDAC
2485 * to delcare the higher power curve (force values
2486 * to be greater than 64). If we only have one curve
2487 * we don't need to set this, if we have 2 curves and
2488 * fill the table backwards this can also be used to
2489 * switch from higher power curve to lower power curve */
2490 u8 edge_flag;
2491 int i;
2492
2493 /* When we have only one curve available
2494 * that's the higher power curve. If we have
2495 * two curves the first is the high power curve
2496 * and the next is the low power curve. */
2497 if (pdcurves > 1) {
2498 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2499 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2500 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2501 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2502
2503 /* If table size goes beyond 31.5dB, keep the
2504 * upper 31.5dB range when setting tx power.
2505 * Note: 126 = 31.5 dB in quarter dB steps */
2506 if (table_max[0] - table_min[1] > 126)
2507 min_pwr_idx = table_max[0] - 126;
2508 else
2509 min_pwr_idx = table_min[1];
2510
2511 /* Since we fill table backwards
2512 * start from high power curve */
2513 pcdac_tmp = pcdac_high_pwr;
2514
2515 edge_flag = 0x40;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002516 } else {
2517 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2518 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2519 min_pwr_idx = table_min[0];
2520 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2521 pcdac_tmp = pcdac_high_pwr;
2522 edge_flag = 0;
2523 }
2524
2525 /* This is used when setting tx power*/
2526 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2527
2528 /* Fill Power to PCDAC table backwards */
2529 pwr = max_pwr_idx;
2530 for (i = 63; i >= 0; i--) {
2531 /* Entering lower power range, reset
2532 * edge flag and set pcdac_tmp to lower
2533 * power curve.*/
2534 if (edge_flag == 0x40 &&
2535 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2536 edge_flag = 0x00;
2537 pcdac_tmp = pcdac_low_pwr;
2538 pwr = mid_pwr_idx/2;
2539 }
2540
2541 /* Don't go below 1, extrapolate below if we have
2542 * already swithced to the lower power curve -or
2543 * we only have one curve and edge_flag is zero
2544 * anyway */
2545 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2546 while (i >= 0) {
2547 pcdac_out[i] = pcdac_out[i + 1];
2548 i--;
2549 }
2550 break;
2551 }
2552
2553 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2554
2555 /* Extrapolate above if pcdac is greater than
2556 * 126 -this can happen because we OR pcdac_out
2557 * value with edge_flag on high power curve */
2558 if (pcdac_out[i] > 126)
2559 pcdac_out[i] = 126;
2560
2561 /* Decrease by a 0.5dB step */
2562 pwr--;
2563 }
2564}
2565
2566/* Write PCDAC values on hw */
2567static void
Bruno Randolf56bd29d2010-12-21 17:30:26 +09002568ath5k_write_pcdac_table(struct ath5k_hw *ah)
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002569{
2570 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2571 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002572
2573 /*
2574 * Write TX power values
2575 */
2576 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2577 ath5k_hw_reg_write(ah,
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002578 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2579 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002580 AR5K_PHY_PCDAC_TXPOWER(i));
2581 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002582}
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002583
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002584
2585/*
2586 * Power to PDADC table functions
2587 */
2588
2589/*
2590 * Set the gain boundaries and create final Power to PDADC table
2591 *
2592 * We can have up to 4 pd curves, we need to do a simmilar process
2593 * as we do for RF5112. This time we don't have an edge_flag but we
2594 * set the gain boundaries on a separate register.
2595 */
2596static void
2597ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2598 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2599{
2600 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2601 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2602 u8 *pdadc_tmp;
2603 s16 pdadc_0;
2604 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2605 u8 pd_gain_overlap;
2606
2607 /* Note: Register value is initialized on initvals
2608 * there is no feedback from hw.
2609 * XXX: What about pd_gain_overlap from EEPROM ? */
2610 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2611 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2612
2613 /* Create final PDADC table */
2614 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2615 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2616
2617 if (pdg == pdcurves - 1)
2618 /* 2 dB boundary stretch for last
2619 * (higher power) curve */
2620 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2621 else
2622 /* Set gain boundary in the middle
2623 * between this curve and the next one */
2624 gain_boundaries[pdg] =
2625 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2626
2627 /* Sanity check in case our 2 db stretch got out of
2628 * range. */
2629 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2630 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2631
2632 /* For the first curve (lower power)
2633 * start from 0 dB */
2634 if (pdg == 0)
2635 pdadc_0 = 0;
2636 else
2637 /* For the other curves use the gain overlap */
2638 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2639 pd_gain_overlap;
2640
2641 /* Force each power step to be at least 0.5 dB */
2642 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2643 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2644 else
2645 pwr_step = 1;
2646
2647 /* If pdadc_0 is negative, we need to extrapolate
2648 * below this pdgain by a number of pwr_steps */
2649 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2650 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2651 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2652 pdadc_0++;
2653 }
2654
2655 /* Set last pwr level, using gain boundaries */
2656 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2657 /* Limit it to be inside pwr range */
2658 table_size = pwr_max[pdg] - pwr_min[pdg];
2659 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2660
2661 /* Fill pdadc_out table */
Bob Copeland4f59fce2010-04-07 23:55:59 -04002662 while (pdadc_0 < max_idx && pdadc_i < 128)
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002663 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2664
2665 /* Need to extrapolate above this pdgain? */
2666 if (pdadc_n <= max_idx)
2667 continue;
2668
2669 /* Force each power step to be at least 0.5 dB */
2670 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2671 pwr_step = pdadc_tmp[table_size - 1] -
2672 pdadc_tmp[table_size - 2];
2673 else
2674 pwr_step = 1;
2675
2676 /* Extrapolate above */
2677 while ((pdadc_0 < (s16) pdadc_n) &&
2678 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2679 s16 tmp = pdadc_tmp[table_size - 1] +
2680 (pdadc_0 - max_idx) * pwr_step;
2681 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2682 pdadc_0++;
2683 }
2684 }
2685
2686 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2687 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2688 pdg++;
2689 }
2690
2691 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2692 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2693 pdadc_i++;
2694 }
2695
2696 /* Set gain boundaries */
2697 ath5k_hw_reg_write(ah,
2698 AR5K_REG_SM(pd_gain_overlap,
2699 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2700 AR5K_REG_SM(gain_boundaries[0],
2701 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2702 AR5K_REG_SM(gain_boundaries[1],
2703 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2704 AR5K_REG_SM(gain_boundaries[2],
2705 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2706 AR5K_REG_SM(gain_boundaries[3],
2707 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2708 AR5K_PHY_TPC_RG5);
2709
2710 /* Used for setting rate power table */
2711 ah->ah_txpower.txp_min_idx = pwr_min[0];
2712
2713}
2714
2715/* Write PDADC values on hw */
2716static void
Bruno Randolf56bd29d2010-12-21 17:30:26 +09002717ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002718{
Nick Kossifidisd84938c2010-12-03 06:03:00 +02002719 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002720 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
Nick Kossifidisd84938c2010-12-03 06:03:00 +02002721 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
2722 u8 pdcurves = ee->ee_pd_gains[ee_mode];
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002723 u32 reg;
2724 u8 i;
2725
2726 /* Select the right pdgain curves */
2727
2728 /* Clear current settings */
2729 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2730 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2731 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2732 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2733 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2734
2735 /*
2736 * Use pd_gains curve from eeprom
2737 *
2738 * This overrides the default setting from initvals
2739 * in case some vendors (e.g. Zcomax) don't use the default
2740 * curves. If we don't honor their settings we 'll get a
2741 * 5dB (1 * gain overlap ?) drop.
2742 */
2743 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2744
2745 switch (pdcurves) {
2746 case 3:
2747 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2748 /* Fall through */
2749 case 2:
2750 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2751 /* Fall through */
2752 case 1:
2753 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2754 break;
2755 }
2756 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2757
2758 /*
2759 * Write TX power values
2760 */
2761 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2762 ath5k_hw_reg_write(ah,
2763 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2764 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2765 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2766 ((pdadc_out[4*i + 3] & 0xff) << 24),
2767 AR5K_PHY_PDADC_TXPOWER(i));
2768 }
2769}
2770
2771
2772/*
2773 * Common code for PCDAC/PDADC tables
2774 */
2775
2776/*
2777 * This is the main function that uses all of the above
2778 * to set PCDAC/PDADC table on hw for the current channel.
2779 * This table is used for tx power calibration on the basband,
2780 * without it we get weird tx power levels and in some cases
2781 * distorted spectral mask
2782 */
2783static int
2784ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2785 struct ieee80211_channel *channel,
2786 u8 ee_mode, u8 type)
2787{
2788 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2789 struct ath5k_chan_pcal_info *pcinfo_L;
2790 struct ath5k_chan_pcal_info *pcinfo_R;
2791 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2792 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2793 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2794 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2795 u8 *tmpL;
2796 u8 *tmpR;
2797 u32 target = channel->center_freq;
2798 int pdg, i;
2799
2800 /* Get surounding freq piers for this channel */
2801 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2802 &pcinfo_L,
2803 &pcinfo_R);
2804
2805 /* Loop over pd gain curves on
2806 * surounding freq piers by index */
2807 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2808
2809 /* Fill curves in reverse order
2810 * from lower power (max gain)
2811 * to higher power. Use curve -> idx
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02002812 * backmapping we did on eeprom init */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002813 u8 idx = pdg_curve_to_idx[pdg];
2814
2815 /* Grab the needed curves by index */
2816 pdg_L = &pcinfo_L->pd_curves[idx];
2817 pdg_R = &pcinfo_R->pd_curves[idx];
2818
2819 /* Initialize the temp tables */
2820 tmpL = ah->ah_txpower.tmpL[pdg];
2821 tmpR = ah->ah_txpower.tmpR[pdg];
2822
2823 /* Set curve's x boundaries and create
2824 * curves so that they cover the same
2825 * range (if we don't do that one table
2826 * will have values on some range and the
2827 * other one won't have any so interpolation
2828 * will fail) */
2829 table_min[pdg] = min(pdg_L->pd_pwr[0],
2830 pdg_R->pd_pwr[0]) / 2;
2831
2832 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2833 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2834
2835 /* Now create the curves on surrounding channels
2836 * and interpolate if needed to get the final
2837 * curve for this gain on this channel */
2838 switch (type) {
2839 case AR5K_PWRTABLE_LINEAR_PCDAC:
2840 /* Override min/max so that we don't loose
2841 * accuracy (don't divide by 2) */
2842 table_min[pdg] = min(pdg_L->pd_pwr[0],
2843 pdg_R->pd_pwr[0]);
2844
2845 table_max[pdg] =
2846 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2847 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2848
2849 /* Override minimum so that we don't get
2850 * out of bounds while extrapolating
2851 * below. Don't do this when we have 2
2852 * curves and we are on the high power curve
2853 * because table_min is ok in this case */
2854 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2855
2856 table_min[pdg] =
2857 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2858 pdg_R->pd_step,
2859 pdg_L->pd_pwr,
2860 pdg_R->pd_pwr);
2861
2862 /* Don't go too low because we will
2863 * miss the upper part of the curve.
2864 * Note: 126 = 31.5dB (max power supported)
2865 * in 0.25dB units */
2866 if (table_max[pdg] - table_min[pdg] > 126)
2867 table_min[pdg] = table_max[pdg] - 126;
2868 }
2869
2870 /* Fall through */
2871 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2872 case AR5K_PWRTABLE_PWR_TO_PDADC:
2873
2874 ath5k_create_power_curve(table_min[pdg],
2875 table_max[pdg],
2876 pdg_L->pd_pwr,
2877 pdg_L->pd_step,
2878 pdg_L->pd_points, tmpL, type);
2879
2880 /* We are in a calibration
2881 * pier, no need to interpolate
2882 * between freq piers */
2883 if (pcinfo_L == pcinfo_R)
2884 continue;
2885
2886 ath5k_create_power_curve(table_min[pdg],
2887 table_max[pdg],
2888 pdg_R->pd_pwr,
2889 pdg_R->pd_step,
2890 pdg_R->pd_points, tmpR, type);
2891 break;
2892 default:
2893 return -EINVAL;
2894 }
2895
2896 /* Interpolate between curves
2897 * of surounding freq piers to
2898 * get the final curve for this
2899 * pd gain. Re-use tmpL for interpolation
2900 * output */
2901 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2902 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2903 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2904 (s16) pcinfo_L->freq,
2905 (s16) pcinfo_R->freq,
2906 (s16) tmpL[i],
2907 (s16) tmpR[i]);
2908 }
2909 }
2910
2911 /* Now we have a set of curves for this
2912 * channel on tmpL (x range is table_max - table_min
2913 * and y values are tmpL[pdg][]) sorted in the same
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02002914 * order as EEPROM (because we've used the backmapping).
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002915 * So for RF5112 it's from higher power to lower power
2916 * and for RF2413 it's from lower power to higher power.
2917 * For RF5111 we only have one curve. */
2918
2919 /* Fill min and max power levels for this
2920 * channel by interpolating the values on
2921 * surounding channels to complete the dataset */
2922 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2923 (s16) pcinfo_L->freq,
2924 (s16) pcinfo_R->freq,
2925 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2926
2927 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2928 (s16) pcinfo_L->freq,
2929 (s16) pcinfo_R->freq,
2930 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2931
Bruno Randolf56bd29d2010-12-21 17:30:26 +09002932 /* Fill PCDAC/PDADC table */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002933 switch (type) {
2934 case AR5K_PWRTABLE_LINEAR_PCDAC:
2935 /* For RF5112 we can have one or two curves
2936 * and each curve covers a certain power lvl
2937 * range so we need to do some more processing */
2938 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2939 ee->ee_pd_gains[ee_mode]);
2940
2941 /* Set txp.offset so that we can
2942 * match max power value with max
2943 * table index */
2944 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002945 break;
2946 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2947 /* We are done for RF5111 since it has only
2948 * one curve, just fit the curve on the table */
2949 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2950
2951 /* No rate powertable adjustment for RF5111 */
2952 ah->ah_txpower.txp_min_idx = 0;
2953 ah->ah_txpower.txp_offset = 0;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002954 break;
2955 case AR5K_PWRTABLE_PWR_TO_PDADC:
2956 /* Set PDADC boundaries and fill
2957 * final PDADC table */
2958 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2959 ee->ee_pd_gains[ee_mode]);
2960
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002961 /* Set txp.offset, note that table_min
2962 * can be negative */
2963 ah->ah_txpower.txp_offset = table_min[0];
2964 break;
2965 default:
2966 return -EINVAL;
2967 }
2968
Bruno Randolf26c7fc42010-12-21 17:30:20 +09002969 ah->ah_txpower.txp_setup = true;
2970
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002971 return 0;
2972}
2973
Bruno Randolf56bd29d2010-12-21 17:30:26 +09002974/* Write power table for current channel to hw */
2975static void
2976ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
2977{
2978 if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
2979 ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
2980 else
2981 ath5k_write_pcdac_table(ah);
2982}
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002983
2984/*
2985 * Per-rate tx power setting
2986 *
2987 * This is the code that sets the desired tx power (below
2988 * maximum) on hw for each rate (we also have TPC that sets
2989 * power per packet). We do that by providing an index on the
2990 * PCDAC/PDADC table we set up.
2991 */
2992
2993/*
2994 * Set rate power table
2995 *
2996 * For now we only limit txpower based on maximum tx power
2997 * supported by hw (what's inside rate_info). We need to limit
2998 * this even more, based on regulatory domain etc.
2999 *
3000 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3001 * and is indexed as follows:
3002 * rates[0] - rates[7] -> OFDM rates
3003 * rates[8] - rates[14] -> CCK rates
3004 * rates[15] -> XR rates (they all have the same power)
3005 */
3006static void
3007ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3008 struct ath5k_rate_pcal_info *rate_info,
3009 u8 ee_mode)
3010{
3011 unsigned int i;
3012 u16 *rates;
3013
3014 /* max_pwr is power level we got from driver/user in 0.5dB
3015 * units, switch to 0.25dB units so we can compare */
3016 max_pwr *= 2;
3017 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3018
3019 /* apply rate limits */
3020 rates = ah->ah_txpower.txp_rates_power_table;
3021
3022 /* OFDM rates 6 to 24Mb/s */
3023 for (i = 0; i < 5; i++)
3024 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3025
3026 /* Rest OFDM rates */
3027 rates[5] = min(rates[0], rate_info->target_power_36);
3028 rates[6] = min(rates[0], rate_info->target_power_48);
3029 rates[7] = min(rates[0], rate_info->target_power_54);
3030
3031 /* CCK rates */
3032 /* 1L */
3033 rates[8] = min(rates[0], rate_info->target_power_6to24);
3034 /* 2L */
3035 rates[9] = min(rates[0], rate_info->target_power_36);
3036 /* 2S */
3037 rates[10] = min(rates[0], rate_info->target_power_36);
3038 /* 5L */
3039 rates[11] = min(rates[0], rate_info->target_power_48);
3040 /* 5S */
3041 rates[12] = min(rates[0], rate_info->target_power_48);
3042 /* 11L */
3043 rates[13] = min(rates[0], rate_info->target_power_54);
3044 /* 11S */
3045 rates[14] = min(rates[0], rate_info->target_power_54);
3046
3047 /* XR rates */
3048 rates[15] = min(rates[0], rate_info->target_power_6to24);
3049
3050 /* CCK rates have different peak to average ratio
3051 * so we have to tweak their power so that gainf
3052 * correction works ok. For this we use OFDM to
3053 * CCK delta from eeprom */
3054 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3055 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3056 for (i = 8; i <= 15; i++)
3057 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3058
Nick Kossifidisa0823812009-04-30 15:55:44 -04003059 /* Now that we have all rates setup use table offset to
3060 * match the power range set by user with the power indices
3061 * on PCDAC/PDADC table */
3062 for (i = 0; i < 16; i++) {
3063 rates[i] += ah->ah_txpower.txp_offset;
3064 /* Don't get out of bounds */
3065 if (rates[i] > 63)
3066 rates[i] = 63;
3067 }
3068
3069 /* Min/max in 0.25dB units */
3070 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
Bruno Randolf51f00622010-12-21 17:30:32 +09003071 ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003072 ah->ah_txpower.txp_ofdm = rates[7];
3073}
3074
3075
3076/*
Bob Copeland8801df82010-08-21 16:39:02 -04003077 * Set transmission power
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003078 */
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003079static int
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003080ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
Bruno Randolf0207c0c2010-12-21 17:30:43 +09003081 u8 txpower)
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003082{
3083 struct ath5k_rate_pcal_info rate_info;
Bruno Randolf26c7fc42010-12-21 17:30:20 +09003084 struct ieee80211_channel *curr_channel = ah->ah_current_channel;
Dan Carpentera8851d12011-01-03 08:46:29 +03003085 int ee_mode;
3086 u8 type;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003087 int ret;
3088
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003089 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3090 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3091 return -EINVAL;
3092 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003093
Bruno Randolf0207c0c2010-12-21 17:30:43 +09003094 ee_mode = ath5k_eeprom_mode_from_channel(channel);
3095 if (ee_mode < 0) {
3096 ATH5K_ERR(ah->ah_sc,
3097 "invalid channel: %d\n", channel->center_freq);
3098 return -EINVAL;
3099 }
3100
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003101 /* Initialize TX power table */
3102 switch (ah->ah_radio) {
Nick Kossifidis3bb17652010-11-23 21:45:21 +02003103 case AR5K_RF5110:
3104 /* TODO */
3105 return 0;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003106 case AR5K_RF5111:
3107 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3108 break;
3109 case AR5K_RF5112:
3110 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3111 break;
3112 case AR5K_RF2413:
3113 case AR5K_RF5413:
3114 case AR5K_RF2316:
3115 case AR5K_RF2317:
3116 case AR5K_RF2425:
3117 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3118 break;
3119 default:
3120 return -EINVAL;
3121 }
3122
Bruno Randolf26c7fc42010-12-21 17:30:20 +09003123 /*
3124 * If we don't change channel/mode skip tx powertable calculation
3125 * and use the cached one.
3126 */
3127 if (!ah->ah_txpower.txp_setup ||
3128 (channel->hw_value != curr_channel->hw_value) ||
3129 (channel->center_freq != curr_channel->center_freq)) {
Nick Kossifidisd84938c2010-12-03 06:03:00 +02003130 /* Reset TX power values */
3131 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3132 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
Nick Kossifidisd84938c2010-12-03 06:03:00 +02003133
3134 /* Calculate the powertable */
Nick Kossifidis4c575812010-11-23 21:37:30 +02003135 ret = ath5k_setup_channel_powertable(ah, channel,
3136 ee_mode, type);
Nick Kossifidisd84938c2010-12-03 06:03:00 +02003137 if (ret)
3138 return ret;
Bruno Randolf56bd29d2010-12-21 17:30:26 +09003139 }
3140
3141 /* Write table on hw */
3142 ath5k_write_channel_powertable(ah, ee_mode, type);
Nick Kossifidisd84938c2010-12-03 06:03:00 +02003143
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003144 /* Limit max power if we have a CTL available */
3145 ath5k_get_max_ctl_power(ah, channel);
3146
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003147 /* FIXME: Antenna reduction stuff */
3148
3149 /* FIXME: Limit power on turbo modes */
3150
3151 /* FIXME: TPC scale reduction */
3152
3153 /* Get surounding channels for per-rate power table
3154 * calibration */
3155 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3156
3157 /* Setup rate power table */
3158 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3159
3160 /* Write rate power table on hw */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003161 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3162 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3163 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3164
3165 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3166 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3167 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3168
3169 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3170 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3171 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3172
3173 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3174 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3175 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3176
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003177 /* FIXME: TPC support */
3178 if (ah->ah_txpower.txp_tpc) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003179 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3180 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003181
3182 ath5k_hw_reg_write(ah,
3183 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3184 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3185 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3186 AR5K_TPC);
3187 } else {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003188 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3189 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003190 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003191
3192 return 0;
3193}
3194
Nick Kossifidisa0823812009-04-30 15:55:44 -04003195int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003196{
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003197 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02003198 "changing txpower to %d\n", txpower);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003199
Bruno Randolf0207c0c2010-12-21 17:30:43 +09003200 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003201}
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003202
3203/*************\
3204 Init function
3205\*************/
3206
3207int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
Bruno Randolf0207c0c2010-12-21 17:30:43 +09003208 u8 mode, bool fast)
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003209{
Nick Kossifidis4c575812010-11-23 21:37:30 +02003210 struct ieee80211_channel *curr_channel;
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003211 int ret, i;
3212 u32 phy_tst1;
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003213 ret = 0;
3214
3215 /*
Nick Kossifidis8aec7af2010-11-23 21:39:28 +02003216 * Sanity check for fast flag
3217 * Don't try fast channel change when changing modulation
3218 * mode/band. We check for chip compatibility on
3219 * ath5k_hw_reset.
3220 */
3221 curr_channel = ah->ah_current_channel;
3222 if (fast && (channel->hw_value != curr_channel->hw_value))
3223 return -EINVAL;
3224
3225 /*
3226 * On fast channel change we only set the synth parameters
3227 * while PHY is running, enable calibration and skip the rest.
3228 */
3229 if (fast) {
3230 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3231 AR5K_PHY_RFBUS_REQ_REQUEST);
3232 for (i = 0; i < 100; i++) {
3233 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3234 break;
3235 udelay(5);
3236 }
3237 /* Failed */
3238 if (i >= 100)
3239 return -EIO;
3240 }
3241
3242 /*
Nick Kossifidis4c575812010-11-23 21:37:30 +02003243 * Set TX power
3244 *
3245 * Note: We need to do that before we set
3246 * RF buffer settings on 5211/5212+ so that we
3247 * properly set curve indices.
3248 */
Bruno Randolf0207c0c2010-12-21 17:30:43 +09003249 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
Bruno Randolf51f00622010-12-21 17:30:32 +09003250 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
Nick Kossifidis4c575812010-11-23 21:37:30 +02003251 if (ret)
3252 return ret;
3253
3254 /*
3255 * For 5210 we do all initialization using
3256 * initvals, so we don't have to modify
3257 * any settings (5210 also only supports
3258 * a/aturbo modes)
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003259 */
Nick Kossifidis8aec7af2010-11-23 21:39:28 +02003260 if ((ah->ah_version != AR5K_AR5210) && !fast) {
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003261
3262 /*
3263 * Write initial RF gain settings
3264 * This should work for both 5111/5112
3265 */
Bruno Randolf26a51ad2010-12-21 17:30:37 +09003266 ret = ath5k_hw_rfgain_init(ah, channel->band);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003267 if (ret)
3268 return ret;
3269
3270 mdelay(1);
3271
3272 /*
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003273 * Write RF buffer
3274 */
3275 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3276 if (ret)
3277 return ret;
3278
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003279 /* Write OFDM timings on 5212*/
3280 if (ah->ah_version == AR5K_AR5212 &&
3281 channel->hw_value & CHANNEL_OFDM) {
3282
3283 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3284 if (ret)
3285 return ret;
3286
3287 /* Spur info is available only from EEPROM versions
3288 * greater than 5.3, but the EEPROM routines will use
3289 * static values for older versions */
3290 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3291 ath5k_hw_set_spur_mitigation_filter(ah,
3292 channel);
3293 }
3294
3295 /*Enable/disable 802.11b mode on 5111
3296 (enable 2111 frequency converter + CCK)*/
3297 if (ah->ah_radio == AR5K_RF5111) {
3298 if (mode == AR5K_MODE_11B)
3299 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3300 AR5K_TXCFG_B_MODE);
3301 else
3302 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3303 AR5K_TXCFG_B_MODE);
3304 }
3305
Nick Kossifidis8aec7af2010-11-23 21:39:28 +02003306 } else if (ah->ah_version == AR5K_AR5210) {
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003307 mdelay(1);
3308 /* Disable phy and wait */
3309 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3310 mdelay(1);
3311 }
3312
3313 /* Set channel on PHY */
3314 ret = ath5k_hw_channel(ah, channel);
3315 if (ret)
3316 return ret;
3317
3318 /*
3319 * Enable the PHY and wait until completion
3320 * This includes BaseBand and Synthesizer
3321 * activation.
3322 */
3323 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3324
3325 /*
3326 * On 5211+ read activation -> rx delay
3327 * and use it.
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003328 */
3329 if (ah->ah_version != AR5K_AR5210) {
3330 u32 delay;
3331 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
3332 AR5K_PHY_RX_DELAY_M;
3333 delay = (channel->hw_value & CHANNEL_CCK) ?
3334 ((delay << 2) / 22) : (delay / 10);
Nick Kossifidisb02f5d12010-11-23 21:44:02 +02003335 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
3336 delay = delay << 1;
3337 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
3338 delay = delay << 2;
3339 /* XXX: /2 on turbo ? Let's be safe
3340 * for now */
3341 udelay(100 + delay);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003342 } else {
3343 mdelay(1);
3344 }
3345
Nick Kossifidis8aec7af2010-11-23 21:39:28 +02003346 if (fast)
3347 /*
3348 * Release RF Bus grant
3349 */
3350 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3351 AR5K_PHY_RFBUS_REQ_REQUEST);
3352 else {
3353 /*
3354 * Perform ADC test to see if baseband is ready
3355 * Set tx hold and check adc test register
3356 */
3357 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3358 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3359 for (i = 0; i <= 20; i++) {
3360 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3361 break;
3362 udelay(200);
3363 }
3364 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003365 }
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02003366
3367 /*
3368 * Start automatic gain control calibration
3369 *
3370 * During AGC calibration RX path is re-routed to
3371 * a power detector so we don't receive anything.
3372 *
3373 * This method is used to calibrate some static offsets
3374 * used together with on-the fly I/Q calibration (the
3375 * one performed via ath5k_hw_phy_calibrate), which doesn't
3376 * interrupt rx path.
3377 *
3378 * While rx path is re-routed to the power detector we also
3379 * start a noise floor calibration to measure the
3380 * card's noise floor (the noise we measure when we are not
3381 * transmitting or receiving anything).
3382 *
3383 * If we are in a noisy environment, AGC calibration may time
3384 * out and/or noise floor calibration might timeout.
3385 */
3386 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3387 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3388
3389 /* At the same time start I/Q calibration for QAM constellation
3390 * -no need for CCK- */
3391 ah->ah_calibration = false;
3392 if (!(mode == AR5K_MODE_11B)) {
3393 ah->ah_calibration = true;
3394 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3395 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3396 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3397 AR5K_PHY_IQ_RUN);
3398 }
3399
3400 /* Wait for gain calibration to finish (we check for I/Q calibration
3401 * during ath5k_phy_calibrate) */
3402 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3403 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3404 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
3405 channel->center_freq);
3406 }
3407
3408 /* Restore antenna mode */
3409 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3410
3411 return ret;
3412}