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Dong Aishenge0d1f482014-07-16 17:30:50 +08001/*
2 * CAN bus driver for Bosch M_CAN controller
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Dong Aisheng <b29396@freescale.com>
6 *
7 * Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/netdevice.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26
27#include <linux/can/dev.h>
28
29/* napi related */
30#define M_CAN_NAPI_WEIGHT 64
31
32/* message ram configuration data length */
33#define MRAM_CFG_LEN 8
34
35/* registers definition */
36enum m_can_reg {
37 M_CAN_CREL = 0x0,
38 M_CAN_ENDN = 0x4,
39 M_CAN_CUST = 0x8,
40 M_CAN_FBTP = 0xc,
41 M_CAN_TEST = 0x10,
42 M_CAN_RWD = 0x14,
43 M_CAN_CCCR = 0x18,
44 M_CAN_BTP = 0x1c,
45 M_CAN_TSCC = 0x20,
46 M_CAN_TSCV = 0x24,
47 M_CAN_TOCC = 0x28,
48 M_CAN_TOCV = 0x2c,
49 M_CAN_ECR = 0x40,
50 M_CAN_PSR = 0x44,
51 M_CAN_IR = 0x50,
52 M_CAN_IE = 0x54,
53 M_CAN_ILS = 0x58,
54 M_CAN_ILE = 0x5c,
55 M_CAN_GFC = 0x80,
56 M_CAN_SIDFC = 0x84,
57 M_CAN_XIDFC = 0x88,
58 M_CAN_XIDAM = 0x90,
59 M_CAN_HPMS = 0x94,
60 M_CAN_NDAT1 = 0x98,
61 M_CAN_NDAT2 = 0x9c,
62 M_CAN_RXF0C = 0xa0,
63 M_CAN_RXF0S = 0xa4,
64 M_CAN_RXF0A = 0xa8,
65 M_CAN_RXBC = 0xac,
66 M_CAN_RXF1C = 0xb0,
67 M_CAN_RXF1S = 0xb4,
68 M_CAN_RXF1A = 0xb8,
69 M_CAN_RXESC = 0xbc,
70 M_CAN_TXBC = 0xc0,
71 M_CAN_TXFQS = 0xc4,
72 M_CAN_TXESC = 0xc8,
73 M_CAN_TXBRP = 0xcc,
74 M_CAN_TXBAR = 0xd0,
75 M_CAN_TXBCR = 0xd4,
76 M_CAN_TXBTO = 0xd8,
77 M_CAN_TXBCF = 0xdc,
78 M_CAN_TXBTIE = 0xe0,
79 M_CAN_TXBCIE = 0xe4,
80 M_CAN_TXEFC = 0xf0,
81 M_CAN_TXEFS = 0xf4,
82 M_CAN_TXEFA = 0xf8,
83};
84
85/* m_can lec values */
86enum m_can_lec_type {
87 LEC_NO_ERROR = 0,
88 LEC_STUFF_ERROR,
89 LEC_FORM_ERROR,
90 LEC_ACK_ERROR,
91 LEC_BIT1_ERROR,
92 LEC_BIT0_ERROR,
93 LEC_CRC_ERROR,
94 LEC_UNUSED,
95};
96
97enum m_can_mram_cfg {
98 MRAM_SIDF = 0,
99 MRAM_XIDF,
100 MRAM_RXF0,
101 MRAM_RXF1,
102 MRAM_RXB,
103 MRAM_TXE,
104 MRAM_TXB,
105 MRAM_CFG_NUM,
106};
107
108/* Test Register (TEST) */
109#define TEST_LBCK BIT(4)
110
111/* CC Control Register(CCCR) */
112#define CCCR_TEST BIT(7)
113#define CCCR_MON BIT(5)
114#define CCCR_CCE BIT(1)
115#define CCCR_INIT BIT(0)
116
117/* Bit Timing & Prescaler Register (BTP) */
118#define BTR_BRP_MASK 0x3ff
119#define BTR_BRP_SHIFT 16
120#define BTR_TSEG1_SHIFT 8
121#define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
122#define BTR_TSEG2_SHIFT 4
123#define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
124#define BTR_SJW_SHIFT 0
125#define BTR_SJW_MASK 0xf
126
127/* Error Counter Register(ECR) */
128#define ECR_RP BIT(15)
129#define ECR_REC_SHIFT 8
130#define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
131#define ECR_TEC_SHIFT 0
132#define ECR_TEC_MASK 0xff
133
134/* Protocol Status Register(PSR) */
135#define PSR_BO BIT(7)
136#define PSR_EW BIT(6)
137#define PSR_EP BIT(5)
138#define PSR_LEC_MASK 0x7
139
140/* Interrupt Register(IR) */
141#define IR_ALL_INT 0xffffffff
142#define IR_STE BIT(31)
143#define IR_FOE BIT(30)
144#define IR_ACKE BIT(29)
145#define IR_BE BIT(28)
146#define IR_CRCE BIT(27)
147#define IR_WDI BIT(26)
148#define IR_BO BIT(25)
149#define IR_EW BIT(24)
150#define IR_EP BIT(23)
151#define IR_ELO BIT(22)
152#define IR_BEU BIT(21)
153#define IR_BEC BIT(20)
154#define IR_DRX BIT(19)
155#define IR_TOO BIT(18)
156#define IR_MRAF BIT(17)
157#define IR_TSW BIT(16)
158#define IR_TEFL BIT(15)
159#define IR_TEFF BIT(14)
160#define IR_TEFW BIT(13)
161#define IR_TEFN BIT(12)
162#define IR_TFE BIT(11)
163#define IR_TCF BIT(10)
164#define IR_TC BIT(9)
165#define IR_HPM BIT(8)
166#define IR_RF1L BIT(7)
167#define IR_RF1F BIT(6)
168#define IR_RF1W BIT(5)
169#define IR_RF1N BIT(4)
170#define IR_RF0L BIT(3)
171#define IR_RF0F BIT(2)
172#define IR_RF0W BIT(1)
173#define IR_RF0N BIT(0)
174#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
175#define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
176#define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
177 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
178 IR_RF1L | IR_RF0L)
179#define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
180
181/* Interrupt Line Select (ILS) */
182#define ILS_ALL_INT0 0x0
183#define ILS_ALL_INT1 0xFFFFFFFF
184
185/* Interrupt Line Enable (ILE) */
186#define ILE_EINT0 BIT(0)
187#define ILE_EINT1 BIT(1)
188
189/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
190#define RXFC_FWM_OFF 24
191#define RXFC_FWM_MASK 0x7f
192#define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
193#define RXFC_FS_OFF 16
194#define RXFC_FS_MASK 0x7f
195
196/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
197#define RXFS_RFL BIT(25)
198#define RXFS_FF BIT(24)
199#define RXFS_FPI_OFF 16
200#define RXFS_FPI_MASK 0x3f0000
201#define RXFS_FGI_OFF 8
202#define RXFS_FGI_MASK 0x3f00
203#define RXFS_FFL_MASK 0x7f
204
205/* Rx Buffer / FIFO Element Size Configuration (RXESC) */
206#define M_CAN_RXESC_8BYTES 0x0
207
208/* Tx Buffer Configuration(TXBC) */
209#define TXBC_NDTB_OFF 16
210#define TXBC_NDTB_MASK 0x3f
211
212/* Tx Buffer Element Size Configuration(TXESC) */
213#define TXESC_TBDS_8BYTES 0x0
214
215/* Tx Event FIFO Con.guration (TXEFC) */
216#define TXEFC_EFS_OFF 16
217#define TXEFC_EFS_MASK 0x3f
218
219/* Message RAM Configuration (in bytes) */
220#define SIDF_ELEMENT_SIZE 4
221#define XIDF_ELEMENT_SIZE 8
222#define RXF0_ELEMENT_SIZE 16
223#define RXF1_ELEMENT_SIZE 16
224#define RXB_ELEMENT_SIZE 16
225#define TXE_ELEMENT_SIZE 8
226#define TXB_ELEMENT_SIZE 16
227
228/* Message RAM Elements */
229#define M_CAN_FIFO_ID 0x0
230#define M_CAN_FIFO_DLC 0x4
231#define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
232
233/* Rx Buffer Element */
234#define RX_BUF_ESI BIT(31)
235#define RX_BUF_XTD BIT(30)
236#define RX_BUF_RTR BIT(29)
237
238/* Tx Buffer Element */
239#define TX_BUF_XTD BIT(30)
240#define TX_BUF_RTR BIT(29)
241
242/* address offset and element number for each FIFO/Buffer in the Message RAM */
243struct mram_cfg {
244 u16 off;
245 u8 num;
246};
247
248/* m_can private data structure */
249struct m_can_priv {
250 struct can_priv can; /* must be the first member */
251 struct napi_struct napi;
252 struct net_device *dev;
253 struct device *device;
254 struct clk *hclk;
255 struct clk *cclk;
256 void __iomem *base;
257 u32 irqstatus;
258
259 /* message ram configuration */
260 void __iomem *mram_base;
261 struct mram_cfg mcfg[MRAM_CFG_NUM];
262};
263
264static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
265{
266 return readl(priv->base + reg);
267}
268
269static inline void m_can_write(const struct m_can_priv *priv,
270 enum m_can_reg reg, u32 val)
271{
272 writel(val, priv->base + reg);
273}
274
275static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
276 u32 fgi, unsigned int offset)
277{
278 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
279 fgi * RXF0_ELEMENT_SIZE + offset);
280}
281
282static inline void m_can_fifo_write(const struct m_can_priv *priv,
283 u32 fpi, unsigned int offset, u32 val)
284{
285 return writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
286 fpi * TXB_ELEMENT_SIZE + offset);
287}
288
289static inline void m_can_config_endisable(const struct m_can_priv *priv,
290 bool enable)
291{
292 u32 cccr = m_can_read(priv, M_CAN_CCCR);
293 u32 timeout = 10;
294 u32 val = 0;
295
296 if (enable) {
297 /* enable m_can configuration */
298 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
Dong Aisheng7660f632014-10-29 18:45:24 +0800299 udelay(5);
Dong Aishenge0d1f482014-07-16 17:30:50 +0800300 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
301 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
302 } else {
303 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
304 }
305
306 /* there's a delay for module initialization */
307 if (enable)
308 val = CCCR_INIT | CCCR_CCE;
309
310 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
311 if (timeout == 0) {
312 netdev_warn(priv->dev, "Failed to init module\n");
313 return;
314 }
315 timeout--;
316 udelay(1);
317 }
318}
319
320static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
321{
322 m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
323}
324
325static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
326{
327 m_can_write(priv, M_CAN_ILE, 0x0);
328}
329
330static void m_can_read_fifo(const struct net_device *dev, struct can_frame *cf,
331 u32 rxfs)
332{
333 struct m_can_priv *priv = netdev_priv(dev);
Dong Aisheng921f1682014-11-18 19:00:54 +0800334 u32 id, fgi, dlc;
Dong Aishenge0d1f482014-07-16 17:30:50 +0800335
336 /* calculate the fifo get index for where to read data */
337 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
338 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
339 if (id & RX_BUF_XTD)
340 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
341 else
342 cf->can_id = (id >> 18) & CAN_SFF_MASK;
343
Dong Aisheng921f1682014-11-18 19:00:54 +0800344 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
345 cf->can_dlc = get_can_dlc((dlc >> 16) & 0x0F);
346
Dong Aishenge0d1f482014-07-16 17:30:50 +0800347 if (id & RX_BUF_RTR) {
348 cf->can_id |= CAN_RTR_FLAG;
349 } else {
Dong Aishenge0d1f482014-07-16 17:30:50 +0800350 *(u32 *)(cf->data + 0) = m_can_fifo_read(priv, fgi,
351 M_CAN_FIFO_DATA(0));
352 *(u32 *)(cf->data + 4) = m_can_fifo_read(priv, fgi,
353 M_CAN_FIFO_DATA(1));
354 }
355
356 /* acknowledge rx fifo 0 */
357 m_can_write(priv, M_CAN_RXF0A, fgi);
358}
359
360static int m_can_do_rx_poll(struct net_device *dev, int quota)
361{
362 struct m_can_priv *priv = netdev_priv(dev);
363 struct net_device_stats *stats = &dev->stats;
364 struct sk_buff *skb;
365 struct can_frame *frame;
366 u32 pkts = 0;
367 u32 rxfs;
368
369 rxfs = m_can_read(priv, M_CAN_RXF0S);
370 if (!(rxfs & RXFS_FFL_MASK)) {
371 netdev_dbg(dev, "no messages in fifo0\n");
372 return 0;
373 }
374
375 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
376 if (rxfs & RXFS_RFL)
377 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
378
379 skb = alloc_can_skb(dev, &frame);
380 if (!skb) {
381 stats->rx_dropped++;
382 return pkts;
383 }
384
385 m_can_read_fifo(dev, frame, rxfs);
386
387 stats->rx_packets++;
388 stats->rx_bytes += frame->can_dlc;
389
390 netif_receive_skb(skb);
391
392 quota--;
393 pkts++;
394 rxfs = m_can_read(priv, M_CAN_RXF0S);
395 }
396
397 if (pkts)
398 can_led_event(dev, CAN_LED_EVENT_RX);
399
400 return pkts;
401}
402
403static int m_can_handle_lost_msg(struct net_device *dev)
404{
405 struct net_device_stats *stats = &dev->stats;
406 struct sk_buff *skb;
407 struct can_frame *frame;
408
409 netdev_err(dev, "msg lost in rxf0\n");
410
411 stats->rx_errors++;
412 stats->rx_over_errors++;
413
414 skb = alloc_can_err_skb(dev, &frame);
415 if (unlikely(!skb))
416 return 0;
417
418 frame->can_id |= CAN_ERR_CRTL;
419 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
420
421 netif_receive_skb(skb);
422
423 return 1;
424}
425
426static int m_can_handle_lec_err(struct net_device *dev,
427 enum m_can_lec_type lec_type)
428{
429 struct m_can_priv *priv = netdev_priv(dev);
430 struct net_device_stats *stats = &dev->stats;
431 struct can_frame *cf;
432 struct sk_buff *skb;
433
434 priv->can.can_stats.bus_error++;
435 stats->rx_errors++;
436
437 /* propagate the error condition to the CAN stack */
438 skb = alloc_can_err_skb(dev, &cf);
439 if (unlikely(!skb))
440 return 0;
441
442 /* check for 'last error code' which tells us the
443 * type of the last error to occur on the CAN bus
444 */
445 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
446 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
447
448 switch (lec_type) {
449 case LEC_STUFF_ERROR:
450 netdev_dbg(dev, "stuff error\n");
451 cf->data[2] |= CAN_ERR_PROT_STUFF;
452 break;
453 case LEC_FORM_ERROR:
454 netdev_dbg(dev, "form error\n");
455 cf->data[2] |= CAN_ERR_PROT_FORM;
456 break;
457 case LEC_ACK_ERROR:
458 netdev_dbg(dev, "ack error\n");
459 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
460 CAN_ERR_PROT_LOC_ACK_DEL);
461 break;
462 case LEC_BIT1_ERROR:
463 netdev_dbg(dev, "bit1 error\n");
464 cf->data[2] |= CAN_ERR_PROT_BIT1;
465 break;
466 case LEC_BIT0_ERROR:
467 netdev_dbg(dev, "bit0 error\n");
468 cf->data[2] |= CAN_ERR_PROT_BIT0;
469 break;
470 case LEC_CRC_ERROR:
471 netdev_dbg(dev, "CRC error\n");
472 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
473 CAN_ERR_PROT_LOC_CRC_DEL);
474 break;
475 default:
476 break;
477 }
478
479 stats->rx_packets++;
480 stats->rx_bytes += cf->can_dlc;
481 netif_receive_skb(skb);
482
483 return 1;
484}
485
Dong Aishengf6a99642014-10-29 18:45:21 +0800486static int __m_can_get_berr_counter(const struct net_device *dev,
487 struct can_berr_counter *bec)
488{
489 struct m_can_priv *priv = netdev_priv(dev);
490 unsigned int ecr;
491
492 ecr = m_can_read(priv, M_CAN_ECR);
493 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
494 bec->txerr = ecr & ECR_TEC_MASK;
495
496 return 0;
497}
498
Dong Aishenge0d1f482014-07-16 17:30:50 +0800499static int m_can_get_berr_counter(const struct net_device *dev,
500 struct can_berr_counter *bec)
501{
502 struct m_can_priv *priv = netdev_priv(dev);
Dong Aishenge0d1f482014-07-16 17:30:50 +0800503 int err;
504
505 err = clk_prepare_enable(priv->hclk);
506 if (err)
507 return err;
508
509 err = clk_prepare_enable(priv->cclk);
510 if (err) {
511 clk_disable_unprepare(priv->hclk);
512 return err;
513 }
514
Dong Aishengf6a99642014-10-29 18:45:21 +0800515 __m_can_get_berr_counter(dev, bec);
Dong Aishenge0d1f482014-07-16 17:30:50 +0800516
517 clk_disable_unprepare(priv->cclk);
518 clk_disable_unprepare(priv->hclk);
519
520 return 0;
521}
522
523static int m_can_handle_state_change(struct net_device *dev,
524 enum can_state new_state)
525{
526 struct m_can_priv *priv = netdev_priv(dev);
527 struct net_device_stats *stats = &dev->stats;
528 struct can_frame *cf;
529 struct sk_buff *skb;
530 struct can_berr_counter bec;
531 unsigned int ecr;
532
533 switch (new_state) {
534 case CAN_STATE_ERROR_ACTIVE:
535 /* error warning state */
536 priv->can.can_stats.error_warning++;
537 priv->can.state = CAN_STATE_ERROR_WARNING;
538 break;
539 case CAN_STATE_ERROR_PASSIVE:
540 /* error passive state */
541 priv->can.can_stats.error_passive++;
542 priv->can.state = CAN_STATE_ERROR_PASSIVE;
543 break;
544 case CAN_STATE_BUS_OFF:
545 /* bus-off state */
546 priv->can.state = CAN_STATE_BUS_OFF;
547 m_can_disable_all_interrupts(priv);
548 can_bus_off(dev);
549 break;
550 default:
551 break;
552 }
553
554 /* propagate the error condition to the CAN stack */
555 skb = alloc_can_err_skb(dev, &cf);
556 if (unlikely(!skb))
557 return 0;
558
Dong Aishengf6a99642014-10-29 18:45:21 +0800559 __m_can_get_berr_counter(dev, &bec);
Dong Aishenge0d1f482014-07-16 17:30:50 +0800560
561 switch (new_state) {
562 case CAN_STATE_ERROR_ACTIVE:
563 /* error warning state */
564 cf->can_id |= CAN_ERR_CRTL;
565 cf->data[1] = (bec.txerr > bec.rxerr) ?
566 CAN_ERR_CRTL_TX_WARNING :
567 CAN_ERR_CRTL_RX_WARNING;
568 cf->data[6] = bec.txerr;
569 cf->data[7] = bec.rxerr;
570 break;
571 case CAN_STATE_ERROR_PASSIVE:
572 /* error passive state */
573 cf->can_id |= CAN_ERR_CRTL;
574 ecr = m_can_read(priv, M_CAN_ECR);
575 if (ecr & ECR_RP)
576 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
577 if (bec.txerr > 127)
578 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
579 cf->data[6] = bec.txerr;
580 cf->data[7] = bec.rxerr;
581 break;
582 case CAN_STATE_BUS_OFF:
583 /* bus-off state */
584 cf->can_id |= CAN_ERR_BUSOFF;
585 break;
586 default:
587 break;
588 }
589
590 stats->rx_packets++;
591 stats->rx_bytes += cf->can_dlc;
592 netif_receive_skb(skb);
593
594 return 1;
595}
596
597static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
598{
599 struct m_can_priv *priv = netdev_priv(dev);
600 int work_done = 0;
601
602 if ((psr & PSR_EW) &&
603 (priv->can.state != CAN_STATE_ERROR_WARNING)) {
604 netdev_dbg(dev, "entered error warning state\n");
605 work_done += m_can_handle_state_change(dev,
606 CAN_STATE_ERROR_WARNING);
607 }
608
609 if ((psr & PSR_EP) &&
610 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
611 netdev_dbg(dev, "entered error warning state\n");
612 work_done += m_can_handle_state_change(dev,
613 CAN_STATE_ERROR_PASSIVE);
614 }
615
616 if ((psr & PSR_BO) &&
617 (priv->can.state != CAN_STATE_BUS_OFF)) {
618 netdev_dbg(dev, "entered error warning state\n");
619 work_done += m_can_handle_state_change(dev,
620 CAN_STATE_BUS_OFF);
621 }
622
623 return work_done;
624}
625
626static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
627{
628 if (irqstatus & IR_WDI)
629 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
630 if (irqstatus & IR_BEU)
631 netdev_err(dev, "Error Logging Overflow\n");
632 if (irqstatus & IR_BEU)
633 netdev_err(dev, "Bit Error Uncorrected\n");
634 if (irqstatus & IR_BEC)
635 netdev_err(dev, "Bit Error Corrected\n");
636 if (irqstatus & IR_TOO)
637 netdev_err(dev, "Timeout reached\n");
638 if (irqstatus & IR_MRAF)
639 netdev_err(dev, "Message RAM access failure occurred\n");
640}
641
642static inline bool is_lec_err(u32 psr)
643{
644 psr &= LEC_UNUSED;
645
646 return psr && (psr != LEC_UNUSED);
647}
648
649static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
650 u32 psr)
651{
652 struct m_can_priv *priv = netdev_priv(dev);
653 int work_done = 0;
654
655 if (irqstatus & IR_RF0L)
656 work_done += m_can_handle_lost_msg(dev);
657
658 /* handle lec errors on the bus */
659 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
660 is_lec_err(psr))
661 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
662
663 /* other unproccessed error interrupts */
664 m_can_handle_other_err(dev, irqstatus);
665
666 return work_done;
667}
668
669static int m_can_poll(struct napi_struct *napi, int quota)
670{
671 struct net_device *dev = napi->dev;
672 struct m_can_priv *priv = netdev_priv(dev);
673 int work_done = 0;
674 u32 irqstatus, psr;
675
676 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
677 if (!irqstatus)
678 goto end;
679
680 psr = m_can_read(priv, M_CAN_PSR);
681 if (irqstatus & IR_ERR_STATE)
682 work_done += m_can_handle_state_errors(dev, psr);
683
684 if (irqstatus & IR_ERR_BUS)
685 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
686
687 if (irqstatus & IR_RF0N)
688 work_done += m_can_do_rx_poll(dev, (quota - work_done));
689
690 if (work_done < quota) {
691 napi_complete(napi);
692 m_can_enable_all_interrupts(priv);
693 }
694
695end:
696 return work_done;
697}
698
699static irqreturn_t m_can_isr(int irq, void *dev_id)
700{
701 struct net_device *dev = (struct net_device *)dev_id;
702 struct m_can_priv *priv = netdev_priv(dev);
703 struct net_device_stats *stats = &dev->stats;
704 u32 ir;
705
706 ir = m_can_read(priv, M_CAN_IR);
707 if (!ir)
708 return IRQ_NONE;
709
710 /* ACK all irqs */
711 if (ir & IR_ALL_INT)
712 m_can_write(priv, M_CAN_IR, ir);
713
714 /* schedule NAPI in case of
715 * - rx IRQ
716 * - state change IRQ
717 * - bus error IRQ and bus error reporting
718 */
719 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
720 priv->irqstatus = ir;
721 m_can_disable_all_interrupts(priv);
722 napi_schedule(&priv->napi);
723 }
724
725 /* transmission complete interrupt */
726 if (ir & IR_TC) {
727 stats->tx_bytes += can_get_echo_skb(dev, 0);
728 stats->tx_packets++;
729 can_led_event(dev, CAN_LED_EVENT_TX);
730 netif_wake_queue(dev);
731 }
732
733 return IRQ_HANDLED;
734}
735
736static const struct can_bittiming_const m_can_bittiming_const = {
737 .name = KBUILD_MODNAME,
738 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
739 .tseg1_max = 64,
740 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
741 .tseg2_max = 16,
742 .sjw_max = 16,
743 .brp_min = 1,
744 .brp_max = 1024,
745 .brp_inc = 1,
746};
747
748static int m_can_set_bittiming(struct net_device *dev)
749{
750 struct m_can_priv *priv = netdev_priv(dev);
751 const struct can_bittiming *bt = &priv->can.bittiming;
752 u16 brp, sjw, tseg1, tseg2;
753 u32 reg_btp;
754
755 brp = bt->brp - 1;
756 sjw = bt->sjw - 1;
757 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
758 tseg2 = bt->phase_seg2 - 1;
759 reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
760 (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
761 m_can_write(priv, M_CAN_BTP, reg_btp);
762 netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp);
763
764 return 0;
765}
766
767/* Configure M_CAN chip:
768 * - set rx buffer/fifo element size
769 * - configure rx fifo
770 * - accept non-matching frame into fifo 0
771 * - configure tx buffer
772 * - configure mode
773 * - setup bittiming
774 */
775static void m_can_chip_config(struct net_device *dev)
776{
777 struct m_can_priv *priv = netdev_priv(dev);
778 u32 cccr, test;
779
780 m_can_config_endisable(priv, true);
781
782 /* RX Buffer/FIFO Element Size 8 bytes data field */
783 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES);
784
785 /* Accept Non-matching Frames Into FIFO 0 */
786 m_can_write(priv, M_CAN_GFC, 0x0);
787
788 /* only support one Tx Buffer currently */
789 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
790 priv->mcfg[MRAM_TXB].off);
791
792 /* only support 8 bytes firstly */
793 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES);
794
795 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
796 priv->mcfg[MRAM_TXE].off);
797
798 /* rx fifo configuration, blocking mode, fifo size 1 */
799 m_can_write(priv, M_CAN_RXF0C,
800 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
801 RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
802
803 m_can_write(priv, M_CAN_RXF1C,
804 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
805 RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
806
807 cccr = m_can_read(priv, M_CAN_CCCR);
808 cccr &= ~(CCCR_TEST | CCCR_MON);
809 test = m_can_read(priv, M_CAN_TEST);
810 test &= ~TEST_LBCK;
811
812 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
813 cccr |= CCCR_MON;
814
815 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
816 cccr |= CCCR_TEST;
817 test |= TEST_LBCK;
818 }
819
820 m_can_write(priv, M_CAN_CCCR, cccr);
821 m_can_write(priv, M_CAN_TEST, test);
822
823 /* enable interrupts */
824 m_can_write(priv, M_CAN_IR, IR_ALL_INT);
825 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
826 m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
827 else
828 m_can_write(priv, M_CAN_IE, IR_ALL_INT);
829
830 /* route all interrupts to INT0 */
831 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
832
833 /* set bittiming params */
834 m_can_set_bittiming(dev);
835
836 m_can_config_endisable(priv, false);
837}
838
839static void m_can_start(struct net_device *dev)
840{
841 struct m_can_priv *priv = netdev_priv(dev);
842
843 /* basic m_can configuration */
844 m_can_chip_config(dev);
845
846 priv->can.state = CAN_STATE_ERROR_ACTIVE;
847
848 m_can_enable_all_interrupts(priv);
849}
850
851static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
852{
853 switch (mode) {
854 case CAN_MODE_START:
855 m_can_start(dev);
856 netif_wake_queue(dev);
857 break;
858 default:
859 return -EOPNOTSUPP;
860 }
861
862 return 0;
863}
864
865static void free_m_can_dev(struct net_device *dev)
866{
867 free_candev(dev);
868}
869
870static struct net_device *alloc_m_can_dev(void)
871{
872 struct net_device *dev;
873 struct m_can_priv *priv;
874
875 dev = alloc_candev(sizeof(*priv), 1);
876 if (!dev)
877 return NULL;
878
879 priv = netdev_priv(dev);
880 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
881
882 priv->dev = dev;
883 priv->can.bittiming_const = &m_can_bittiming_const;
884 priv->can.do_set_mode = m_can_set_mode;
885 priv->can.do_get_berr_counter = m_can_get_berr_counter;
886 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
887 CAN_CTRLMODE_LISTENONLY |
888 CAN_CTRLMODE_BERR_REPORTING;
889
890 return dev;
891}
892
893static int m_can_open(struct net_device *dev)
894{
895 struct m_can_priv *priv = netdev_priv(dev);
896 int err;
897
898 err = clk_prepare_enable(priv->hclk);
899 if (err)
900 return err;
901
902 err = clk_prepare_enable(priv->cclk);
903 if (err)
904 goto exit_disable_hclk;
905
906 /* open the can device */
907 err = open_candev(dev);
908 if (err) {
909 netdev_err(dev, "failed to open can device\n");
910 goto exit_disable_cclk;
911 }
912
913 /* register interrupt handler */
914 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
915 dev);
916 if (err < 0) {
917 netdev_err(dev, "failed to request interrupt\n");
918 goto exit_irq_fail;
919 }
920
921 /* start the m_can controller */
922 m_can_start(dev);
923
924 can_led_event(dev, CAN_LED_EVENT_OPEN);
925 napi_enable(&priv->napi);
926 netif_start_queue(dev);
927
928 return 0;
929
930exit_irq_fail:
931 close_candev(dev);
932exit_disable_cclk:
933 clk_disable_unprepare(priv->cclk);
934exit_disable_hclk:
935 clk_disable_unprepare(priv->hclk);
936 return err;
937}
938
939static void m_can_stop(struct net_device *dev)
940{
941 struct m_can_priv *priv = netdev_priv(dev);
942
943 /* disable all interrupts */
944 m_can_disable_all_interrupts(priv);
945
946 clk_disable_unprepare(priv->hclk);
947 clk_disable_unprepare(priv->cclk);
948
949 /* set the state as STOPPED */
950 priv->can.state = CAN_STATE_STOPPED;
951}
952
953static int m_can_close(struct net_device *dev)
954{
955 struct m_can_priv *priv = netdev_priv(dev);
956
957 netif_stop_queue(dev);
958 napi_disable(&priv->napi);
959 m_can_stop(dev);
960 free_irq(dev->irq, dev);
961 close_candev(dev);
962 can_led_event(dev, CAN_LED_EVENT_STOP);
963
964 return 0;
965}
966
967static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
968 struct net_device *dev)
969{
970 struct m_can_priv *priv = netdev_priv(dev);
971 struct can_frame *cf = (struct can_frame *)skb->data;
972 u32 id;
973
974 if (can_dropped_invalid_skb(dev, skb))
975 return NETDEV_TX_OK;
976
977 netif_stop_queue(dev);
978
979 if (cf->can_id & CAN_EFF_FLAG) {
980 id = cf->can_id & CAN_EFF_MASK;
981 id |= TX_BUF_XTD;
982 } else {
983 id = ((cf->can_id & CAN_SFF_MASK) << 18);
984 }
985
986 if (cf->can_id & CAN_RTR_FLAG)
987 id |= TX_BUF_RTR;
988
989 /* message ram configuration */
990 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
991 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, cf->can_dlc << 16);
992 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), *(u32 *)(cf->data + 0));
993 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), *(u32 *)(cf->data + 4));
994 can_put_echo_skb(skb, dev, 0);
995
996 /* enable first TX buffer to start transfer */
997 m_can_write(priv, M_CAN_TXBTIE, 0x1);
998 m_can_write(priv, M_CAN_TXBAR, 0x1);
999
1000 return NETDEV_TX_OK;
1001}
1002
1003static const struct net_device_ops m_can_netdev_ops = {
1004 .ndo_open = m_can_open,
1005 .ndo_stop = m_can_close,
1006 .ndo_start_xmit = m_can_start_xmit,
Dong Aishengd6fdb382014-10-29 18:45:23 +08001007 .ndo_change_mtu = can_change_mtu,
Dong Aishenge0d1f482014-07-16 17:30:50 +08001008};
1009
1010static int register_m_can_dev(struct net_device *dev)
1011{
1012 dev->flags |= IFF_ECHO; /* we support local echo */
1013 dev->netdev_ops = &m_can_netdev_ops;
1014
1015 return register_candev(dev);
1016}
1017
1018static int m_can_of_parse_mram(struct platform_device *pdev,
1019 struct m_can_priv *priv)
1020{
1021 struct device_node *np = pdev->dev.of_node;
1022 struct resource *res;
1023 void __iomem *addr;
1024 u32 out_val[MRAM_CFG_LEN];
Dong Aisheng962845d2014-11-07 16:45:14 +08001025 int i, start, end, ret;
Dong Aishenge0d1f482014-07-16 17:30:50 +08001026
1027 /* message ram could be shared */
1028 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1029 if (!res)
1030 return -ENODEV;
1031
1032 addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1033 if (!addr)
1034 return -ENOMEM;
1035
1036 /* get message ram configuration */
1037 ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1038 out_val, sizeof(out_val) / 4);
1039 if (ret) {
1040 dev_err(&pdev->dev, "can not get message ram configuration\n");
1041 return -ENODEV;
1042 }
1043
1044 priv->mram_base = addr;
1045 priv->mcfg[MRAM_SIDF].off = out_val[0];
1046 priv->mcfg[MRAM_SIDF].num = out_val[1];
1047 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1048 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1049 priv->mcfg[MRAM_XIDF].num = out_val[2];
1050 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1051 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1052 priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
1053 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1054 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1055 priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
1056 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1057 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1058 priv->mcfg[MRAM_RXB].num = out_val[5];
1059 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1060 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1061 priv->mcfg[MRAM_TXE].num = out_val[6];
1062 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1063 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1064 priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
1065
1066 dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1067 priv->mram_base,
1068 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1069 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1070 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1071 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1072 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1073 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1074 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1075
Dong Aisheng962845d2014-11-07 16:45:14 +08001076 /* initialize the entire Message RAM in use to avoid possible
1077 * ECC/parity checksum errors when reading an uninitialized buffer
1078 */
1079 start = priv->mcfg[MRAM_SIDF].off;
1080 end = priv->mcfg[MRAM_TXB].off +
1081 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1082 for (i = start; i < end; i += 4)
1083 writel(0x0, priv->mram_base + i);
1084
Dong Aishenge0d1f482014-07-16 17:30:50 +08001085 return 0;
1086}
1087
1088static int m_can_plat_probe(struct platform_device *pdev)
1089{
1090 struct net_device *dev;
1091 struct m_can_priv *priv;
1092 struct resource *res;
1093 void __iomem *addr;
1094 struct clk *hclk, *cclk;
1095 int irq, ret;
1096
1097 hclk = devm_clk_get(&pdev->dev, "hclk");
1098 cclk = devm_clk_get(&pdev->dev, "cclk");
1099 if (IS_ERR(hclk) || IS_ERR(cclk)) {
1100 dev_err(&pdev->dev, "no clock find\n");
1101 return -ENODEV;
1102 }
1103
1104 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1105 addr = devm_ioremap_resource(&pdev->dev, res);
1106 irq = platform_get_irq_byname(pdev, "int0");
1107 if (IS_ERR(addr) || irq < 0)
1108 return -EINVAL;
1109
1110 /* allocate the m_can device */
1111 dev = alloc_m_can_dev();
1112 if (!dev)
1113 return -ENOMEM;
1114
1115 priv = netdev_priv(dev);
1116 dev->irq = irq;
1117 priv->base = addr;
1118 priv->device = &pdev->dev;
1119 priv->hclk = hclk;
1120 priv->cclk = cclk;
1121 priv->can.clock.freq = clk_get_rate(cclk);
1122
1123 ret = m_can_of_parse_mram(pdev, priv);
1124 if (ret)
1125 goto failed_free_dev;
1126
1127 platform_set_drvdata(pdev, dev);
1128 SET_NETDEV_DEV(dev, &pdev->dev);
1129
1130 ret = register_m_can_dev(dev);
1131 if (ret) {
1132 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1133 KBUILD_MODNAME, ret);
1134 goto failed_free_dev;
1135 }
1136
1137 devm_can_led_init(dev);
1138
1139 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
1140 KBUILD_MODNAME, priv->base, dev->irq);
1141
1142 return 0;
1143
1144failed_free_dev:
1145 free_m_can_dev(dev);
1146 return ret;
1147}
1148
1149static __maybe_unused int m_can_suspend(struct device *dev)
1150{
1151 struct net_device *ndev = dev_get_drvdata(dev);
1152 struct m_can_priv *priv = netdev_priv(ndev);
1153
1154 if (netif_running(ndev)) {
1155 netif_stop_queue(ndev);
1156 netif_device_detach(ndev);
1157 }
1158
1159 /* TODO: enter low power */
1160
1161 priv->can.state = CAN_STATE_SLEEPING;
1162
1163 return 0;
1164}
1165
1166static __maybe_unused int m_can_resume(struct device *dev)
1167{
1168 struct net_device *ndev = dev_get_drvdata(dev);
1169 struct m_can_priv *priv = netdev_priv(ndev);
1170
1171 /* TODO: exit low power */
1172
1173 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1174
1175 if (netif_running(ndev)) {
1176 netif_device_attach(ndev);
1177 netif_start_queue(ndev);
1178 }
1179
1180 return 0;
1181}
1182
1183static void unregister_m_can_dev(struct net_device *dev)
1184{
1185 unregister_candev(dev);
1186}
1187
1188static int m_can_plat_remove(struct platform_device *pdev)
1189{
1190 struct net_device *dev = platform_get_drvdata(pdev);
1191
1192 unregister_m_can_dev(dev);
1193 platform_set_drvdata(pdev, NULL);
1194
1195 free_m_can_dev(dev);
1196
1197 return 0;
1198}
1199
1200static const struct dev_pm_ops m_can_pmops = {
1201 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1202};
1203
1204static const struct of_device_id m_can_of_table[] = {
1205 { .compatible = "bosch,m_can", .data = NULL },
1206 { /* sentinel */ },
1207};
1208MODULE_DEVICE_TABLE(of, m_can_of_table);
1209
1210static struct platform_driver m_can_plat_driver = {
1211 .driver = {
1212 .name = KBUILD_MODNAME,
1213 .of_match_table = m_can_of_table,
1214 .pm = &m_can_pmops,
1215 },
1216 .probe = m_can_plat_probe,
1217 .remove = m_can_plat_remove,
1218};
1219
1220module_platform_driver(m_can_plat_driver);
1221
1222MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1223MODULE_LICENSE("GPL v2");
1224MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");