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Vaibhav Hirematha2cfc502012-07-25 13:51:13 -06001/*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Tony Lindgren3a8761c2012-10-08 09:11:22 -070017#include <linux/i2c-omap.h>
18
Tony Lindgren2a296c82012-10-02 17:41:35 -070019#include "omap_hwmod.h"
Tony Lindgren11964f52012-09-12 21:29:07 -070020#include <linux/platform_data/gpio-omap.h>
Kevin Hilmanaa817b22012-09-20 09:38:14 -070021#include <linux/platform_data/spi-omap2-mcspi.h>
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060022
23#include "omap_hwmod_common_data.h"
24
25#include "control.h"
26#include "cm33xx.h"
27#include "prm33xx.h"
28#include "prm-regbits-33xx.h"
Tony Lindgren3a8761c2012-10-08 09:11:22 -070029#include "i2c.h"
Vaibhav Hiremath05cf03b2013-03-31 20:22:21 -060030#include "wd_timer.h"
Afzal Mohammed26649462013-10-12 15:44:46 +053031#include "omap_hwmod_33xx_43xx_common_data.h"
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060032
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060033/*
34 * IP blocks
35 */
36
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060037/* emif */
38static struct omap_hwmod am33xx_emif_hwmod = {
39 .name = "emif",
40 .class = &am33xx_emif_hwmod_class,
41 .clkdm_name = "l3_clkdm",
Rajendra Nayakb2eb0002013-08-20 13:02:44 +053042 .flags = HWMOD_INIT_NO_IDLE,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060043 .main_clk = "dpll_ddr_m2_div2_ck",
44 .prcm = {
45 .omap4 = {
46 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
47 .modulemode = MODULEMODE_SWCTRL,
48 },
49 },
50};
51
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060052/* l4_hs */
53static struct omap_hwmod am33xx_l4_hs_hwmod = {
54 .name = "l4_hs",
55 .class = &am33xx_l4_hwmod_class,
56 .clkdm_name = "l4hs_clkdm",
Rajendra Nayakb2eb0002013-08-20 13:02:44 +053057 .flags = HWMOD_INIT_NO_IDLE,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060058 .main_clk = "l4hs_gclk",
59 .prcm = {
60 .omap4 = {
61 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
62 .modulemode = MODULEMODE_SWCTRL,
63 },
64 },
65};
66
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060067static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
68 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
69};
70
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060071/* wkup_m3 */
72static struct omap_hwmod am33xx_wkup_m3_hwmod = {
73 .name = "wkup_m3",
74 .class = &am33xx_wkup_m3_hwmod_class,
75 .clkdm_name = "l4_wkup_aon_clkdm",
Hebbar Gururaja092bda62013-02-08 08:21:10 -070076 /* Keep hardreset asserted */
77 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060078 .main_clk = "dpll_core_m4_div2_ck",
79 .prcm = {
80 .omap4 = {
81 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
82 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
Vaibhav Bedia3077fe62013-01-29 16:45:05 +053083 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060084 .modulemode = MODULEMODE_SWCTRL,
85 },
86 },
87 .rst_lines = am33xx_wkup_m3_resets,
88 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
89};
90
91/*
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -060092 * 'adc/tsc' class
93 * TouchScreen Controller (Anolog-To-Digital Converter)
94 */
95static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
96 .rev_offs = 0x00,
97 .sysc_offs = 0x10,
98 .sysc_flags = SYSC_HAS_SIDLEMODE,
99 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
100 SIDLE_SMART_WKUP),
101 .sysc_fields = &omap_hwmod_sysc_type2,
102};
103
104static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
105 .name = "adc_tsc",
106 .sysc = &am33xx_adc_tsc_sysc,
107};
108
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600109static struct omap_hwmod am33xx_adc_tsc_hwmod = {
110 .name = "adc_tsc",
111 .class = &am33xx_adc_tsc_hwmod_class,
112 .clkdm_name = "l4_wkup_clkdm",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600113 .main_clk = "adc_tsc_fck",
114 .prcm = {
115 .omap4 = {
116 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
117 .modulemode = MODULEMODE_SWCTRL,
118 },
119 },
120};
121
122/*
123 * Modules omap_hwmod structures
124 *
125 * The following IPs are excluded for the moment because:
126 * - They do not need an explicit SW control using omap_hwmod API.
127 * - They still need to be validated with the driver
128 * properly adapted to omap_hwmod / omap_device
129 *
130 * - cEFUSE (doesn't fall under any ocp_if)
131 * - clkdiv32k
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600132 * - ocp watch point
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600133 */
134#if 0
135/*
136 * 'cefuse' class
137 */
138static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
139 .name = "cefuse",
140};
141
142static struct omap_hwmod am33xx_cefuse_hwmod = {
143 .name = "cefuse",
144 .class = &am33xx_cefuse_hwmod_class,
145 .clkdm_name = "l4_cefuse_clkdm",
146 .main_clk = "cefuse_fck",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
150 .modulemode = MODULEMODE_SWCTRL,
151 },
152 },
153};
154
155/*
156 * 'clkdiv32k' class
157 */
158static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
159 .name = "clkdiv32k",
160};
161
162static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
163 .name = "clkdiv32k",
164 .class = &am33xx_clkdiv32k_hwmod_class,
165 .clkdm_name = "clk_24mhz_clkdm",
166 .main_clk = "clkdiv32k_ick",
167 .prcm = {
168 .omap4 = {
169 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
170 .modulemode = MODULEMODE_SWCTRL,
171 },
172 },
173};
174
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600175/* ocpwp */
176static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
177 .name = "ocpwp",
178};
179
180static struct omap_hwmod am33xx_ocpwp_hwmod = {
181 .name = "ocpwp",
182 .class = &am33xx_ocpwp_hwmod_class,
183 .clkdm_name = "l4ls_clkdm",
184 .main_clk = "l4ls_gclk",
185 .prcm = {
186 .omap4 = {
187 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
188 .modulemode = MODULEMODE_SWCTRL,
189 },
190 },
191};
Mark A. Greer1cb804b2012-12-21 09:28:14 -0700192#endif
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600193
194/*
Vaibhav Hiremath1721c702013-08-20 18:54:09 -0600195 * 'debugss' class
196 * debug sub system
197 */
198static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
199 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
200 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
201};
202
203static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
204 .name = "debugss",
205};
206
207static struct omap_hwmod am33xx_debugss_hwmod = {
208 .name = "debugss",
209 .class = &am33xx_debugss_hwmod_class,
210 .clkdm_name = "l3_aon_clkdm",
211 .main_clk = "trace_clk_div_ck",
212 .prcm = {
213 .omap4 = {
214 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218 .opt_clks = debugss_opt_clks,
219 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
220};
221
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600222static struct omap_hwmod am33xx_control_hwmod = {
223 .name = "control",
224 .class = &am33xx_control_hwmod_class,
225 .clkdm_name = "l4_wkup_clkdm",
Rajendra Nayakb2eb0002013-08-20 13:02:44 +0530226 .flags = HWMOD_INIT_NO_IDLE,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600227 .main_clk = "dpll_core_m4_div2_ck",
228 .prcm = {
229 .omap4 = {
230 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
231 .modulemode = MODULEMODE_SWCTRL,
232 },
233 },
234};
235
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600236/* gpio0 */
237static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
238 { .role = "dbclk", .clk = "gpio0_dbclk" },
239};
240
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600241static struct omap_hwmod am33xx_gpio0_hwmod = {
242 .name = "gpio1",
243 .class = &am33xx_gpio_hwmod_class,
244 .clkdm_name = "l4_wkup_clkdm",
245 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600246 .main_clk = "dpll_core_m4_div2_ck",
247 .prcm = {
248 .omap4 = {
249 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
250 .modulemode = MODULEMODE_SWCTRL,
251 },
252 },
253 .opt_clks = gpio0_opt_clks,
254 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
255 .dev_attr = &gpio_dev_attr,
256};
257
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600258/* lcdc */
259static struct omap_hwmod_class_sysconfig lcdc_sysc = {
260 .rev_offs = 0x0,
261 .sysc_offs = 0x54,
262 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
263 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
264 .sysc_fields = &omap_hwmod_sysc_type2,
265};
266
267static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
268 .name = "lcdc",
269 .sysc = &lcdc_sysc,
270};
271
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600272static struct omap_hwmod am33xx_lcdc_hwmod = {
273 .name = "lcdc",
274 .class = &am33xx_lcdc_hwmod_class,
275 .clkdm_name = "lcdc_clkdm",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600276 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
277 .main_clk = "lcd_gclk",
278 .prcm = {
279 .omap4 = {
280 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
281 .modulemode = MODULEMODE_SWCTRL,
282 },
283 },
284};
285
286/*
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600287 * 'usb_otg' class
288 * high-speed on-the-go universal serial bus (usb_otg) controller
289 */
290static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
291 .rev_offs = 0x0,
292 .sysc_offs = 0x10,
293 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
294 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
295 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
296 .sysc_fields = &omap_hwmod_sysc_type2,
297};
298
299static struct omap_hwmod_class am33xx_usbotg_class = {
300 .name = "usbotg",
301 .sysc = &am33xx_usbhsotg_sysc,
302};
303
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600304static struct omap_hwmod am33xx_usbss_hwmod = {
305 .name = "usb_otg_hs",
306 .class = &am33xx_usbotg_class,
307 .clkdm_name = "l3s_clkdm",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600308 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
309 .main_clk = "usbotg_fck",
310 .prcm = {
311 .omap4 = {
312 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
313 .modulemode = MODULEMODE_SWCTRL,
314 },
315 },
316};
317
318
319/*
320 * Interfaces
321 */
322
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600323/* l3 main -> emif */
324static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
325 .master = &am33xx_l3_main_hwmod,
326 .slave = &am33xx_emif_hwmod,
327 .clk = "dpll_core_m4_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329};
330
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600331/* l3 main -> l4 hs */
332static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
333 .master = &am33xx_l3_main_hwmod,
334 .slave = &am33xx_l4_hs_hwmod,
335 .clk = "l3s_gclk",
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337};
338
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600339/* wkup m3 -> l4 wkup */
340static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
341 .master = &am33xx_wkup_m3_hwmod,
342 .slave = &am33xx_l4_wkup_hwmod,
343 .clk = "dpll_core_m4_div2_ck",
344 .user = OCP_USER_MPU | OCP_USER_SDMA,
345};
346
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600347/* l4 wkup -> wkup m3 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600348static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
349 .master = &am33xx_l4_wkup_hwmod,
350 .slave = &am33xx_wkup_m3_hwmod,
351 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600352 .user = OCP_USER_MPU | OCP_USER_SDMA,
353};
354
355/* l4 hs -> pru-icss */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600356static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
357 .master = &am33xx_l4_hs_hwmod,
358 .slave = &am33xx_pruss_hwmod,
359 .clk = "dpll_core_m4_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600360 .user = OCP_USER_MPU | OCP_USER_SDMA,
361};
362
Vaibhav Hiremath1721c702013-08-20 18:54:09 -0600363/* l3_main -> debugss */
Vaibhav Hiremath1721c702013-08-20 18:54:09 -0600364static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
365 .master = &am33xx_l3_main_hwmod,
366 .slave = &am33xx_debugss_hwmod,
367 .clk = "dpll_core_m4_ck",
Vaibhav Hiremath1721c702013-08-20 18:54:09 -0600368 .user = OCP_USER_MPU,
369};
370
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600371/* l4 wkup -> smartreflex0 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600372static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
373 .master = &am33xx_l4_wkup_hwmod,
374 .slave = &am33xx_smartreflex0_hwmod,
375 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600376 .user = OCP_USER_MPU,
377};
378
379/* l4 wkup -> smartreflex1 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600380static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
381 .master = &am33xx_l4_wkup_hwmod,
382 .slave = &am33xx_smartreflex1_hwmod,
383 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600384 .user = OCP_USER_MPU,
385};
386
387/* l4 wkup -> control */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600388static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
389 .master = &am33xx_l4_wkup_hwmod,
390 .slave = &am33xx_control_hwmod,
391 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600392 .user = OCP_USER_MPU,
393};
394
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600395/* L4 WKUP -> I2C1 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600396static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
397 .master = &am33xx_l4_wkup_hwmod,
398 .slave = &am33xx_i2c1_hwmod,
399 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600400 .user = OCP_USER_MPU,
401};
402
403/* L4 WKUP -> GPIO1 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600404static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
405 .master = &am33xx_l4_wkup_hwmod,
406 .slave = &am33xx_gpio0_hwmod,
407 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600408 .user = OCP_USER_MPU | OCP_USER_SDMA,
409};
410
411/* L4 WKUP -> ADC_TSC */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600412static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
413 .master = &am33xx_l4_wkup_hwmod,
414 .slave = &am33xx_adc_tsc_hwmod,
415 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600416 .user = OCP_USER_MPU,
417};
418
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600419static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
420 .master = &am33xx_l4_hs_hwmod,
421 .slave = &am33xx_cpgmac0_hwmod,
422 .clk = "cpsw_125mhz_gclk",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600423 .user = OCP_USER_MPU,
424};
425
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600426static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
427 .master = &am33xx_l3_main_hwmod,
428 .slave = &am33xx_lcdc_hwmod,
429 .clk = "dpll_core_m4_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600430 .user = OCP_USER_MPU,
431};
432
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600433/* l4 wkup -> timer1 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600434static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
435 .master = &am33xx_l4_wkup_hwmod,
436 .slave = &am33xx_timer1_hwmod,
437 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600438 .user = OCP_USER_MPU,
439};
440
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600441/* l4 wkup -> uart1 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600442static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
443 .master = &am33xx_l4_wkup_hwmod,
444 .slave = &am33xx_uart1_hwmod,
445 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600446 .user = OCP_USER_MPU,
447};
448
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600449/* l4 wkup -> wd_timer1 */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600450static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
451 .master = &am33xx_l4_wkup_hwmod,
452 .slave = &am33xx_wd_timer1_hwmod,
453 .clk = "dpll_core_m4_div2_ck",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600454 .user = OCP_USER_MPU,
455};
456
457/* usbss */
458/* l3 s -> USBSS interface */
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600459static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
460 .master = &am33xx_l3_s_hwmod,
461 .slave = &am33xx_usbss_hwmod,
462 .clk = "l3s_gclk",
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600463 .user = OCP_USER_MPU,
464 .flags = OCPIF_SWSUP_IDLE,
465};
466
467static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600468 &am33xx_l3_main__emif,
469 &am33xx_mpu__l3_main,
470 &am33xx_mpu__prcm,
471 &am33xx_l3_s__l4_ls,
472 &am33xx_l3_s__l4_wkup,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600473 &am33xx_l3_main__l4_hs,
474 &am33xx_l3_main__l3_s,
475 &am33xx_l3_main__l3_instr,
476 &am33xx_l3_main__gfx,
477 &am33xx_l3_s__l3_main,
478 &am33xx_pruss__l3_main,
479 &am33xx_wkup_m3__l4_wkup,
480 &am33xx_gfx__l3_main,
Vaibhav Hiremath1721c702013-08-20 18:54:09 -0600481 &am33xx_l3_main__debugss,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600482 &am33xx_l4_wkup__wkup_m3,
483 &am33xx_l4_wkup__control,
484 &am33xx_l4_wkup__smartreflex0,
485 &am33xx_l4_wkup__smartreflex1,
486 &am33xx_l4_wkup__uart1,
487 &am33xx_l4_wkup__timer1,
488 &am33xx_l4_wkup__rtc,
489 &am33xx_l4_wkup__i2c1,
490 &am33xx_l4_wkup__gpio0,
491 &am33xx_l4_wkup__adc_tsc,
492 &am33xx_l4_wkup__wd_timer1,
493 &am33xx_l4_hs__pruss,
494 &am33xx_l4_per__dcan0,
495 &am33xx_l4_per__dcan1,
496 &am33xx_l4_per__gpio1,
497 &am33xx_l4_per__gpio2,
498 &am33xx_l4_per__gpio3,
499 &am33xx_l4_per__i2c2,
500 &am33xx_l4_per__i2c3,
501 &am33xx_l4_per__mailbox,
502 &am33xx_l4_ls__mcasp0,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600503 &am33xx_l4_ls__mcasp1,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600504 &am33xx_l4_ls__mmc0,
505 &am33xx_l4_ls__mmc1,
506 &am33xx_l3_s__mmc2,
507 &am33xx_l4_ls__timer2,
508 &am33xx_l4_ls__timer3,
509 &am33xx_l4_ls__timer4,
510 &am33xx_l4_ls__timer5,
511 &am33xx_l4_ls__timer6,
512 &am33xx_l4_ls__timer7,
513 &am33xx_l3_main__tpcc,
514 &am33xx_l4_ls__uart2,
515 &am33xx_l4_ls__uart3,
516 &am33xx_l4_ls__uart4,
517 &am33xx_l4_ls__uart5,
518 &am33xx_l4_ls__uart6,
519 &am33xx_l4_ls__spinlock,
520 &am33xx_l4_ls__elm,
Philip Avinash9652d192013-01-02 18:54:49 +0530521 &am33xx_l4_ls__epwmss0,
Philip Avinash9652d192013-01-02 18:54:49 +0530522 &am33xx_l4_ls__epwmss1,
Philip Avinash9652d192013-01-02 18:54:49 +0530523 &am33xx_l4_ls__epwmss2,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600524 &am33xx_l3_s__gpmc,
525 &am33xx_l3_main__lcdc,
526 &am33xx_l4_ls__mcspi0,
527 &am33xx_l4_ls__mcspi1,
528 &am33xx_l3_main__tptc0,
529 &am33xx_l3_main__tptc1,
530 &am33xx_l3_main__tptc2,
Vaibhav Bediaca903b62013-01-29 16:45:02 +0530531 &am33xx_l3_main__ocmc,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600532 &am33xx_l3_s__usbss,
533 &am33xx_l4_hs__cpgmac0,
Mugunthan V N70384a62012-11-14 09:07:58 +0000534 &am33xx_cpgmac0__mdio,
Mark A. Greeraec94bf2013-03-18 10:06:35 -0600535 &am33xx_l3_main__sha0,
Mark A. Greer1cb804b2012-12-21 09:28:14 -0700536 &am33xx_l3_main__aes0,
Lokesh Vutlaace1e3e2013-08-29 18:22:10 +0530537 &am33xx_l4_per__rng,
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600538 NULL,
539};
540
541int __init am33xx_hwmod_init(void)
542{
Afzal Mohammed1c7e2242013-10-12 15:45:26 +0530543 omap_hwmod_am33xx_reg();
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600544 omap_hwmod_init();
545 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
546}