| Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, NVIDIA Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #ifndef TEGRA_VIC_H |
| 10 | #define TEGRA_VIC_H |
| 11 | |
| 12 | /* VIC methods */ |
| 13 | |
| 14 | #define VIC_SET_APPLICATION_ID 0x00000200 |
| 15 | #define VIC_SET_FCE_UCODE_SIZE 0x0000071C |
| 16 | #define VIC_SET_FCE_UCODE_OFFSET 0x0000072C |
| 17 | |
| 18 | /* VIC registers */ |
| 19 | |
| 20 | #define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0 |
| 21 | #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0) |
| 22 | #define CG_IDLE_CG_EN (1 << 6) |
| 23 | #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) |
| 24 | |
| 25 | /* Firmware offsets */ |
| 26 | |
| 27 | #define VIC_UCODE_FCE_HEADER_OFFSET (6*4) |
| 28 | #define VIC_UCODE_FCE_DATA_OFFSET (7*4) |
| 29 | #define FCE_UCODE_SIZE_OFFSET (2*4) |
| 30 | |
| 31 | #endif /* TEGRA_VIC_H */ |