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gerrit-public.fairphone.software / kernel / msm-5.4 / 84a263f39403ca3b399af77499876e02e634b00b / . / drivers / pci / host / pcie-designware.h
blob: a476e60993cb4c6ede387761ba906c29c751d1dd [file] [log] [blame]
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]1/*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
Seungwon Jeon18edf452013-10-09 09:12:21 -0600[diff] [blame]14#ifndef _PCIE_DESIGNWARE_H
15#define _PCIE_DESIGNWARE_H
16
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]17struct pcie_port_info {
18 u32 cfg0_size;
19 u32 cfg1_size;
20 u32 io_size;
21 u32 mem_size;
22 phys_addr_t io_bus_addr;
23 phys_addr_t mem_bus_addr;
24};
25
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]26/*
27 * Maximum number of MSI IRQs can be 256 per controller. But keep
28 * it 32 as of now. Probably we will never need more than 32. If needed,
29 * then increment it in multiple of 32.
30 */
31#define MAX_MSI_IRQS 32
32#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
33
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]34struct pcie_port {
35 struct device *dev;
36 u8 root_bus_nr;
37 void __iomem *dbi_base;
38 u64 cfg0_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]39 u64 cfg0_mod_base;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]40 void __iomem *va_cfg0_base;
41 u64 cfg1_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]42 u64 cfg1_mod_base;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]43 void __iomem *va_cfg1_base;
44 u64 io_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]45 u64 io_mod_base;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]46 u64 mem_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]47 u64 mem_mod_base;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]48 struct resource cfg;
49 struct resource io;
50 struct resource mem;
Lucas Stach4f2ebe02014-07-23 19:52:38 +0200[diff] [blame]51 struct resource busn;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]52 struct pcie_port_info config;
53 int irq;
54 u32 lanes;
55 struct pcie_host_ops *ops;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]56 int msi_irq;
Pratyush Anand904d0e72013-10-09 21:32:12 +0900[diff] [blame]57 struct irq_domain *irq_domain;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]58 unsigned long msi_data;
59 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]60};
61
62struct pcie_host_ops {
63 void (*readl_rc)(struct pcie_port *pp,
64 void __iomem *dbi_base, u32 *val);
65 void (*writel_rc)(struct pcie_port *pp,
66 u32 val, void __iomem *dbi_base);
67 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
68 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
Murali Karicheria1c0ae92014-07-21 12:58:41 -0400[diff] [blame]69 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
70 unsigned int devfn, int where, int size, u32 *val);
71 int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
72 unsigned int devfn, int where, int size, u32 val);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]73 int (*link_up)(struct pcie_port *pp);
74 void (*host_init)(struct pcie_port *pp);
Murali Karicheri2f37c5a2014-07-21 12:58:42 -0400[diff] [blame]75 void (*msi_set_irq)(struct pcie_port *pp, int irq);
76 void (*msi_clear_irq)(struct pcie_port *pp, int irq);
77 u32 (*get_msi_data)(struct pcie_port *pp);
Murali Karicherib14a3d12014-07-23 14:54:51 -0400[diff] [blame]78 void (*scan_bus)(struct pcie_port *pp);
79 int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]80};
81
Pratyush Ananda01ef592013-12-11 15:08:32 +0530[diff] [blame]82int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
83int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
Lucas Stach7f4f16e2014-03-28 17:52:58 +0100[diff] [blame]84irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]85void dw_pcie_msi_init(struct pcie_port *pp);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]86int dw_pcie_link_up(struct pcie_port *pp);
87void dw_pcie_setup_rc(struct pcie_port *pp);
88int dw_pcie_host_init(struct pcie_port *pp);
Seungwon Jeon18edf452013-10-09 09:12:21 -0600[diff] [blame]89
90#endif /* _PCIE_DESIGNWARE_H */