| Mark Salter | 041cadc | 2011-10-04 12:12:20 -0400 | [diff] [blame] | 1 | |
| 2 | / { |
| 3 | #address-cells = <1>; |
| 4 | #size-cells = <1>; |
| 5 | |
| 6 | cpus { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <0>; |
| 9 | |
| 10 | cpu@0 { |
| 11 | device_type = "cpu"; |
| 12 | reg = <0>; |
| 13 | model = "ti,c64x+"; |
| 14 | }; |
| 15 | cpu@1 { |
| 16 | device_type = "cpu"; |
| 17 | reg = <1>; |
| 18 | model = "ti,c64x+"; |
| 19 | }; |
| 20 | cpu@2 { |
| 21 | device_type = "cpu"; |
| 22 | reg = <2>; |
| 23 | model = "ti,c64x+"; |
| 24 | }; |
| 25 | cpu@3 { |
| 26 | device_type = "cpu"; |
| 27 | reg = <3>; |
| 28 | model = "ti,c64x+"; |
| 29 | }; |
| 30 | cpu@4 { |
| 31 | device_type = "cpu"; |
| 32 | reg = <4>; |
| 33 | model = "ti,c64x+"; |
| 34 | }; |
| 35 | cpu@5 { |
| 36 | device_type = "cpu"; |
| 37 | reg = <5>; |
| 38 | model = "ti,c64x+"; |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | soc { |
| 43 | compatible = "simple-bus"; |
| 44 | model = "tms320c6472"; |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <1>; |
| 47 | ranges; |
| 48 | |
| 49 | core_pic: interrupt-controller { |
| 50 | compatible = "ti,c64x+core-pic"; |
| 51 | interrupt-controller; |
| 52 | #interrupt-cells = <1>; |
| 53 | }; |
| 54 | |
| 55 | megamod_pic: interrupt-controller@1800000 { |
| 56 | compatible = "ti,c64x+megamod-pic"; |
| 57 | interrupt-controller; |
| 58 | #interrupt-cells = <1>; |
| 59 | reg = <0x1800000 0x1000>; |
| 60 | interrupt-parent = <&core_pic>; |
| 61 | }; |
| 62 | |
| 63 | cache-controller@1840000 { |
| 64 | compatible = "ti,c64x+cache"; |
| 65 | reg = <0x01840000 0x8400>; |
| 66 | }; |
| 67 | |
| 68 | timer0: timer@25e0000 { |
| 69 | compatible = "ti,c64x+timer64"; |
| 70 | ti,core-mask = < 0x01 >; |
| 71 | reg = <0x25e0000 0x40>; |
| 72 | }; |
| 73 | |
| 74 | timer1: timer@25f0000 { |
| 75 | compatible = "ti,c64x+timer64"; |
| 76 | ti,core-mask = < 0x02 >; |
| 77 | reg = <0x25f0000 0x40>; |
| 78 | }; |
| 79 | |
| 80 | timer2: timer@2600000 { |
| 81 | compatible = "ti,c64x+timer64"; |
| 82 | ti,core-mask = < 0x04 >; |
| 83 | reg = <0x2600000 0x40>; |
| 84 | }; |
| 85 | |
| 86 | timer3: timer@2610000 { |
| 87 | compatible = "ti,c64x+timer64"; |
| 88 | ti,core-mask = < 0x08 >; |
| 89 | reg = <0x2610000 0x40>; |
| 90 | }; |
| 91 | |
| 92 | timer4: timer@2620000 { |
| 93 | compatible = "ti,c64x+timer64"; |
| 94 | ti,core-mask = < 0x10 >; |
| 95 | reg = <0x2620000 0x40>; |
| 96 | }; |
| 97 | |
| 98 | timer5: timer@2630000 { |
| 99 | compatible = "ti,c64x+timer64"; |
| 100 | ti,core-mask = < 0x20 >; |
| 101 | reg = <0x2630000 0x40>; |
| 102 | }; |
| 103 | |
| 104 | clock-controller@29a0000 { |
| 105 | compatible = "ti,c6472-pll", "ti,c64x+pll"; |
| 106 | reg = <0x029a0000 0x200>; |
| 107 | ti,c64x+pll-bypass-delay = <200>; |
| 108 | ti,c64x+pll-reset-delay = <12000>; |
| 109 | ti,c64x+pll-lock-delay = <80000>; |
| 110 | }; |
| 111 | |
| 112 | device-state-controller@2a80000 { |
| 113 | compatible = "ti,c64x+dscr"; |
| 114 | reg = <0x02a80000 0x1000>; |
| 115 | |
| 116 | ti,dscr-devstat = <0>; |
| 117 | ti,dscr-silicon-rev = <0x70c 16 0xff>; |
| 118 | |
| 119 | ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 |
| 120 | 0x704 5 6 0 0>; |
| 121 | |
| 122 | ti,dscr-rmii-resets = <0x208 1 |
| 123 | 0x20c 1>; |
| 124 | |
| 125 | ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a |
| 126 | 0x40c 0x420 0xbea7 |
| 127 | 0x41c 0x420 0xbea7>; |
| 128 | |
| 129 | ti,dscr-privperm = <0x41c 0xaaaaaaaa>; |
| 130 | |
| 131 | ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>; |
| 132 | }; |
| 133 | }; |
| 134 | }; |