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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Terje Bergstromd43f81c2013-03-22 16:34:09 +02003 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Terje Bergstrom4231c6b2013-03-22 16:34:05 +020010#ifndef HOST1X_DRM_H
11#define HOST1X_DRM_H 1
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000012
Thierry Redinge1e90642013-09-24 13:59:01 +020013#include <uapi/drm/tegra_drm.h>
14#include <linux/host1x.h>
Thierry Redingfb36d0ee2015-04-27 15:12:39 +020015#include <linux/of_gpio.h>
Thierry Redinge1e90642013-09-24 13:59:01 +020016
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000017#include <drm/drmP.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_edid.h>
20#include <drm/drm_fb_helper.h>
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000021#include <drm/drm_fixed.h>
22
Thierry Redingc134f012014-06-03 14:48:12 +020023#include "gem.h"
24
Stephen Warrenca480802013-11-06 16:20:54 -070025struct reset_control;
26
Arto Merilainende2ba662013-03-22 16:34:08 +020027struct tegra_fb {
28 struct drm_framebuffer base;
29 struct tegra_bo **planes;
30 unsigned int num_planes;
31};
32
Archit Tanejab110ef32015-10-27 13:40:59 +053033#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020034struct tegra_fbdev {
35 struct drm_fb_helper base;
36 struct tegra_fb *fb;
37};
Thierry Reding60c2f702013-10-31 13:28:50 +010038#endif
Arto Merilainende2ba662013-03-22 16:34:08 +020039
Thierry Reding386a2a72013-09-24 13:22:17 +020040struct tegra_drm {
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000041 struct drm_device *drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000042
Thierry Redingdf06b752014-06-26 21:41:53 +020043 struct iommu_domain *domain;
44 struct drm_mm mm;
45
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000046 struct mutex clients_lock;
47 struct list_head clients;
48
Archit Tanejab110ef32015-10-27 13:40:59 +053049#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020050 struct tegra_fbdev *fbdev;
Thierry Reding60c2f702013-10-31 13:28:50 +010051#endif
Thierry Redingd1f3e1e2014-07-11 08:29:14 +020052
53 unsigned int pitch_align;
Thierry Reding1503ca42014-11-24 17:41:23 +010054
55 struct {
56 struct drm_atomic_state *state;
57 struct work_struct work;
58 struct mutex lock;
59 } commit;
Thierry Reding986c58d2015-08-11 13:11:49 +020060
61 struct drm_atomic_state *state;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000062};
63
Thierry Reding53fa7f72013-09-24 15:35:40 +020064struct tegra_drm_client;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000065
Thierry Redingc88c3632013-09-26 16:08:22 +020066struct tegra_drm_context {
Thierry Reding53fa7f72013-09-24 15:35:40 +020067 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +020068 struct host1x_channel *channel;
69 struct list_head list;
70};
71
Thierry Reding53fa7f72013-09-24 15:35:40 +020072struct tegra_drm_client_ops {
73 int (*open_channel)(struct tegra_drm_client *client,
Thierry Redingc88c3632013-09-26 16:08:22 +020074 struct tegra_drm_context *context);
75 void (*close_channel)(struct tegra_drm_context *context);
Thierry Redingc40f0f12013-10-10 11:00:33 +020076 int (*is_addr_reg)(struct device *dev, u32 class, u32 offset);
Thierry Redingc88c3632013-09-26 16:08:22 +020077 int (*submit)(struct tegra_drm_context *context,
Terje Bergstromd43f81c2013-03-22 16:34:09 +020078 struct drm_tegra_submit *args, struct drm_device *drm,
79 struct drm_file *file);
80};
81
Thierry Redingc40f0f12013-10-10 11:00:33 +020082int tegra_drm_submit(struct tegra_drm_context *context,
83 struct drm_tegra_submit *args, struct drm_device *drm,
84 struct drm_file *file);
85
Thierry Reding53fa7f72013-09-24 15:35:40 +020086struct tegra_drm_client {
87 struct host1x_client base;
Thierry Reding776dc382013-10-14 14:43:22 +020088 struct list_head list;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000089
Thierry Reding53fa7f72013-09-24 15:35:40 +020090 const struct tegra_drm_client_ops *ops;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000091};
92
Thierry Reding53fa7f72013-09-24 15:35:40 +020093static inline struct tegra_drm_client *
Thierry Reding776dc382013-10-14 14:43:22 +020094host1x_to_drm_client(struct host1x_client *client)
Thierry Reding53fa7f72013-09-24 15:35:40 +020095{
96 return container_of(client, struct tegra_drm_client, base);
97}
98
Thierry Reding688c59a2014-04-16 09:54:21 +020099int tegra_drm_register_client(struct tegra_drm *tegra,
100 struct tegra_drm_client *client);
101int tegra_drm_unregister_client(struct tegra_drm *tegra,
102 struct tegra_drm_client *client);
Thierry Reding776dc382013-10-14 14:43:22 +0200103
Thierry Reding688c59a2014-04-16 09:54:21 +0200104int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm);
105int tegra_drm_exit(struct tegra_drm *tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000106
Thierry Reding8620fc62013-12-12 11:03:59 +0100107struct tegra_dc_soc_info;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000108struct tegra_output;
109
Thierry Reding791ddb12015-07-28 21:27:05 +0200110struct tegra_dc_stats {
111 unsigned long frames;
112 unsigned long vblank;
113 unsigned long underflow;
114 unsigned long overflow;
115};
116
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000117struct tegra_dc {
Thierry Reding776dc382013-10-14 14:43:22 +0200118 struct host1x_client client;
Thierry Reding42e9ce02015-01-28 14:43:05 +0100119 struct host1x_syncpt *syncpt;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000120 struct device *dev;
Thierry Redingd18d3032013-09-26 16:09:19 +0200121 spinlock_t lock;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000122
123 struct drm_crtc base;
Jon Hunter70293ed2016-02-11 18:03:22 +0000124 unsigned int powergate;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000125 int pipe;
126
127 struct clk *clk;
Stephen Warrenca480802013-11-06 16:20:54 -0700128 struct reset_control *rst;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000129 void __iomem *regs;
130 int irq;
131
132 struct tegra_output *rgb;
133
Thierry Reding791ddb12015-07-28 21:27:05 +0200134 struct tegra_dc_stats stats;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000135 struct list_head list;
136
137 struct drm_info_list *debugfs_files;
138 struct drm_minor *minor;
139 struct dentry *debugfs;
Thierry Reding3c03c462012-11-28 12:00:18 +0100140
141 /* page-flip handling */
142 struct drm_pending_vblank_event *event;
Thierry Reding8620fc62013-12-12 11:03:59 +0100143
144 const struct tegra_dc_soc_info *soc;
Thierry Redingdf06b752014-06-26 21:41:53 +0200145
146 struct iommu_domain *domain;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000147};
148
Thierry Reding53fa7f72013-09-24 15:35:40 +0200149static inline struct tegra_dc *
Thierry Reding776dc382013-10-14 14:43:22 +0200150host1x_client_to_dc(struct host1x_client *client)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000151{
152 return container_of(client, struct tegra_dc, client);
153}
154
155static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
156{
Thierry Reding37826512013-11-08 12:30:37 +0100157 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000158}
159
Thierry Reding03a60562014-10-21 13:48:48 +0200160static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
161 unsigned long offset)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000162{
Thierry Reding03a60562014-10-21 13:48:48 +0200163 writel(value, dc->regs + (offset << 2));
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000164}
165
Thierry Reding03a60562014-10-21 13:48:48 +0200166static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000167{
Thierry Reding03a60562014-10-21 13:48:48 +0200168 return readl(dc->regs + (offset << 2));
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000169}
170
Thierry Redingf34bc782012-11-04 21:47:13 +0100171struct tegra_dc_window {
172 struct {
173 unsigned int x;
174 unsigned int y;
175 unsigned int w;
176 unsigned int h;
177 } src;
178 struct {
179 unsigned int x;
180 unsigned int y;
181 unsigned int w;
182 unsigned int h;
183 } dst;
184 unsigned int bits_per_pixel;
Thierry Redingf34bc782012-11-04 21:47:13 +0100185 unsigned int stride[2];
186 unsigned long base[3];
Thierry Redingdb7fbdf2013-10-07 09:47:58 +0200187 bool bottom_up;
Thierry Redingc134f012014-06-03 14:48:12 +0200188
189 struct tegra_bo_tiling tiling;
Thierry Reding8f604f82014-11-28 13:14:55 +0100190 u32 format;
191 u32 swap;
Thierry Redingf34bc782012-11-04 21:47:13 +0100192};
193
194/* from dc.c */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100195u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc);
Thierry Reding688c59a2014-04-16 09:54:21 +0200196void tegra_dc_enable_vblank(struct tegra_dc *dc);
197void tegra_dc_disable_vblank(struct tegra_dc *dc);
Thierry Reding62b9e062014-11-21 17:33:33 +0100198void tegra_dc_commit(struct tegra_dc *dc);
Thierry Redingca915b12014-12-08 16:14:45 +0100199int tegra_dc_state_setup_clock(struct tegra_dc *dc,
200 struct drm_crtc_state *crtc_state,
201 struct clk *clk, unsigned long pclk,
202 unsigned int div);
Thierry Redingf34bc782012-11-04 21:47:13 +0100203
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000204struct tegra_output {
205 struct device_node *of_node;
206 struct device *dev;
207
Thierry Reding9be7d862013-08-30 15:22:36 +0200208 struct drm_panel *panel;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000209 struct i2c_adapter *ddc;
210 const struct edid *edid;
211 unsigned int hpd_irq;
212 int hpd_gpio;
Thierry Redingfb36d0ee2015-04-27 15:12:39 +0200213 enum of_gpio_flags hpd_gpio_flags;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000214
215 struct drm_encoder encoder;
216 struct drm_connector connector;
217};
218
219static inline struct tegra_output *encoder_to_output(struct drm_encoder *e)
220{
221 return container_of(e, struct tegra_output, encoder);
222}
223
224static inline struct tegra_output *connector_to_output(struct drm_connector *c)
225{
226 return container_of(c, struct tegra_output, connector);
227}
228
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000229/* from rgb.c */
Thierry Reding688c59a2014-04-16 09:54:21 +0200230int tegra_dc_rgb_probe(struct tegra_dc *dc);
231int tegra_dc_rgb_remove(struct tegra_dc *dc);
232int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
233int tegra_dc_rgb_exit(struct tegra_dc *dc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000234
235/* from output.c */
Thierry Reding688c59a2014-04-16 09:54:21 +0200236int tegra_output_probe(struct tegra_output *output);
Thierry Reding328ec692014-12-19 15:55:08 +0100237void tegra_output_remove(struct tegra_output *output);
Thierry Reding688c59a2014-04-16 09:54:21 +0200238int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
Thierry Reding328ec692014-12-19 15:55:08 +0100239void tegra_output_exit(struct tegra_output *output);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000240
Thierry Reding132085d2014-11-28 15:38:40 +0100241int tegra_output_connector_get_modes(struct drm_connector *connector);
242struct drm_encoder *
243tegra_output_connector_best_encoder(struct drm_connector *connector);
244enum drm_connector_status
245tegra_output_connector_detect(struct drm_connector *connector, bool force);
246void tegra_output_connector_destroy(struct drm_connector *connector);
247
248void tegra_output_encoder_destroy(struct drm_encoder *encoder);
249
Thierry Reding6b6b6042013-11-15 16:06:05 +0100250/* from dpaux.c */
Thierry Reding6b6b6042013-11-15 16:06:05 +0100251struct drm_dp_link;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100252
Thierry Reding9542c232015-07-08 13:39:09 +0200253struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np);
254enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux);
255int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output);
256int drm_dp_aux_detach(struct drm_dp_aux *aux);
257int drm_dp_aux_enable(struct drm_dp_aux *aux);
258int drm_dp_aux_disable(struct drm_dp_aux *aux);
259int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding);
260int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
261 u8 pattern);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100262
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000263/* from fb.c */
Arto Merilainende2ba662013-03-22 16:34:08 +0200264struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
265 unsigned int index);
Thierry Redingdb7fbdf2013-10-07 09:47:58 +0200266bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
Thierry Redingc134f012014-06-03 14:48:12 +0200267int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
268 struct tegra_bo_tiling *tiling);
Thierry Redingf9914212014-11-26 13:03:57 +0100269struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
270 struct drm_file *file,
Ville Syrjälä1eb83452015-11-11 19:11:29 +0200271 const struct drm_mode_fb_cmd2 *cmd);
Thierry Redinge2215322014-06-27 17:19:25 +0200272int tegra_drm_fb_prepare(struct drm_device *drm);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100273void tegra_drm_fb_free(struct drm_device *drm);
Thierry Reding688c59a2014-04-16 09:54:21 +0200274int tegra_drm_fb_init(struct drm_device *drm);
275void tegra_drm_fb_exit(struct drm_device *drm);
Thierry Reding986c58d2015-08-11 13:11:49 +0200276void tegra_drm_fb_suspend(struct drm_device *drm);
277void tegra_drm_fb_resume(struct drm_device *drm);
Archit Tanejab110ef32015-10-27 13:40:59 +0530278#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding688c59a2014-04-16 09:54:21 +0200279void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
Thierry Redingf9914212014-11-26 13:03:57 +0100280void tegra_fb_output_poll_changed(struct drm_device *drm);
Thierry Reding60c2f702013-10-31 13:28:50 +0100281#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000282
Thierry Reding776dc382013-10-14 14:43:22 +0200283extern struct platform_driver tegra_dc_driver;
284extern struct platform_driver tegra_hdmi_driver;
Thierry Reding473112e2015-09-10 16:07:14 +0200285extern struct platform_driver tegra_dsi_driver;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100286extern struct platform_driver tegra_dpaux_driver;
Thierry Reding473112e2015-09-10 16:07:14 +0200287extern struct platform_driver tegra_sor_driver;
Thierry Reding776dc382013-10-14 14:43:22 +0200288extern struct platform_driver tegra_gr2d_driver;
Thierry Reding5f60ed02013-02-28 08:08:01 +0100289extern struct platform_driver tegra_gr3d_driver;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000290
Terje Bergstrom4231c6b2013-03-22 16:34:05 +0200291#endif /* HOST1X_DRM_H */