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gerrit-public.fairphone.software / kernel / msm-5.4 / b24413180f5600bcb3bb70fbed5cf186b60864bd / . / arch / powerpc / include / asm / timex.h
blob: 926b9f91a3ef26f6fbbab910586d8ba165a0d0d9 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0 */
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]2#ifndef _ASM_POWERPC_TIMEX_H
3#define _ASM_POWERPC_TIMEX_H
4
5#ifdef __KERNEL__
6
7/*
8 * PowerPC architecture timex specifications
9 */
10
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]11#include <asm/cputable.h>
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]12#include <asm/reg.h>
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]13
Benjamin Herrenschmidtcbd27b82005-10-12 11:39:33 +1000[diff] [blame]14#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]15
16typedef unsigned long cycles_t;
17
18static inline cycles_t get_cycles(void)
19{
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]20#ifdef __powerpc64__
21 return mftb();
22#else
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]23 cycles_t ret;
24
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]25 /*
26 * For the "cycle" counter we use the timebase lower half.
27 * Currently only used on SMP.
28 */
29
30 ret = 0;
31
32 __asm__ __volatile__(
Christophe Leroy968159c2017-08-08 13:58:54 +0200[diff] [blame]33#ifdef CONFIG_PPC_8xx
LEROY Christopheae2163b2013-11-22 17:57:31 +0100[diff] [blame]34 "97: mftb %0\n"
35#else
Scott Woodbeb2dc02013-08-20 19:33:12 -0500[diff] [blame]36 "97: mfspr %0, %2\n"
LEROY Christopheae2163b2013-11-22 17:57:31 +0100[diff] [blame]37#endif
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]38 "99:\n"
39 ".section __ftr_fixup,\"a\"\n"
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]40 ".align 2\n"
41 "98:\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]42 " .long %1\n"
43 " .long 0\n"
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]44 " .long 97b-98b\n"
45 " .long 99b-98b\n"
Michael Ellermanfac23fe2008-06-24 11:32:54 +1000[diff] [blame]46 " .long 0\n"
47 " .long 0\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]48 ".previous"
Scott Woodbeb2dc02013-08-20 19:33:12 -0500[diff] [blame]49 : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]50 return ret;
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]51#endif
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -0500[diff] [blame]52}
53
54#endif /* __KERNEL__ */
55#endif /* _ASM_POWERPC_TIMEX_H */