blob: e61aa1f442ff5b1db1b60f23923791910d1ab5ce [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -07001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Mark Rustad14438462014-02-28 15:48:57 -08004 Copyright(c) 1999 - 2014 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Jacob Kellerb89aae72014-02-22 01:23:50 +000023 Linux NICS <linux.nics@intel.com>
Auke Kok9a799d72007-09-15 14:07:45 -070024 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
Stephen Hemminger9c8eb722007-10-29 10:46:24 -070033#include "ixgbe.h"
Auke Kok9a799d72007-09-15 14:07:45 -070034#include "ixgbe_phy.h"
35
36#define IXGBE_82598_MAX_TX_QUEUES 32
37#define IXGBE_82598_MAX_RX_QUEUES 64
38#define IXGBE_82598_RAR_ENTRIES 16
Christopher Leech2c5645c2008-08-26 04:27:02 -070039#define IXGBE_82598_MC_TBL_SIZE 128
40#define IXGBE_82598_VFT_TBL_SIZE 128
John Fastabende09ad232011-04-04 04:29:41 +000041#define IXGBE_82598_RX_PB_SIZE 512
Auke Kok9a799d72007-09-15 14:07:45 -070042
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000043static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
Mallikarjuna R Chilakala21ce8492010-05-13 17:33:41 +000044 ixgbe_link_speed speed,
Mallikarjuna R Chilakala21ce8492010-05-13 17:33:41 +000045 bool autoneg_wait_to_complete);
Donald Skidmorec4900be2008-11-20 21:11:42 -080046static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
47 u8 *eeprom_data);
Auke Kok9a799d72007-09-15 14:07:45 -070048
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070049/**
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000050 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
51 * @hw: pointer to the HW structure
52 *
53 * The defaults for 82598 should be in the range of 50us to 50ms,
54 * however the hardware default for these parts is 500us to 1ms which is less
55 * than the 10ms recommended by the pci-e spec. To address this we need to
56 * increase the value to either 10ms to 250ms for capability version 1 config,
57 * or 16ms to 55ms for version 2.
58 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +000059static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000060{
61 struct ixgbe_adapter *adapter = hw->back;
62 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
63 u16 pcie_devctl2;
64
Mark Rustad14438462014-02-28 15:48:57 -080065 if (ixgbe_removed(hw->hw_addr))
66 return;
67
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000068 /* only take action if timeout value is defaulted to 0 */
69 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
70 goto out;
71
72 /*
73 * if capababilities version is type 1 we can write the
74 * timeout of 10ms to 250ms through the GCR register
75 */
76 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
77 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
78 goto out;
79 }
80
81 /*
82 * for version 2 capabilities we need to write the config space
83 * directly in order to set the completion timeout value for
84 * 16ms to 55ms
85 */
Mark Rustad14438462014-02-28 15:48:57 -080086 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
87 if (ixgbe_removed(hw->hw_addr))
88 return;
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000089 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
90 pci_write_config_word(adapter->pdev,
91 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
92out:
93 /* disable completion timeout resend */
94 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
95 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
96}
97
Auke Kok9a799d72007-09-15 14:07:45 -070098static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
99{
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700100 struct ixgbe_mac_info *mac = &hw->mac;
PJ Waskiewicz03cfa202009-03-19 01:23:29 +0000101
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700102 /* Call PHY identify routine to get the phy type */
103 ixgbe_identify_phy_generic(hw);
Auke Kok3957d632007-10-31 15:22:10 -0700104
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000105 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
106 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
107 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
Jacob Keller6997d4d2014-02-22 01:23:49 +0000108 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000109 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
110 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
Emil Tantilov71161302012-03-22 03:00:29 +0000111 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000112
113 return 0;
114}
115
116/**
117 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
118 * @hw: pointer to hardware structure
119 *
120 * Initialize any function pointers that were not able to be
121 * set during get_invariants because the PHY/SFP type was
122 * not known. Perform the SFP init if necessary.
123 *
124 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000125static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000126{
127 struct ixgbe_mac_info *mac = &hw->mac;
128 struct ixgbe_phy_info *phy = &hw->phy;
129 s32 ret_val = 0;
130 u16 list_offset, data_offset;
131
132 /* Identify the PHY */
133 phy->ops.identify(hw);
134
135 /* Overwrite the link function pointers if copper PHY */
136 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
137 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000138 mac->ops.get_link_capabilities =
Don Skidmorea391f1d2010-11-16 19:27:15 -0800139 &ixgbe_get_copper_link_capabilities_generic;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000140 }
141
142 switch (hw->phy.type) {
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700143 case ixgbe_phy_tn:
Emil Tantilov9dda1732011-03-05 01:28:07 +0000144 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700145 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
146 phy->ops.get_firmware_version =
147 &ixgbe_get_phy_firmware_version_tnx;
148 break;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800149 case ixgbe_phy_nl:
150 phy->ops.reset = &ixgbe_reset_phy_nl;
151
152 /* Call SFP+ identify routine to get the SFP+ module type */
153 ret_val = phy->ops.identify_sfp(hw);
154 if (ret_val != 0)
155 goto out;
156 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
157 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
158 goto out;
159 }
160
161 /* Check to see if SFP+ module is supported */
162 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000163 &list_offset,
164 &data_offset);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800165 if (ret_val != 0) {
166 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
167 goto out;
168 }
169 break;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700170 default:
171 break;
Auke Kok3957d632007-10-31 15:22:10 -0700172 }
173
Donald Skidmorec4900be2008-11-20 21:11:42 -0800174out:
175 return ret_val;
Auke Kok9a799d72007-09-15 14:07:45 -0700176}
177
178/**
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000179 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
180 * @hw: pointer to hardware structure
181 *
182 * Starts the hardware using the generic start_hw function.
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000183 * Disables relaxed ordering Then set pcie completion timeout
184 *
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000185 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000186static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000187{
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000188 u32 regval;
189 u32 i;
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000190 s32 ret_val = 0;
191
192 ret_val = ixgbe_start_hw_generic(hw);
193
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000194 /* Disable relaxed ordering */
195 for (i = 0; ((i < hw->mac.max_tx_queues) &&
196 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
197 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
Alexander Duyckbdda1a62012-02-08 07:50:14 +0000198 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000199 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
200 }
201
202 for (i = 0; ((i < hw->mac.max_rx_queues) &&
203 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
204 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
Alexander Duyckbdda1a62012-02-08 07:50:14 +0000205 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
206 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000207 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
208 }
209
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000210 /* set the completion timeout for interface */
211 if (ret_val == 0)
212 ixgbe_set_pcie_completion_timeout(hw);
213
214 return ret_val;
215}
216
217/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700218 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
Auke Kok9a799d72007-09-15 14:07:45 -0700219 * @hw: pointer to hardware structure
220 * @speed: pointer to link speed
221 * @autoneg: boolean auto-negotiation value
222 *
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700223 * Determines the link capabilities by reading the AUTOC register.
Auke Kok9a799d72007-09-15 14:07:45 -0700224 **/
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700225static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700226 ixgbe_link_speed *speed,
227 bool *autoneg)
Auke Kok9a799d72007-09-15 14:07:45 -0700228{
229 s32 status = 0;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000230 u32 autoc = 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700231
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800232 /*
233 * Determine link capabilities based on the stored value of AUTOC,
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000234 * which represents EEPROM defaults. If AUTOC value has not been
235 * stored, use the current register value.
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800236 */
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000237 if (hw->mac.orig_link_settings_stored)
238 autoc = hw->mac.orig_autoc;
239 else
240 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
241
242 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
Auke Kok9a799d72007-09-15 14:07:45 -0700243 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
244 *speed = IXGBE_LINK_SPEED_1GB_FULL;
245 *autoneg = false;
246 break;
247
248 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
249 *speed = IXGBE_LINK_SPEED_10GB_FULL;
250 *autoneg = false;
251 break;
252
253 case IXGBE_AUTOC_LMS_1G_AN:
254 *speed = IXGBE_LINK_SPEED_1GB_FULL;
255 *autoneg = true;
256 break;
257
258 case IXGBE_AUTOC_LMS_KX4_AN:
259 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
260 *speed = IXGBE_LINK_SPEED_UNKNOWN;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000261 if (autoc & IXGBE_AUTOC_KX4_SUPP)
Auke Kok9a799d72007-09-15 14:07:45 -0700262 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000263 if (autoc & IXGBE_AUTOC_KX_SUPP)
Auke Kok9a799d72007-09-15 14:07:45 -0700264 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
265 *autoneg = true;
266 break;
267
268 default:
269 status = IXGBE_ERR_LINK_SETUP;
270 break;
271 }
272
273 return status;
274}
275
276/**
Auke Kok9a799d72007-09-15 14:07:45 -0700277 * ixgbe_get_media_type_82598 - Determines media type
278 * @hw: pointer to hardware structure
279 *
280 * Returns the media type (fiber, copper, backplane)
281 **/
282static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
283{
284 enum ixgbe_media_type media_type;
285
Emil Tantilov037c6d02011-02-25 07:49:39 +0000286 /* Detect if there is a copper PHY attached. */
287 switch (hw->phy.type) {
288 case ixgbe_phy_cu_unknown:
289 case ixgbe_phy_tn:
Emil Tantilov037c6d02011-02-25 07:49:39 +0000290 media_type = ixgbe_media_type_copper;
291 goto out;
292 default:
293 break;
294 }
295
Auke Kok9a799d72007-09-15 14:07:45 -0700296 /* Media type for I82598 is based on device ID */
297 switch (hw->device_id) {
Don Skidmore1e336d02009-01-26 20:57:51 -0800298 case IXGBE_DEV_ID_82598:
Don Skidmore2f21bdd2009-02-01 01:18:23 -0800299 case IXGBE_DEV_ID_82598_BX:
Emil Tantilov037c6d02011-02-25 07:49:39 +0000300 /* Default device ID is mezzanine card KX/KX4 */
Don Skidmore1e336d02009-01-26 20:57:51 -0800301 media_type = ixgbe_media_type_backplane;
302 break;
Auke Kok9a799d72007-09-15 14:07:45 -0700303 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
304 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
Donald Skidmorec4900be2008-11-20 21:11:42 -0800305 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
306 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
Jesse Brandeburgb95f5fc2008-09-11 19:58:59 -0700307 case IXGBE_DEV_ID_82598EB_XF_LR:
Donald Skidmorec4900be2008-11-20 21:11:42 -0800308 case IXGBE_DEV_ID_82598EB_SFP_LOM:
Auke Kok9a799d72007-09-15 14:07:45 -0700309 media_type = ixgbe_media_type_fiber;
310 break;
Peter P Waskiewicz Jr6b1be192009-09-14 07:48:10 +0000311 case IXGBE_DEV_ID_82598EB_CX4:
312 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
313 media_type = ixgbe_media_type_cx4;
314 break;
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700315 case IXGBE_DEV_ID_82598AT:
Peter P Waskiewicz Jr3845bec2009-07-16 15:50:52 +0000316 case IXGBE_DEV_ID_82598AT2:
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700317 media_type = ixgbe_media_type_copper;
318 break;
Auke Kok9a799d72007-09-15 14:07:45 -0700319 default:
320 media_type = ixgbe_media_type_unknown;
321 break;
322 }
Emil Tantilov037c6d02011-02-25 07:49:39 +0000323out:
Auke Kok9a799d72007-09-15 14:07:45 -0700324 return media_type;
325}
326
327/**
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800328 * ixgbe_fc_enable_82598 - Enable flow control
329 * @hw: pointer to hardware structure
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800330 *
331 * Enable flow control according to the current settings.
332 **/
Alexander Duyck041441d2012-04-19 17:48:48 +0000333static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800334{
335 s32 ret_val = 0;
336 u32 fctrl_reg;
337 u32 rmcs_reg;
338 u32 reg;
Alexander Duyck041441d2012-04-19 17:48:48 +0000339 u32 fcrtl, fcrth;
Don Skidmorea626e842010-02-11 04:13:49 +0000340 u32 link_speed = 0;
Alexander Duyck041441d2012-04-19 17:48:48 +0000341 int i;
Don Skidmorea626e842010-02-11 04:13:49 +0000342 bool link_up;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800343
Alexander Duyck041441d2012-04-19 17:48:48 +0000344 /*
345 * Validate the water mark configuration for packet buffer 0. Zero
346 * water marks indicate that the packet buffer was not configured
347 * and the watermarks for packet buffer 0 should always be configured.
348 */
349 if (!hw->fc.low_water ||
350 !hw->fc.high_water[0] ||
351 !hw->fc.pause_time) {
352 hw_dbg(hw, "Invalid water mark configuration\n");
353 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000354 goto out;
Alexander Duyck041441d2012-04-19 17:48:48 +0000355 }
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000356
Don Skidmorea626e842010-02-11 04:13:49 +0000357 /*
358 * On 82598 having Rx FC on causes resets while doing 1G
359 * so if it's on turn it off once we know link_speed. For
360 * more details see 82598 Specification update.
361 */
362 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
363 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
364 switch (hw->fc.requested_mode) {
365 case ixgbe_fc_full:
366 hw->fc.requested_mode = ixgbe_fc_tx_pause;
367 break;
368 case ixgbe_fc_rx_pause:
369 hw->fc.requested_mode = ixgbe_fc_none;
370 break;
371 default:
372 /* no change */
373 break;
374 }
375 }
376
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000377 /* Negotiate the fc mode to use */
Alexander Duyck786e9a52012-03-28 08:03:48 +0000378 ixgbe_fc_autoneg(hw);
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000379
380 /* Disable any previous flow control settings */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800381 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
382 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
383
384 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
385 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
386
387 /*
388 * The possible values of fc.current_mode are:
389 * 0: Flow control is completely disabled
390 * 1: Rx flow control is enabled (we can receive pause frames,
391 * but not send pause frames).
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000392 * 2: Tx flow control is enabled (we can send pause frames but
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800393 * we do not support receiving pause frames).
394 * 3: Both Rx and Tx flow control (symmetric) are enabled.
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000395 * other: Invalid.
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800396 */
397 switch (hw->fc.current_mode) {
398 case ixgbe_fc_none:
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000399 /*
400 * Flow control is disabled by software override or autoneg.
401 * The code below will actually disable it in the HW.
402 */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800403 break;
404 case ixgbe_fc_rx_pause:
405 /*
406 * Rx Flow control is enabled and Tx Flow control is
407 * disabled by software override. Since there really
408 * isn't a way to advertise that we are capable of RX
409 * Pause ONLY, we will advertise that we support both
410 * symmetric and asymmetric Rx PAUSE. Later, we will
411 * disable the adapter's ability to send PAUSE frames.
412 */
413 fctrl_reg |= IXGBE_FCTRL_RFCE;
414 break;
415 case ixgbe_fc_tx_pause:
416 /*
417 * Tx Flow control is enabled, and Rx Flow control is
418 * disabled by software override.
419 */
420 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
421 break;
422 case ixgbe_fc_full:
423 /* Flow control (both Rx and Tx) is enabled by SW override. */
424 fctrl_reg |= IXGBE_FCTRL_RFCE;
425 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
426 break;
427 default:
428 hw_dbg(hw, "Flow control param set incorrectly\n");
Peter P Waskiewicz Jr539e5f02009-09-30 12:07:38 +0000429 ret_val = IXGBE_ERR_CONFIG;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800430 goto out;
431 break;
432 }
433
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000434 /* Set 802.3x based flow control settings. */
PJ Waskiewicz2132d382009-04-09 22:26:21 +0000435 fctrl_reg |= IXGBE_FCTRL_DPF;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800436 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
437 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
438
Alexander Duyck041441d2012-04-19 17:48:48 +0000439 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
440
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800441 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
Alexander Duyck041441d2012-04-19 17:48:48 +0000442 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
443 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
444 hw->fc.high_water[i]) {
445 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
446 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
447 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
448 } else {
449 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
450 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
451 }
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000452
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800453 }
454
455 /* Configure pause time (2 TCs per register) */
Alexander Duyck041441d2012-04-19 17:48:48 +0000456 reg = hw->fc.pause_time * 0x00010001;
457 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
458 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800459
Alexander Duyck041441d2012-04-19 17:48:48 +0000460 /* Configure flow control refresh threshold value */
461 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800462
463out:
464 return ret_val;
465}
466
467/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000468 * ixgbe_start_mac_link_82598 - Configures MAC link settings
Auke Kok9a799d72007-09-15 14:07:45 -0700469 * @hw: pointer to hardware structure
470 *
471 * Configures link settings based on values in the ixgbe_hw struct.
472 * Restarts the link. Performs autonegotiation if needed.
473 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000474static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
475 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700476{
477 u32 autoc_reg;
478 u32 links_reg;
479 u32 i;
480 s32 status = 0;
481
Auke Kok9a799d72007-09-15 14:07:45 -0700482 /* Restart link */
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800483 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
Auke Kok9a799d72007-09-15 14:07:45 -0700484 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
485 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
486
487 /* Only poll for autoneg to complete if specified to do so */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000488 if (autoneg_wait_to_complete) {
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800489 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
490 IXGBE_AUTOC_LMS_KX4_AN ||
491 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
492 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
Auke Kok9a799d72007-09-15 14:07:45 -0700493 links_reg = 0; /* Just in case Autoneg time = 0 */
494 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
495 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
496 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
497 break;
498 msleep(100);
499 }
500 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
501 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700502 hw_dbg(hw, "Autonegotiation did not complete.\n");
Auke Kok9a799d72007-09-15 14:07:45 -0700503 }
504 }
505 }
506
Auke Kok9a799d72007-09-15 14:07:45 -0700507 /* Add delay to filter out noises during initial link setup */
508 msleep(50);
509
510 return status;
511}
512
513/**
Mallikarjuna R Chilakala734e9792009-12-15 11:57:20 +0000514 * ixgbe_validate_link_ready - Function looks for phy link
515 * @hw: pointer to hardware structure
516 *
517 * Function indicates success when phy link is available. If phy is not ready
518 * within 5 seconds of MAC indicating link, the function returns error.
519 **/
520static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
521{
522 u32 timeout;
523 u16 an_reg;
524
525 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
526 return 0;
527
528 for (timeout = 0;
529 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
530 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
531
532 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
533 (an_reg & MDIO_STAT1_LSTATUS))
534 break;
535
536 msleep(100);
537 }
538
539 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
540 hw_dbg(hw, "Link was indicated but link is down\n");
541 return IXGBE_ERR_LINK_SETUP;
542 }
543
544 return 0;
545}
546
547/**
Auke Kok9a799d72007-09-15 14:07:45 -0700548 * ixgbe_check_mac_link_82598 - Get link/speed status
549 * @hw: pointer to hardware structure
550 * @speed: pointer to link speed
551 * @link_up: true is link is up, false otherwise
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700552 * @link_up_wait_to_complete: bool used to wait for link up or not
Auke Kok9a799d72007-09-15 14:07:45 -0700553 *
554 * Reads the links register to determine if link is up and the current speed
555 **/
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700556static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
557 ixgbe_link_speed *speed, bool *link_up,
558 bool link_up_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700559{
560 u32 links_reg;
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700561 u32 i;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800562 u16 link_reg, adapt_comp_reg;
563
564 /*
565 * SERDES PHY requires us to read link status from register 0xC79F.
566 * Bit 0 set indicates link is up/ready; clear indicates link down.
567 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
568 * clear indicates active; set indicates inactive.
569 */
570 if (hw->phy.type == ixgbe_phy_nl) {
Ben Hutchings6b73e102009-04-29 08:08:58 +0000571 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
572 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
573 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -0800574 &adapt_comp_reg);
575 if (link_up_wait_to_complete) {
576 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
577 if ((link_reg & 1) &&
578 ((adapt_comp_reg & 1) == 0)) {
579 *link_up = true;
580 break;
581 } else {
582 *link_up = false;
583 }
584 msleep(100);
585 hw->phy.ops.read_reg(hw, 0xC79F,
Ben Hutchings6b73e102009-04-29 08:08:58 +0000586 MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -0800587 &link_reg);
588 hw->phy.ops.read_reg(hw, 0xC00C,
Ben Hutchings6b73e102009-04-29 08:08:58 +0000589 MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -0800590 &adapt_comp_reg);
591 }
592 } else {
593 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
594 *link_up = true;
595 else
596 *link_up = false;
597 }
598
Joe Perches23677ce2012-02-09 11:17:23 +0000599 if (!*link_up)
Donald Skidmorec4900be2008-11-20 21:11:42 -0800600 goto out;
601 }
Auke Kok9a799d72007-09-15 14:07:45 -0700602
603 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700604 if (link_up_wait_to_complete) {
605 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
606 if (links_reg & IXGBE_LINKS_UP) {
607 *link_up = true;
608 break;
609 } else {
610 *link_up = false;
611 }
612 msleep(100);
613 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
614 }
615 } else {
616 if (links_reg & IXGBE_LINKS_UP)
617 *link_up = true;
618 else
619 *link_up = false;
620 }
Auke Kok9a799d72007-09-15 14:07:45 -0700621
622 if (links_reg & IXGBE_LINKS_SPEED)
623 *speed = IXGBE_LINK_SPEED_10GB_FULL;
624 else
625 *speed = IXGBE_LINK_SPEED_1GB_FULL;
626
Joe Perches23677ce2012-02-09 11:17:23 +0000627 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
Mallikarjuna R Chilakala734e9792009-12-15 11:57:20 +0000628 (ixgbe_validate_link_ready(hw) != 0))
629 *link_up = false;
630
Donald Skidmorec4900be2008-11-20 21:11:42 -0800631out:
Auke Kok9a799d72007-09-15 14:07:45 -0700632 return 0;
633}
634
635/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000636 * ixgbe_setup_mac_link_82598 - Set MAC link speed
Auke Kok9a799d72007-09-15 14:07:45 -0700637 * @hw: pointer to hardware structure
638 * @speed: new link speed
Emil Tantilov037c6d02011-02-25 07:49:39 +0000639 * @autoneg_wait_to_complete: true when waiting for completion is needed
Auke Kok9a799d72007-09-15 14:07:45 -0700640 *
641 * Set the link speed in the AUTOC register and restarts link.
642 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000643static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
Josh Hayfd0326f2012-12-15 03:28:30 +0000644 ixgbe_link_speed speed,
645 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700646{
Josh Hayfd0326f2012-12-15 03:28:30 +0000647 bool autoneg = false;
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800648 s32 status = 0;
649 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
650 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
651 u32 autoc = curr_autoc;
652 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
Auke Kok9a799d72007-09-15 14:07:45 -0700653
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800654 /* Check to see if speed passed in is supported. */
655 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
656 speed &= link_capabilities;
657
658 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
Auke Kok9a799d72007-09-15 14:07:45 -0700659 status = IXGBE_ERR_LINK_SETUP;
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800660
661 /* Set KX4/KX support according to speed requested */
662 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
663 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
664 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
665 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
666 autoc |= IXGBE_AUTOC_KX4_SUPP;
667 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
668 autoc |= IXGBE_AUTOC_KX_SUPP;
669 if (autoc != curr_autoc)
670 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
Auke Kok9a799d72007-09-15 14:07:45 -0700671 }
672
673 if (status == 0) {
Auke Kok9a799d72007-09-15 14:07:45 -0700674 /*
675 * Setup and restart the link based on the new values in
676 * ixgbe_hw This will write the AUTOC register based on the new
677 * stored values
678 */
Emil Tantilov037c6d02011-02-25 07:49:39 +0000679 status = ixgbe_start_mac_link_82598(hw,
680 autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700681 }
682
683 return status;
684}
685
686
687/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000688 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
Auke Kok9a799d72007-09-15 14:07:45 -0700689 * @hw: pointer to hardware structure
690 * @speed: new link speed
Auke Kok9a799d72007-09-15 14:07:45 -0700691 * @autoneg_wait_to_complete: true if waiting is needed to complete
692 *
693 * Sets the link speed in the AUTOC register in the MAC and restarts link.
694 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000695static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700696 ixgbe_link_speed speed,
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700697 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700698{
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700699 s32 status;
Auke Kok9a799d72007-09-15 14:07:45 -0700700
701 /* Setup the PHY according to input speed */
Josh Hay99b76642012-12-15 03:28:24 +0000702 status = hw->phy.ops.setup_link_speed(hw, speed,
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700703 autoneg_wait_to_complete);
Auke Kok3957d632007-10-31 15:22:10 -0700704 /* Set up MAC */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000705 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700706
707 return status;
708}
709
710/**
711 * ixgbe_reset_hw_82598 - Performs hardware reset
712 * @hw: pointer to hardware structure
713 *
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700714 * Resets the hardware by resetting the transmit and receive units, masks and
Auke Kok9a799d72007-09-15 14:07:45 -0700715 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
716 * reset.
717 **/
718static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
719{
720 s32 status = 0;
Don Skidmore8ca783a2009-05-26 20:40:47 -0700721 s32 phy_status = 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700722 u32 ctrl;
723 u32 gheccr;
724 u32 i;
725 u32 autoc;
726 u8 analog_val;
727
728 /* Call adapter stop to disable tx/rx and clear interrupts */
Emil Tantilovff9d1a52011-08-16 04:35:11 +0000729 status = hw->mac.ops.stop_adapter(hw);
730 if (status != 0)
731 goto reset_hw_out;
Auke Kok9a799d72007-09-15 14:07:45 -0700732
733 /*
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700734 * Power up the Atlas Tx lanes if they are currently powered down.
735 * Atlas Tx lanes are powered down for MAC loopback tests, but
Auke Kok9a799d72007-09-15 14:07:45 -0700736 * they are not automatically restored on reset.
737 */
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700738 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700739 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700740 /* Enable Tx Atlas so packets can be transmitted again */
741 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
742 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700743 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700744 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
745 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700746
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700747 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
748 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700749 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700750 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
751 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700752
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700753 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
754 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700755 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700756 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
757 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700758
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700759 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
760 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700761 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700762 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
763 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700764 }
765
766 /* Reset PHY */
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000767 if (hw->phy.reset_disable == false) {
768 /* PHY ops must be identified and initialized prior to reset */
769
770 /* Init PHY and function pointers, perform SFP setup */
Don Skidmore8ca783a2009-05-26 20:40:47 -0700771 phy_status = hw->phy.ops.init(hw);
772 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000773 goto reset_hw_out;
Emil Tantilovff9d1a52011-08-16 04:35:11 +0000774 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
775 goto mac_reset_top;
Don Skidmore8ca783a2009-05-26 20:40:47 -0700776
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700777 hw->phy.ops.reset(hw);
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000778 }
Auke Kok9a799d72007-09-15 14:07:45 -0700779
Emil Tantilova4297dc2011-02-14 08:45:13 +0000780mac_reset_top:
Auke Kok9a799d72007-09-15 14:07:45 -0700781 /*
782 * Issue global reset to the MAC. This needs to be a SW reset.
783 * If link reset is used, it might reset the MAC when mng is using it
784 */
Alexander Duyck8132b542011-07-15 07:29:44 +0000785 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
786 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
Auke Kok9a799d72007-09-15 14:07:45 -0700787 IXGBE_WRITE_FLUSH(hw);
788
789 /* Poll for reset bit to self-clear indicating reset is complete */
790 for (i = 0; i < 10; i++) {
791 udelay(1);
792 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
793 if (!(ctrl & IXGBE_CTRL_RST))
794 break;
795 }
796 if (ctrl & IXGBE_CTRL_RST) {
797 status = IXGBE_ERR_RESET_FAILED;
798 hw_dbg(hw, "Reset polling failed to complete.\n");
799 }
800
Alexander Duyck8132b542011-07-15 07:29:44 +0000801 msleep(50);
802
Emil Tantilova4297dc2011-02-14 08:45:13 +0000803 /*
804 * Double resets are required for recovery from certain error
805 * conditions. Between resets, it is necessary to stall to allow time
Alexander Duyck8132b542011-07-15 07:29:44 +0000806 * for any pending HW events to complete.
Emil Tantilova4297dc2011-02-14 08:45:13 +0000807 */
808 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
809 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
Emil Tantilova4297dc2011-02-14 08:45:13 +0000810 goto mac_reset_top;
811 }
812
Auke Kok9a799d72007-09-15 14:07:45 -0700813 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
814 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
815 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
816
817 /*
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800818 * Store the original AUTOC value if it has not been
819 * stored off yet. Otherwise restore the stored original
820 * AUTOC value since the reset operation sets back to deaults.
Auke Kok9a799d72007-09-15 14:07:45 -0700821 */
822 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800823 if (hw->mac.orig_link_settings_stored == false) {
824 hw->mac.orig_autoc = autoc;
825 hw->mac.orig_link_settings_stored = true;
826 } else if (autoc != hw->mac.orig_autoc) {
827 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
Auke Kok9a799d72007-09-15 14:07:45 -0700828 }
829
Emil Tantilov278675d2011-02-19 08:43:49 +0000830 /* Store the permanent mac address */
831 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
832
Waskiewicz Jr, Peter Paca6bee2009-05-17 12:32:48 +0000833 /*
834 * Store MAC address from RAR0, clear receive address registers, and
835 * clear the multicast table
836 */
837 hw->mac.ops.init_rx_addrs(hw);
838
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000839reset_hw_out:
Don Skidmore8ca783a2009-05-26 20:40:47 -0700840 if (phy_status)
841 status = phy_status;
842
Auke Kok9a799d72007-09-15 14:07:45 -0700843 return status;
844}
845
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700846/**
847 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
848 * @hw: pointer to hardware struct
849 * @rar: receive address register index to associate with a VMDq index
850 * @vmdq: VMDq set index
851 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800852static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700853{
854 u32 rar_high;
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000855 u32 rar_entries = hw->mac.num_rar_entries;
856
857 /* Make sure we are using a valid rar index range */
858 if (rar >= rar_entries) {
859 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
860 return IXGBE_ERR_INVALID_ARGUMENT;
861 }
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700862
863 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
864 rar_high &= ~IXGBE_RAH_VIND_MASK;
865 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
866 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
867 return 0;
868}
869
870/**
871 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
872 * @hw: pointer to hardware struct
873 * @rar: receive address register index to associate with a VMDq index
874 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
875 **/
876static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
877{
878 u32 rar_high;
879 u32 rar_entries = hw->mac.num_rar_entries;
880
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000881
882 /* Make sure we are using a valid rar index range */
883 if (rar >= rar_entries) {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700884 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000885 return IXGBE_ERR_INVALID_ARGUMENT;
886 }
887
888 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
889 if (rar_high & IXGBE_RAH_VIND_MASK) {
890 rar_high &= ~IXGBE_RAH_VIND_MASK;
891 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700892 }
893
894 return 0;
895}
896
897/**
898 * ixgbe_set_vfta_82598 - Set VLAN filter table
899 * @hw: pointer to hardware structure
900 * @vlan: VLAN id to write to VLAN filter
901 * @vind: VMDq output index that maps queue to VLAN id in VFTA
902 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
903 *
904 * Turn on/off specified VLAN in the VLAN filter table.
905 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800906static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
907 bool vlan_on)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700908{
909 u32 regindex;
910 u32 bitindex;
911 u32 bits;
912 u32 vftabyte;
913
914 if (vlan > 4095)
915 return IXGBE_ERR_PARAM;
916
917 /* Determine 32-bit word position in array */
918 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
919
920 /* Determine the location of the (VMD) queue index */
921 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
922 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
923
924 /* Set the nibble for VMD queue index */
925 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
926 bits &= (~(0x0F << bitindex));
927 bits |= (vind << bitindex);
928 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
929
930 /* Determine the location of the bit for this VLAN id */
931 bitindex = vlan & 0x1F; /* lower five bits */
932
933 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
934 if (vlan_on)
935 /* Turn on this VLAN id */
936 bits |= (1 << bitindex);
937 else
938 /* Turn off this VLAN id */
939 bits &= ~(1 << bitindex);
940 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
941
942 return 0;
943}
944
945/**
946 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
947 * @hw: pointer to hardware structure
948 *
949 * Clears the VLAN filer table, and the VMDq index associated with the filter
950 **/
951static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
952{
953 u32 offset;
954 u32 vlanbyte;
955
956 for (offset = 0; offset < hw->mac.vft_size; offset++)
957 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
958
959 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
960 for (offset = 0; offset < hw->mac.vft_size; offset++)
961 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700962 0);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700963
964 return 0;
965}
966
967/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700968 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
969 * @hw: pointer to hardware structure
970 * @reg: analog register to read
971 * @val: read value
972 *
973 * Performs read operation to Atlas analog register specified.
974 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800975static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700976{
977 u32 atlas_ctl;
978
979 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
980 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
981 IXGBE_WRITE_FLUSH(hw);
982 udelay(10);
983 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
984 *val = (u8)atlas_ctl;
985
986 return 0;
987}
988
989/**
990 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
991 * @hw: pointer to hardware structure
992 * @reg: atlas register to write
993 * @val: value to write
994 *
995 * Performs write operation to Atlas analog register specified.
996 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800997static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700998{
999 u32 atlas_ctl;
1000
1001 atlas_ctl = (reg << 8) | val;
1002 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1003 IXGBE_WRITE_FLUSH(hw);
1004 udelay(10);
1005
1006 return 0;
1007}
1008
1009/**
Emil Tantilov07ce8702012-12-19 07:14:17 +00001010 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
Donald Skidmorec4900be2008-11-20 21:11:42 -08001011 * @hw: pointer to hardware structure
Emil Tantilov07ce8702012-12-19 07:14:17 +00001012 * @dev_addr: address to read from
1013 * @byte_offset: byte offset to read from dev_addr
Donald Skidmorec4900be2008-11-20 21:11:42 -08001014 * @eeprom_data: value read
1015 *
Emil Tantilov07ce8702012-12-19 07:14:17 +00001016 * Performs 8 byte read operation to SFP module's data over I2C interface.
Donald Skidmorec4900be2008-11-20 21:11:42 -08001017 **/
Emil Tantilov07ce8702012-12-19 07:14:17 +00001018static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
1019 u8 byte_offset, u8 *eeprom_data)
Donald Skidmorec4900be2008-11-20 21:11:42 -08001020{
1021 s32 status = 0;
1022 u16 sfp_addr = 0;
1023 u16 sfp_data = 0;
1024 u16 sfp_stat = 0;
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001025 u16 gssr;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001026 u32 i;
1027
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001028 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1029 gssr = IXGBE_GSSR_PHY1_SM;
1030 else
1031 gssr = IXGBE_GSSR_PHY0_SM;
1032
1033 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
1034 return IXGBE_ERR_SWFW_SYNC;
1035
Donald Skidmorec4900be2008-11-20 21:11:42 -08001036 if (hw->phy.type == ixgbe_phy_nl) {
1037 /*
1038 * phy SDA/SCL registers are at addresses 0xC30A to
1039 * 0xC30D. These registers are used to talk to the SFP+
1040 * module's EEPROM through the SDA/SCL (I2C) interface.
1041 */
Emil Tantilov07ce8702012-12-19 07:14:17 +00001042 sfp_addr = (dev_addr << 8) + byte_offset;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001043 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001044 hw->phy.ops.write_reg_mdi(hw,
1045 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1046 MDIO_MMD_PMAPMD,
1047 sfp_addr);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001048
1049 /* Poll status */
1050 for (i = 0; i < 100; i++) {
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001051 hw->phy.ops.read_reg_mdi(hw,
1052 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1053 MDIO_MMD_PMAPMD,
1054 &sfp_stat);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001055 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1056 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1057 break;
Don Skidmore032b4322011-03-18 09:32:53 +00001058 usleep_range(10000, 20000);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001059 }
1060
1061 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1062 hw_dbg(hw, "EEPROM read did not pass.\n");
1063 status = IXGBE_ERR_SFP_NOT_PRESENT;
1064 goto out;
1065 }
1066
1067 /* Read data */
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001068 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1069 MDIO_MMD_PMAPMD, &sfp_data);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001070
1071 *eeprom_data = (u8)(sfp_data >> 8);
1072 } else {
1073 status = IXGBE_ERR_PHY;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001074 }
1075
1076out:
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001077 hw->mac.ops.release_swfw_sync(hw, gssr);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001078 return status;
1079}
1080
1081/**
Emil Tantilov07ce8702012-12-19 07:14:17 +00001082 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1083 * @hw: pointer to hardware structure
1084 * @byte_offset: EEPROM byte offset to read
1085 * @eeprom_data: value read
1086 *
1087 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1088 **/
1089static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1090 u8 *eeprom_data)
1091{
1092 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1093 byte_offset, eeprom_data);
1094}
1095
1096/**
1097 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1098 * @hw: pointer to hardware structure
1099 * @byte_offset: byte offset at address 0xA2
1100 * @eeprom_data: value read
1101 *
1102 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1103 **/
1104static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1105 u8 *sff8472_data)
1106{
1107 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1108 byte_offset, sff8472_data);
1109}
1110
1111/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001112 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1113 * @hw: pointer to hardware structure
1114 *
1115 * Determines physical layer capabilities of the current configuration.
1116 **/
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001117static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001118{
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001119 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001120 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1121 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1122 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1123 u16 ext_ability = 0;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001124
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001125 hw->phy.ops.identify(hw);
1126
1127 /* Copper PHY must be checked before AUTOC LMS to determine correct
1128 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
Emil Tantilov037c6d02011-02-25 07:49:39 +00001129 switch (hw->phy.type) {
1130 case ixgbe_phy_tn:
Emil Tantilov037c6d02011-02-25 07:49:39 +00001131 case ixgbe_phy_cu_unknown:
1132 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE,
1133 MDIO_MMD_PMAPMD, &ext_ability);
Ben Hutchings6b73e102009-04-29 08:08:58 +00001134 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001135 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
Ben Hutchings6b73e102009-04-29 08:08:58 +00001136 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001137 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
Ben Hutchings6b73e102009-04-29 08:08:58 +00001138 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001139 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1140 goto out;
Emil Tantilov037c6d02011-02-25 07:49:39 +00001141 default:
1142 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001143 }
1144
1145 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1146 case IXGBE_AUTOC_LMS_1G_AN:
1147 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1148 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1149 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1150 else
1151 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
Don Skidmore1e336d02009-01-26 20:57:51 -08001152 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001153 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1154 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1155 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1156 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1157 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1158 else /* XAUI */
1159 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001160 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001161 case IXGBE_AUTOC_LMS_KX4_AN:
1162 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1163 if (autoc & IXGBE_AUTOC_KX_SUPP)
1164 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1165 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1166 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001167 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001168 default:
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001169 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001170 }
1171
1172 if (hw->phy.type == ixgbe_phy_nl) {
Donald Skidmorec4900be2008-11-20 21:11:42 -08001173 hw->phy.ops.identify_sfp(hw);
1174
1175 switch (hw->phy.sfp_type) {
1176 case ixgbe_sfp_type_da_cu:
1177 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1178 break;
1179 case ixgbe_sfp_type_sr:
1180 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1181 break;
1182 case ixgbe_sfp_type_lr:
1183 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1184 break;
1185 default:
1186 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1187 break;
1188 }
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001189 }
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001190
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001191 switch (hw->device_id) {
1192 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1193 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1194 break;
1195 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1196 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1197 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1198 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1199 break;
1200 case IXGBE_DEV_ID_82598EB_XF_LR:
1201 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1202 break;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001203 default:
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001204 break;
1205 }
1206
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001207out:
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001208 return physical_layer;
1209}
1210
Emil Tantilovc9130182011-03-16 01:55:55 +00001211/**
1212 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1213 * port devices.
1214 * @hw: pointer to the HW structure
1215 *
1216 * Calls common function and corrects issue with some single port devices
1217 * that enable LAN1 but not LAN0.
1218 **/
1219static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1220{
1221 struct ixgbe_bus_info *bus = &hw->bus;
1222 u16 pci_gen = 0;
1223 u16 pci_ctrl2 = 0;
1224
1225 ixgbe_set_lan_id_multi_port_pcie(hw);
1226
1227 /* check if LAN0 is disabled */
1228 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1229 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1230
1231 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1232
1233 /* if LAN0 is completely disabled force function to 0 */
1234 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1235 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1236 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1237
1238 bus->func = 0;
1239 }
1240 }
1241}
1242
John Fastabend80605c652011-05-02 12:34:10 +00001243/**
1244 * ixgbe_set_rxpba_82598 - Configure packet buffers
1245 * @hw: pointer to hardware structure
1246 * @dcb_config: pointer to ixgbe_dcb_config structure
1247 *
1248 * Configure packet buffers.
1249 */
1250static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,
1251 int strategy)
1252{
1253 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1254 u8 i = 0;
1255
1256 if (!num_pb)
1257 return;
1258
1259 /* Setup Rx packet buffer sizes */
1260 switch (strategy) {
1261 case PBA_STRATEGY_WEIGHTED:
1262 /* Setup the first four at 80KB */
1263 rxpktsize = IXGBE_RXPBSIZE_80KB;
1264 for (; i < 4; i++)
1265 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1266 /* Setup the last four at 48KB...don't re-init i */
1267 rxpktsize = IXGBE_RXPBSIZE_48KB;
1268 /* Fall Through */
1269 case PBA_STRATEGY_EQUAL:
1270 default:
1271 /* Divide the remaining Rx packet buffer evenly among the TCs */
1272 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1273 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1274 break;
1275 }
1276
1277 /* Setup Tx packet buffer sizes */
1278 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1279 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1280
1281 return;
1282}
1283
Auke Kok9a799d72007-09-15 14:07:45 -07001284static struct ixgbe_mac_operations mac_ops_82598 = {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001285 .init_hw = &ixgbe_init_hw_generic,
1286 .reset_hw = &ixgbe_reset_hw_82598,
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +00001287 .start_hw = &ixgbe_start_hw_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001288 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
Auke Kok9a799d72007-09-15 14:07:45 -07001289 .get_media_type = &ixgbe_get_media_type_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001290 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001291 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001292 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1293 .stop_adapter = &ixgbe_stop_adapter_generic,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001294 .get_bus_info = &ixgbe_get_bus_info_generic,
Emil Tantilovc9130182011-03-16 01:55:55 +00001295 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001296 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1297 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
Auke Kok3957d632007-10-31 15:22:10 -07001298 .setup_link = &ixgbe_setup_mac_link_82598,
John Fastabend80605c652011-05-02 12:34:10 +00001299 .set_rxpba = &ixgbe_set_rxpba_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001300 .check_link = &ixgbe_check_mac_link_82598,
1301 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1302 .led_on = &ixgbe_led_on_generic,
1303 .led_off = &ixgbe_led_off_generic,
PJ Waskiewicz87c12012009-04-08 13:20:31 +00001304 .blink_led_start = &ixgbe_blink_led_start_generic,
1305 .blink_led_stop = &ixgbe_blink_led_stop_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001306 .set_rar = &ixgbe_set_rar_generic,
1307 .clear_rar = &ixgbe_clear_rar_generic,
1308 .set_vmdq = &ixgbe_set_vmdq_82598,
1309 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1310 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001311 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1312 .enable_mc = &ixgbe_enable_mc_generic,
1313 .disable_mc = &ixgbe_disable_mc_generic,
1314 .clear_vfta = &ixgbe_clear_vfta_82598,
1315 .set_vfta = &ixgbe_set_vfta_82598,
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +00001316 .fc_enable = &ixgbe_fc_enable_82598,
Emil Tantilov9612de92011-05-07 07:40:20 +00001317 .set_fw_drv_ver = NULL,
Don Skidmore5e655102011-02-25 01:58:04 +00001318 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1319 .release_swfw_sync = &ixgbe_release_swfw_sync,
Don Skidmore3ca8bc62012-04-12 00:33:31 +00001320 .get_thermal_sensor_data = NULL,
1321 .init_thermal_sensor_thresh = NULL,
Don Skidmore0b2679d2013-02-21 03:00:04 +00001322 .mng_fw_enabled = NULL,
Don Skidmore429d6a32014-02-27 20:32:41 -08001323 .prot_autoc_read = &prot_autoc_read_generic,
1324 .prot_autoc_write = &prot_autoc_write_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001325};
1326
1327static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1328 .init_params = &ixgbe_init_eeprom_params_generic,
Mallikarjuna R Chilakala21ce8492010-05-13 17:33:41 +00001329 .read = &ixgbe_read_eerd_generic,
Emil Tantilov2fa5eef2011-10-06 08:57:04 +00001330 .write = &ixgbe_write_eeprom_generic,
1331 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
Emil Tantilov68c70052011-04-20 08:49:06 +00001332 .read_buffer = &ixgbe_read_eerd_buffer_generic,
Don Skidmorea391f1d2010-11-16 19:27:15 -08001333 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001334 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1335 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1336};
1337
1338static struct ixgbe_phy_operations phy_ops_82598 = {
1339 .identify = &ixgbe_identify_phy_generic,
Don Skidmore8f583322013-07-27 06:25:38 +00001340 .identify_sfp = &ixgbe_identify_module_generic,
PJ Waskiewicz04f165e2009-04-09 22:27:57 +00001341 .init = &ixgbe_init_phy_ops_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001342 .reset = &ixgbe_reset_phy_generic,
1343 .read_reg = &ixgbe_read_phy_reg_generic,
1344 .write_reg = &ixgbe_write_phy_reg_generic,
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001345 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
1346 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001347 .setup_link = &ixgbe_setup_phy_link_generic,
1348 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
Emil Tantilov07ce8702012-12-19 07:14:17 +00001349 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
Donald Skidmorec4900be2008-11-20 21:11:42 -08001350 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -07001351 .check_overtemp = &ixgbe_tn_check_overtemp,
Auke Kok9a799d72007-09-15 14:07:45 -07001352};
1353
Auke Kok3957d632007-10-31 15:22:10 -07001354struct ixgbe_info ixgbe_82598_info = {
Auke Kok9a799d72007-09-15 14:07:45 -07001355 .mac = ixgbe_mac_82598EB,
1356 .get_invariants = &ixgbe_get_invariants_82598,
1357 .mac_ops = &mac_ops_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001358 .eeprom_ops = &eeprom_ops_82598,
1359 .phy_ops = &phy_ops_82598,
Auke Kok9a799d72007-09-15 14:07:45 -07001360};