blob: 3285c8e2c87aaf439a414702ef16487f183e4e2f [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
Tvrtko Ursulin93b81f52015-02-10 17:16:05 +000034#include <uapi/drm/drm_fourcc.h>
Chris Wilsone9b73c62012-12-03 21:03:14 +000035
Keith Packard0839ccb2008-10-30 19:38:48 -070036#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070037#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010038#include <linux/i2c-algo-bit.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020039#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010040#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070041#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020042#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010043#include <linux/pm_qos.h>
Chris Wilsone73bdd22016-04-13 17:35:01 +010044#include <linux/shmem_fs.h>
45
46#include <drm/drmP.h>
47#include <drm/intel-gtt.h>
48#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49#include <drm/drm_gem.h>
Daniel Vetter3b96a0b2016-06-21 10:54:22 +020050#include <drm/drm_auth.h>
Chris Wilsone73bdd22016-04-13 17:35:01 +010051
52#include "i915_params.h"
53#include "i915_reg.h"
54
55#include "intel_bios.h"
Ander Conselvan de Oliveiraac7f11c2016-03-08 17:46:19 +020056#include "intel_dpll_mgr.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010057#include "intel_guc.h"
58#include "intel_lrc.h"
59#include "intel_ringbuffer.h"
60
Chris Wilsond501b1d2016-04-13 17:35:02 +010061#include "i915_gem.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010062#include "i915_gem_gtt.h"
63#include "i915_gem_render_state.h"
Chris Wilson05235c52016-07-20 09:21:08 +010064#include "i915_gem_request.h"
Jesse Barnes585fb112008-07-29 11:54:06 -070065
Zhi Wang0ad35fe2016-06-16 08:07:00 -040066#include "intel_gvt.h"
67
Linus Torvalds1da177e2005-04-16 15:20:36 -070068/* General customization:
69 */
70
Linus Torvalds1da177e2005-04-16 15:20:36 -070071#define DRIVER_NAME "i915"
72#define DRIVER_DESC "Intel Graphics"
Daniel Vetterc5b7e972016-08-08 09:37:31 +020073#define DRIVER_DATE "20160808"
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
Mika Kuoppalac883ef12014-10-28 17:32:30 +020075#undef WARN_ON
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010076/* Many gcc seem to no see through this and fall over :( */
77#if 0
78#define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83#else
Joonas Lahtinen152b2262015-12-18 14:27:27 +020084#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010085#endif
86
Jani Nikulacd9bfac2015-03-12 13:01:12 +020087#undef WARN_ON_ONCE
Joonas Lahtinen152b2262015-12-18 14:27:27 +020088#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
Jani Nikulacd9bfac2015-03-12 13:01:12 +020089
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010090#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
Mika Kuoppalac883ef12014-10-28 17:32:30 +020092
Rob Clarke2c719b2014-12-15 13:56:32 -050093/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
98 * spam.
99 */
100#define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
Joonas Lahtinen32753cb2015-12-18 14:27:26 +0200102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
Rob Clarke2c719b2014-12-15 13:56:32 -0500104 DRM_ERROR(format); \
Rob Clarke2c719b2014-12-15 13:56:32 -0500105 unlikely(__ret_warn_on); \
106})
107
Joonas Lahtinen152b2262015-12-18 14:27:27 +0200108#define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
Jesse Barnes317c35d2008-08-25 15:11:06 -0700110
Imre Deak4fec15d2016-03-16 13:39:08 +0200111bool __i915_inject_load_failure(const char *func, int line);
112#define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
114
Jani Nikula42a8ca42015-08-27 16:23:30 +0300115static inline const char *yesno(bool v)
116{
117 return v ? "yes" : "no";
118}
119
Jani Nikula87ad3212016-01-14 12:53:34 +0200120static inline const char *onoff(bool v)
121{
122 return v ? "on" : "off";
123}
124
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125enum pipe {
Jesse Barnes317c35d2008-08-25 15:11:06 -0700126 INVALID_PIPE = -1,
127 PIPE_A = 0,
128 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800129 PIPE_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200130 _PIPE_EDP,
131 I915_MAX_PIPES = _PIPE_EDP
Jesse Barnes317c35d2008-08-25 15:11:06 -0700132};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800133#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -0700134
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200135enum transcoder {
136 TRANSCODER_A = 0,
137 TRANSCODER_B,
138 TRANSCODER_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200139 TRANSCODER_EDP,
Jani Nikula4d1de972016-03-18 17:05:42 +0200140 TRANSCODER_DSI_A,
141 TRANSCODER_DSI_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200142 I915_MAX_TRANSCODERS
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200143};
Jani Nikulada205632016-03-15 21:51:10 +0200144
145static inline const char *transcoder_name(enum transcoder transcoder)
146{
147 switch (transcoder) {
148 case TRANSCODER_A:
149 return "A";
150 case TRANSCODER_B:
151 return "B";
152 case TRANSCODER_C:
153 return "C";
154 case TRANSCODER_EDP:
155 return "EDP";
Jani Nikula4d1de972016-03-18 17:05:42 +0200156 case TRANSCODER_DSI_A:
157 return "DSI A";
158 case TRANSCODER_DSI_C:
159 return "DSI C";
Jani Nikulada205632016-03-15 21:51:10 +0200160 default:
161 return "<invalid>";
162 }
163}
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200164
Jani Nikula4d1de972016-03-18 17:05:42 +0200165static inline bool transcoder_is_dsi(enum transcoder transcoder)
166{
167 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
168}
169
Damien Lespiau84139d12014-03-28 00:18:32 +0530170/*
Matt Roper31409e92015-09-24 15:53:09 -0700171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
Damien Lespiau84139d12014-03-28 00:18:32 +0530175 */
Jesse Barnes80824002009-09-10 15:28:06 -0700176enum plane {
177 PLANE_A = 0,
178 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800179 PLANE_C,
Matt Roper31409e92015-09-24 15:53:09 -0700180 PLANE_CURSOR,
181 I915_MAX_PLANES,
Jesse Barnes80824002009-09-10 15:28:06 -0700182};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800183#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -0800184
Damien Lespiaud615a162014-03-03 17:31:48 +0000185#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +0300186
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300187enum port {
188 PORT_A = 0,
189 PORT_B,
190 PORT_C,
191 PORT_D,
192 PORT_E,
193 I915_MAX_PORTS
194};
195#define port_name(p) ((p) + 'A')
196
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300197#define I915_NUM_PHYS_VLV 2
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800198
199enum dpio_channel {
200 DPIO_CH0,
201 DPIO_CH1
202};
203
204enum dpio_phy {
205 DPIO_PHY0,
206 DPIO_PHY1
207};
208
Paulo Zanonib97186f2013-05-03 12:15:36 -0300209enum intel_display_power_domain {
210 POWER_DOMAIN_PIPE_A,
211 POWER_DOMAIN_PIPE_B,
212 POWER_DOMAIN_PIPE_C,
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
216 POWER_DOMAIN_TRANSCODER_A,
217 POWER_DOMAIN_TRANSCODER_B,
218 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300219 POWER_DOMAIN_TRANSCODER_EDP,
Jani Nikula4d1de972016-03-18 17:05:42 +0200220 POWER_DOMAIN_TRANSCODER_DSI_A,
221 POWER_DOMAIN_TRANSCODER_DSI_C,
Patrik Jakobsson6331a702015-11-09 16:48:21 +0100222 POWER_DOMAIN_PORT_DDI_A_LANES,
223 POWER_DOMAIN_PORT_DDI_B_LANES,
224 POWER_DOMAIN_PORT_DDI_C_LANES,
225 POWER_DOMAIN_PORT_DDI_D_LANES,
226 POWER_DOMAIN_PORT_DDI_E_LANES,
Imre Deak319be8a2014-03-04 19:22:57 +0200227 POWER_DOMAIN_PORT_DSI,
228 POWER_DOMAIN_PORT_CRT,
229 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300230 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200231 POWER_DOMAIN_AUDIO,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300232 POWER_DOMAIN_PLLS,
Satheeshakrishna M14071212015-01-16 15:57:51 +0000233 POWER_DOMAIN_AUX_A,
234 POWER_DOMAIN_AUX_B,
235 POWER_DOMAIN_AUX_C,
236 POWER_DOMAIN_AUX_D,
Ville Syrjäläf0ab43e2015-11-09 16:48:19 +0100237 POWER_DOMAIN_GMBUS,
Patrik Jakobssondfa57622015-11-09 16:48:22 +0100238 POWER_DOMAIN_MODESET,
Imre Deakbaa70702013-10-25 17:36:48 +0300239 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300240
241 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300242};
243
244#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300247#define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300250
Egbert Eich1d843f92013-02-25 12:06:49 -0500251enum hpd_pin {
252 HPD_NONE = 0,
Egbert Eich1d843f92013-02-25 12:06:49 -0500253 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
254 HPD_CRT,
255 HPD_SDVO_B,
256 HPD_SDVO_C,
Imre Deakcc24fcd2015-07-21 15:32:45 -0700257 HPD_PORT_A,
Egbert Eich1d843f92013-02-25 12:06:49 -0500258 HPD_PORT_B,
259 HPD_PORT_C,
260 HPD_PORT_D,
Xiong Zhang26951ca2015-08-17 15:55:50 +0800261 HPD_PORT_E,
Egbert Eich1d843f92013-02-25 12:06:49 -0500262 HPD_NUM_PINS
263};
264
Jani Nikulac91711f2015-05-28 15:43:48 +0300265#define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267
Jani Nikula5fcece82015-05-27 15:03:42 +0300268struct i915_hotplug {
269 struct work_struct hotplug_work;
270
271 struct {
272 unsigned long last_jiffies;
273 int count;
274 enum {
275 HPD_ENABLED = 0,
276 HPD_DISABLED = 1,
277 HPD_MARK_DISABLED = 2
278 } state;
279 } stats[HPD_NUM_PINS];
280 u32 event_bits;
281 struct delayed_work reenable_work;
282
283 struct intel_digital_port *irq_port[I915_MAX_PORTS];
284 u32 long_port_mask;
285 u32 short_port_mask;
286 struct work_struct dig_port_work;
287
Lyude19625e82016-06-21 17:03:44 -0400288 struct work_struct poll_init_work;
289 bool poll_enabled;
290
Jani Nikula5fcece82015-05-27 15:03:42 +0300291 /*
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
297 */
298 struct workqueue_struct *dp_wq;
299};
300
Chris Wilson2a2d5482012-12-03 11:49:06 +0000301#define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700307
Damien Lespiau055e3932014-08-18 13:49:10 +0100308#define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Ville Syrjälä6831f3e2016-02-19 20:47:31 +0200310#define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
Damien Lespiaudd740782015-02-28 14:54:08 +0000313#define for_each_plane(__dev_priv, __pipe, __p) \
314 for ((__p) = 0; \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
316 (__p)++)
Damien Lespiau3bdcfc02015-02-28 14:54:09 +0000317#define for_each_sprite(__dev_priv, __p, __s) \
318 for ((__s) = 0; \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
320 (__s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800321
Jani Nikulac3aeadc82016-03-15 21:51:09 +0200322#define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
325
Damien Lespiaud79b8142014-05-13 23:32:23 +0100326#define for_each_crtc(dev, crtc) \
Chris Wilson91c8a322016-07-05 10:40:23 +0100327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
Damien Lespiaud79b8142014-05-13 23:32:23 +0100328
Maarten Lankhorst27321ae2015-04-21 17:12:52 +0300329#define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
Chris Wilson91c8a322016-07-05 10:40:23 +0100331 &(dev)->mode_config.plane_list, \
Maarten Lankhorst27321ae2015-04-21 17:12:52 +0300332 base.head)
333
Matt Roperc107acf2016-05-12 07:06:01 -0700334#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
Chris Wilson91c8a322016-07-05 10:40:23 +0100335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
Matt Roperc107acf2016-05-12 07:06:01 -0700337 base.head) \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
340
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300341#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
344 base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300346
Chris Wilson91c8a322016-07-05 10:40:23 +0100347#define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
350 base.head)
Damien Lespiaud063ae42014-05-13 23:32:21 +0100351
Chris Wilson91c8a322016-07-05 10:40:23 +0100352#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
355 base.head) \
Matt Roper98d39492016-05-12 07:06:03 -0700356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
357
Damien Lespiaub2784e12014-08-05 11:29:37 +0100358#define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
361 base.head)
362
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +0200363#define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
Chris Wilson91c8a322016-07-05 10:40:23 +0100365 &(dev)->mode_config.connector_list, \
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +0200366 base.head)
367
Daniel Vetter6c2b7c12012-07-05 09:50:24 +0200368#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
Daniel Vetter6c2b7c12012-07-05 09:50:24 +0200371
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800372#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200374 for_each_if ((intel_connector)->base.encoder == (__encoder))
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800375
Borun Fub04c5bd2014-07-12 10:02:27 +0530376#define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200378 for_each_if ((1 << (domain)) & (mask))
Borun Fub04c5bd2014-07-12 10:02:27 +0530379
Daniel Vettere7b903d2013-06-05 13:34:14 +0200380struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100381struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100382struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200383
Chris Wilsona6f766f2015-04-27 13:41:20 +0100384struct drm_i915_file_private {
385 struct drm_i915_private *dev_priv;
386 struct drm_file *file;
387
388 struct {
389 spinlock_t lock;
390 struct list_head request_list;
Chris Wilsond0bc54f2015-05-21 21:01:48 +0100391/* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
395 */
396#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
Chris Wilsona6f766f2015-04-27 13:41:20 +0100397 } mm;
398 struct idr context_idr;
399
Chris Wilson2e1b8732015-04-27 13:41:22 +0100400 struct intel_rps_client {
401 struct list_head link;
402 unsigned boosts;
403 } rps;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100404
Chris Wilsonc80ff162016-07-27 09:07:27 +0100405 unsigned int bsd_engine;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100406};
407
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100408/* Used by dp and fdi links */
409struct intel_link_m_n {
410 uint32_t tu;
411 uint32_t gmch_m;
412 uint32_t gmch_n;
413 uint32_t link_m;
414 uint32_t link_n;
415};
416
417void intel_link_compute_m_n(int bpp, int nlanes,
418 int pixel_clock, int link_clock,
419 struct intel_link_m_n *m_n);
420
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421/* Interface history:
422 *
423 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100426 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000427 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 */
431#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000432#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433#define DRIVER_PATCHLEVEL 0
434
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700435struct opregion_header;
436struct opregion_acpi;
437struct opregion_swsci;
438struct opregion_asle;
439
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100440struct intel_opregion {
Williams, Dan J115719f2015-10-12 21:12:57 +0000441 struct opregion_header *header;
442 struct opregion_acpi *acpi;
443 struct opregion_swsci *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300444 u32 swsci_gbda_sub_functions;
445 u32 swsci_sbcb_sub_functions;
Williams, Dan J115719f2015-10-12 21:12:57 +0000446 struct opregion_asle *asle;
Jani Nikula04ebaad2015-12-15 13:18:00 +0200447 void *rvda;
Jani Nikula82730382015-12-14 12:50:52 +0200448 const void *vbt;
Jani Nikulaada8f952015-12-15 13:17:12 +0200449 u32 vbt_size;
Williams, Dan J115719f2015-10-12 21:12:57 +0000450 u32 *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200451 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100452};
Chris Wilson44834a62010-08-19 16:09:23 +0100453#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100454
Chris Wilson6ef3d422010-08-04 20:26:07 +0100455struct intel_overlay;
456struct intel_overlay_error_state;
457
Jesse Barnesde151cf2008-11-12 10:03:55 -0800458#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300459#define I915_MAX_NUM_FENCES 32
460/* 32 fences + sign bit for FENCE_REG_NONE */
461#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800462
463struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200464 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000465 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100466 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800467};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000468
yakui_zhao9b9d1722009-05-31 17:17:17 +0800469struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100470 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800471 u8 dvo_port;
472 u8 slave_addr;
473 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100474 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400475 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800476};
477
Jani Nikula7bd688c2013-11-08 16:48:56 +0200478struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200479struct intel_encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200480struct intel_crtc_state;
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000481struct intel_initial_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100482struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200483struct intel_limit;
484struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100485
Jesse Barnese70236a2009-09-21 10:42:27 -0700486struct drm_i915_display_funcs {
Jesse Barnese70236a2009-09-21 10:42:27 -0700487 int (*get_display_clock_speed)(struct drm_device *dev);
488 int (*get_fifo_size)(struct drm_device *dev, int plane);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +0100489 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
Matt Ropered4a6a72016-02-23 17:20:13 -0800490 int (*compute_intermediate_wm)(struct drm_device *dev,
491 struct intel_crtc *intel_crtc,
492 struct intel_crtc_state *newstate);
493 void (*initial_watermarks)(struct intel_crtc_state *cstate);
494 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
Matt Roper98d39492016-05-12 07:06:03 -0700495 int (*compute_global_watermarks)(struct drm_atomic_state *state);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300496 void (*update_wm)(struct drm_crtc *crtc);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +0200497 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
498 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100499 /* Returns the active state of the crtc, and if the crtc is active,
500 * fills out the pipe-config with the hw state. */
501 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200502 struct intel_crtc_state *);
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000503 void (*get_initial_plane_config)(struct intel_crtc *,
504 struct intel_initial_plane_config *);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200505 int (*crtc_compute_clock)(struct intel_crtc *crtc,
506 struct intel_crtc_state *crtc_state);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200507 void (*crtc_enable)(struct drm_crtc *crtc);
508 void (*crtc_disable)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200509 void (*audio_codec_enable)(struct drm_connector *connector,
510 struct intel_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300511 const struct drm_display_mode *adjusted_mode);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200512 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700513 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700514 void (*init_clock_gating)(struct drm_device *dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +0200515 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
516 struct drm_framebuffer *fb,
517 struct drm_i915_gem_object *obj,
518 struct drm_i915_gem_request *req,
519 uint32_t flags);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100520 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
Jesse Barnese70236a2009-09-21 10:42:27 -0700521 /* clock updates for mode set */
522 /* cursor updates */
523 /* render clock increase/decrease */
524 /* display clock increase/decrease */
525 /* pll clock increase/decrease */
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +0000526
Maarten Lankhorstb95c5322016-03-30 17:16:34 +0200527 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
528 void (*load_luts)(struct drm_crtc_state *crtc_state);
Jesse Barnese70236a2009-09-21 10:42:27 -0700529};
530
Mika Kuoppala48c10262015-01-16 11:34:41 +0200531enum forcewake_domain_id {
532 FW_DOMAIN_ID_RENDER = 0,
533 FW_DOMAIN_ID_BLITTER,
534 FW_DOMAIN_ID_MEDIA,
535
536 FW_DOMAIN_ID_COUNT
537};
538
539enum forcewake_domains {
540 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
541 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
542 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
543 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
544 FORCEWAKE_BLITTER |
545 FORCEWAKE_MEDIA)
546};
547
Tvrtko Ursulin37566852016-04-12 14:37:31 +0100548#define FW_REG_READ (1)
549#define FW_REG_WRITE (2)
550
551enum forcewake_domains
552intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
553 i915_reg_t reg, unsigned int op);
554
Chris Wilson907b28c2013-07-19 20:36:52 +0100555struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530556 void (*force_wake_get)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200557 enum forcewake_domains domains);
Deepak Sc8d9a592013-11-23 14:55:42 +0530558 void (*force_wake_put)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200559 enum forcewake_domains domains);
Ben Widawsky0b274482013-10-04 21:22:51 -0700560
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200561 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
562 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
563 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
564 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
Ben Widawsky0b274482013-10-04 21:22:51 -0700565
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200566 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700567 uint8_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200568 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700569 uint16_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200570 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700571 uint32_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200572 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700573 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300574};
575
Chris Wilson907b28c2013-07-19 20:36:52 +0100576struct intel_uncore {
577 spinlock_t lock; /** lock is also taken in irq contexts. */
578
579 struct intel_uncore_funcs funcs;
580
581 unsigned fifo_count;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200582 enum forcewake_domains fw_domains;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100583
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200584 struct intel_uncore_forcewake_domain {
585 struct drm_i915_private *i915;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200586 enum forcewake_domain_id id;
Tvrtko Ursulin33c582c2016-04-07 17:04:33 +0100587 enum forcewake_domains mask;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200588 unsigned wake_count;
Tvrtko Ursulina57a4a62016-04-07 17:04:32 +0100589 struct hrtimer timer;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200590 i915_reg_t reg_set;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200591 u32 val_set;
592 u32 val_clear;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200593 i915_reg_t reg_ack;
594 i915_reg_t reg_post;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200595 u32 val_reset;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200596 } fw_domain[FW_DOMAIN_ID_COUNT];
Mika Kuoppala75714942015-12-16 09:26:48 +0200597
598 int unclaimed_mmio_check;
Chris Wilson907b28c2013-07-19 20:36:52 +0100599};
600
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200601/* Iterate over initialised fw domains */
Tvrtko Ursulin33c582c2016-04-07 17:04:33 +0100602#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
603 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
604 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
605 (domain__)++) \
606 for_each_if ((mask__) & (domain__)->mask)
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200607
Tvrtko Ursulin33c582c2016-04-07 17:04:33 +0100608#define for_each_fw_domain(domain__, dev_priv__) \
609 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200610
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200611#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
612#define CSR_VERSION_MAJOR(version) ((version) >> 16)
613#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
614
Daniel Vettereb805622015-05-04 14:58:44 +0200615struct intel_csr {
Daniel Vetter8144ac52015-10-28 23:59:04 +0200616 struct work_struct work;
Daniel Vettereb805622015-05-04 14:58:44 +0200617 const char *fw_path;
Animesh Mannaa7f749f2015-08-03 21:55:32 +0530618 uint32_t *dmc_payload;
Daniel Vettereb805622015-05-04 14:58:44 +0200619 uint32_t dmc_fw_size;
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200620 uint32_t version;
Daniel Vettereb805622015-05-04 14:58:44 +0200621 uint32_t mmio_count;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200622 i915_reg_t mmioaddr[8];
Daniel Vettereb805622015-05-04 14:58:44 +0200623 uint32_t mmiodata[8];
Patrik Jakobsson832dba82016-02-18 17:21:11 +0200624 uint32_t dc_state;
Imre Deaka37baf32016-02-29 22:49:03 +0200625 uint32_t allowed_dc_mask;
Daniel Vettereb805622015-05-04 14:58:44 +0200626};
627
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100628#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
629 func(is_mobile) sep \
630 func(is_i85x) sep \
631 func(is_i915g) sep \
632 func(is_i945gm) sep \
633 func(is_g33) sep \
634 func(need_gfx_hws) sep \
635 func(is_g4x) sep \
636 func(is_pineview) sep \
637 func(is_broadwater) sep \
638 func(is_crestline) sep \
639 func(is_ivybridge) sep \
640 func(is_valleyview) sep \
Wayne Boyer666a4532015-12-09 12:29:35 -0800641 func(is_cherryview) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100642 func(is_haswell) sep \
Tvrtko Ursulinab0d24a2016-05-10 10:57:05 +0100643 func(is_broadwell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530644 func(is_skylake) sep \
Rodrigo Vivi7526ac12015-10-27 10:14:54 -0700645 func(is_broxton) sep \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700646 func(is_kabylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700647 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100648 func(has_fbc) sep \
649 func(has_pipe_cxsr) sep \
650 func(has_hotplug) sep \
651 func(cursor_needs_physical) sep \
652 func(has_overlay) sep \
653 func(overlay_needs_physical) sep \
654 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100655 func(has_llc) sep \
Tvrtko Ursulinca377802016-03-02 12:10:31 +0000656 func(has_snoop) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100657 func(has_ddi) sep \
arun.siluvery@linux.intel.com33e141e2016-06-03 06:34:33 +0100658 func(has_fpga_dbg) sep \
659 func(has_pooled_eu)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200660
Damien Lespiaua587f772013-04-22 18:40:38 +0100661#define DEFINE_FLAG(name) u8 name:1
662#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200663
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500664struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200665 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100666 u16 device_id;
Tvrtko Ursulinac208a82016-05-10 10:57:07 +0100667 u8 num_pipes;
Damien Lespiaud615a162014-03-03 17:31:48 +0000668 u8 num_sprites[I915_MAX_PIPES];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700669 u8 gen;
Tvrtko Ursulinae5702d2016-05-10 10:57:04 +0100670 u16 gen_mask;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700671 u8 ring_mask; /* Rings supported by the HW */
Tvrtko Ursulinc1bb1142016-08-10 16:22:10 +0100672 u8 num_rings;
Damien Lespiaua587f772013-04-22 18:40:38 +0100673 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200674 /* Register offsets for the various display pipes and transcoders */
675 int pipe_offsets[I915_MAX_TRANSCODERS];
676 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200677 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300678 int cursor_offsets[I915_MAX_PIPES];
Jeff McGee38732182015-02-13 10:27:54 -0600679
680 /* Slice/subslice/EU info */
681 u8 slice_total;
682 u8 subslice_total;
683 u8 subslice_per_slice;
684 u8 eu_total;
685 u8 eu_per_subslice;
arun.siluvery@linux.intel.com33e141e2016-06-03 06:34:33 +0100686 u8 min_eu_in_pool;
Damien Lespiaub7668792015-02-14 18:30:29 +0000687 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
688 u8 subslice_7eu[3];
Jeff McGee38732182015-02-13 10:27:54 -0600689 u8 has_slice_pg:1;
690 u8 has_subslice_pg:1;
691 u8 has_eu_pg:1;
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000692
693 struct color_luts {
694 u16 degamma_lut_size;
695 u16 gamma_lut_size;
696 } color;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500697};
698
Damien Lespiaua587f772013-04-22 18:40:38 +0100699#undef DEFINE_FLAG
700#undef SEP_SEMICOLON
701
Chris Wilson2bd160a2016-08-15 10:48:45 +0100702struct intel_display_error_state;
703
704struct drm_i915_error_state {
705 struct kref ref;
706 struct timeval time;
707
708 char error_msg[128];
709 bool simulated;
710 int iommu;
711 u32 reset_count;
712 u32 suspend_count;
713 struct intel_device_info device_info;
714
715 /* Generic register state */
716 u32 eir;
717 u32 pgtbl_er;
718 u32 ier;
719 u32 gtier[4];
720 u32 ccid;
721 u32 derrmr;
722 u32 forcewake;
723 u32 error; /* gen6+ */
724 u32 err_int; /* gen7 */
725 u32 fault_data0; /* gen8, gen9 */
726 u32 fault_data1; /* gen8, gen9 */
727 u32 done_reg;
728 u32 gac_eco;
729 u32 gam_ecochk;
730 u32 gab_ctl;
731 u32 gfx_mode;
732 u32 extra_instdone[I915_NUM_INSTDONE_REG];
733 u64 fence[I915_MAX_NUM_FENCES];
734 struct intel_overlay_error_state *overlay;
735 struct intel_display_error_state *display;
736 struct drm_i915_error_object *semaphore_obj;
737
738 struct drm_i915_error_engine {
739 int engine_id;
740 /* Software tracked state */
741 bool waiting;
742 int num_waiters;
743 int hangcheck_score;
744 enum intel_engine_hangcheck_action hangcheck_action;
745 struct i915_address_space *vm;
746 int num_requests;
747
748 /* our own tracking of ring head and tail */
749 u32 cpu_ring_head;
750 u32 cpu_ring_tail;
751
752 u32 last_seqno;
753 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
754
755 /* Register state */
756 u32 start;
757 u32 tail;
758 u32 head;
759 u32 ctl;
760 u32 hws;
761 u32 ipeir;
762 u32 ipehr;
763 u32 instdone;
764 u32 bbstate;
765 u32 instpm;
766 u32 instps;
767 u32 seqno;
768 u64 bbaddr;
769 u64 acthd;
770 u32 fault_reg;
771 u64 faddr;
772 u32 rc_psmi; /* sleep state */
773 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
774
775 struct drm_i915_error_object {
776 int page_count;
777 u64 gtt_offset;
778 u32 *pages[0];
779 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
780
781 struct drm_i915_error_object *wa_ctx;
782
783 struct drm_i915_error_request {
784 long jiffies;
785 u32 seqno;
786 u32 head;
787 u32 tail;
788 } *requests;
789
790 struct drm_i915_error_waiter {
791 char comm[TASK_COMM_LEN];
792 pid_t pid;
793 u32 seqno;
794 } *waiters;
795
796 struct {
797 u32 gfx_mode;
798 union {
799 u64 pdp[4];
800 u32 pp_dir_base;
801 };
802 } vm_info;
803
804 pid_t pid;
805 char comm[TASK_COMM_LEN];
806 } engine[I915_NUM_ENGINES];
807
808 struct drm_i915_error_buffer {
809 u32 size;
810 u32 name;
811 u32 rseqno[I915_NUM_ENGINES], wseqno;
812 u64 gtt_offset;
813 u32 read_domains;
814 u32 write_domain;
815 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
816 u32 tiling:2;
817 u32 dirty:1;
818 u32 purgeable:1;
819 u32 userptr:1;
820 s32 engine:4;
821 u32 cache_level:3;
822 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
823 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
824 struct i915_address_space *active_vm[I915_NUM_ENGINES];
825};
826
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800827enum i915_cache_level {
828 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100829 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
830 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
831 caches, eg sampler/render caches, and the
832 large Last-Level-Cache. LLC is coherent with
833 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100834 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800835};
836
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300837struct i915_ctx_hang_stats {
838 /* This context had batch pending when hang was declared */
839 unsigned batch_pending;
840
841 /* This context had batch active when hang was declared */
842 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300843
844 /* Time when this context was last blamed for a GPU reset */
845 unsigned long guilty_ts;
846
Chris Wilson676fa572014-12-24 08:13:39 -0800847 /* If the contexts causes a second GPU hang within this time,
848 * it is permanently banned from submitting any more work.
849 */
850 unsigned long ban_period_seconds;
851
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300852 /* This context is banned to submit more work */
853 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300854};
Ben Widawsky40521052012-06-04 14:42:43 -0700855
856/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100857#define DEFAULT_CONTEXT_HANDLE 0
David Weinehallb1b38272015-05-20 17:00:13 +0300858
Oscar Mateo31b7a882014-07-03 16:28:01 +0100859/**
Chris Wilsone2efd132016-05-24 14:53:34 +0100860 * struct i915_gem_context - as the name implies, represents a context.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100861 * @ref: reference count.
862 * @user_handle: userspace tracking identity for this context.
863 * @remap_slice: l3 row remapping information.
David Weinehallb1b38272015-05-20 17:00:13 +0300864 * @flags: context specific flags:
865 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100866 * @file_priv: filp associated with this context (NULL for global default
867 * context).
868 * @hang_stats: information about the role of this context in possible GPU
869 * hangs.
Tvrtko Ursulin7df113e2015-04-17 12:49:07 +0100870 * @ppgtt: virtual memory space used by this context.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100871 * @legacy_hw_ctx: render context backing object and whether it is correctly
872 * initialized (legacy ring submission mechanism only).
873 * @link: link in the global list of contexts.
874 *
875 * Contexts are memory images used by the hardware to store copies of their
876 * internal state.
877 */
Chris Wilsone2efd132016-05-24 14:53:34 +0100878struct i915_gem_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300879 struct kref ref;
Chris Wilson9ea4fee2015-05-05 09:17:29 +0100880 struct drm_i915_private *i915;
Ben Widawsky40521052012-06-04 14:42:43 -0700881 struct drm_i915_file_private *file_priv;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200882 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700883
Chris Wilson8d59bc62016-05-24 14:53:42 +0100884 struct i915_ctx_hang_stats hang_stats;
885
Chris Wilson5d1808e2016-04-28 09:56:51 +0100886 /* Unique identifier for this context, used by the hw for tracking */
Chris Wilson8d59bc62016-05-24 14:53:42 +0100887 unsigned long flags;
Chris Wilsonbc3d6742016-07-04 08:08:39 +0100888#define CONTEXT_NO_ZEROMAP BIT(0)
889#define CONTEXT_NO_ERROR_CAPTURE BIT(1)
Chris Wilson5d1808e2016-04-28 09:56:51 +0100890 unsigned hw_id;
Chris Wilson8d59bc62016-05-24 14:53:42 +0100891 u32 user_handle;
Chris Wilson5d1808e2016-04-28 09:56:51 +0100892
Chris Wilson0cb26a82016-06-24 14:55:53 +0100893 u32 ggtt_alignment;
894
Chris Wilson9021ad02016-05-24 14:53:37 +0100895 struct intel_context {
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100896 struct drm_i915_gem_object *state;
Chris Wilson7e37f882016-08-02 22:50:21 +0100897 struct intel_ring *ring;
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000898 struct i915_vma *lrc_vma;
Tvrtko Ursulin82352e92016-01-15 17:12:45 +0000899 uint32_t *lrc_reg_state;
Chris Wilson8d59bc62016-05-24 14:53:42 +0100900 u64 lrc_desc;
901 int pin_count;
Chris Wilson24f1d3c2016-04-28 09:56:53 +0100902 bool initialised;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000903 } engine[I915_NUM_ENGINES];
Zhi Wangbcd794c2016-06-16 08:07:01 -0400904 u32 ring_size;
Zhi Wangc01fc532016-06-16 08:07:02 -0400905 u32 desc_template;
Zhi Wang3c7ba632016-06-16 08:07:03 -0400906 struct atomic_notifier_head status_notifier;
Zhi Wang80a9a8d2016-06-16 08:07:04 -0400907 bool execlists_force_single_submission;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100908
Ben Widawskya33afea2013-09-17 21:12:45 -0700909 struct list_head link;
Chris Wilson8d59bc62016-05-24 14:53:42 +0100910
911 u8 remap_slice;
Chris Wilson50e046b2016-08-04 07:52:46 +0100912 bool closed:1;
Ben Widawsky40521052012-06-04 14:42:43 -0700913};
914
Paulo Zanonia4001f12015-02-13 17:23:44 -0200915enum fb_op_origin {
916 ORIGIN_GTT,
917 ORIGIN_CPU,
918 ORIGIN_CS,
919 ORIGIN_FLIP,
Paulo Zanoni74b4ea12015-07-14 16:29:14 -0300920 ORIGIN_DIRTYFB,
Paulo Zanonia4001f12015-02-13 17:23:44 -0200921};
922
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200923struct intel_fbc {
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300924 /* This is always the inner lock when overlapping with struct_mutex and
925 * it's the outer lock when overlapping with stolen_lock. */
926 struct mutex lock;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700927 unsigned threshold;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200928 unsigned int possible_framebuffer_bits;
929 unsigned int busy_bits;
Paulo Zanoni010cf732016-01-19 11:35:48 -0200930 unsigned int visible_pipes_mask;
Paulo Zanonie35fef22015-02-09 14:46:29 -0200931 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700932
Ben Widawskyc4213882014-06-19 12:06:10 -0700933 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700934 struct drm_mm_node *compressed_llb;
935
Rodrigo Vivida46f932014-08-01 02:04:45 -0700936 bool false_color;
937
Paulo Zanonid029bca2015-10-15 10:44:46 -0300938 bool enabled;
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300939 bool active;
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300940
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200941 struct intel_fbc_state_cache {
942 struct {
943 unsigned int mode_flags;
944 uint32_t hsw_bdw_pixel_rate;
945 } crtc;
946
947 struct {
948 unsigned int rotation;
949 int src_w;
950 int src_h;
951 bool visible;
952 } plane;
953
954 struct {
955 u64 ilk_ggtt_offset;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200956 uint32_t pixel_format;
957 unsigned int stride;
958 int fence_reg;
959 unsigned int tiling_mode;
960 } fb;
961 } state_cache;
962
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200963 struct intel_fbc_reg_params {
964 struct {
965 enum pipe pipe;
966 enum plane plane;
967 unsigned int fence_y_offset;
968 } crtc;
969
970 struct {
971 u64 ggtt_offset;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200972 uint32_t pixel_format;
973 unsigned int stride;
974 int fence_reg;
975 } fb;
976
977 int cfb_size;
978 } params;
979
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700980 struct intel_fbc_work {
Paulo Zanoni128d7352015-10-26 16:27:49 -0200981 bool scheduled;
Paulo Zanonica18d512016-01-21 18:03:05 -0200982 u32 scheduled_vblank;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200983 struct work_struct work;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200984 } work;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700985
Paulo Zanonibf6189c2015-10-27 14:50:03 -0200986 const char *no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800987};
988
Vandana Kannan96178ee2015-01-10 02:25:56 +0530989/**
990 * HIGH_RR is the highest eDP panel refresh rate read from EDID
991 * LOW_RR is the lowest eDP panel refresh rate found from EDID
992 * parsing for same resolution.
993 */
994enum drrs_refresh_rate_type {
995 DRRS_HIGH_RR,
996 DRRS_LOW_RR,
997 DRRS_MAX_RR, /* RR count */
998};
999
1000enum drrs_support_type {
1001 DRRS_NOT_SUPPORTED = 0,
1002 STATIC_DRRS_SUPPORT = 1,
1003 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301004};
1005
Daniel Vetter2807cf62014-07-11 10:30:11 -07001006struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +05301007struct i915_drrs {
1008 struct mutex mutex;
1009 struct delayed_work work;
1010 struct intel_dp *dp;
1011 unsigned busy_frontbuffer_bits;
1012 enum drrs_refresh_rate_type refresh_rate_type;
1013 enum drrs_support_type type;
1014};
1015
Rodrigo Vivia031d702013-10-03 16:15:06 -03001016struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -07001017 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -03001018 bool sink_support;
1019 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -07001020 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07001021 bool active;
1022 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -07001023 unsigned busy_frontbuffer_bits;
Sonika Jindal474d1ec2015-04-02 11:02:44 +05301024 bool psr2_support;
1025 bool aux_frame_sync;
Rodrigo Vivi60e5ffe2016-02-01 12:02:07 -08001026 bool link_standby;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001027};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001028
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001029enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -03001030 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001031 PCH_IBX, /* Ibexpeak PCH */
1032 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03001033 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05301034 PCH_SPT, /* Sunrisepoint PCH */
Rodrigo Vivi22dea0b2016-07-01 17:07:12 -07001035 PCH_KBP, /* Kabypoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -07001036 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001037};
1038
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001039enum intel_sbi_destination {
1040 SBI_ICLK,
1041 SBI_MPHY,
1042};
1043
Jesse Barnesb690e962010-07-19 13:53:12 -07001044#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -07001045#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +01001046#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +00001047#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001048#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +01001049#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -07001050
Dave Airlie8be48d92010-03-30 05:34:14 +00001051struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +01001052struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +00001053
Daniel Vetterc2b91522012-02-14 22:37:19 +01001054struct intel_gmbus {
1055 struct i2c_adapter adapter;
Ville Syrjälä3e4d44e2016-03-07 17:56:59 +02001056#define GMBUS_FORCE_BIT_RETRY (1U << 31)
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +00001057 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +01001058 u32 reg0;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001059 i915_reg_t gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +01001060 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +01001061 struct drm_i915_private *dev_priv;
1062};
1063
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001064struct i915_suspend_saved_registers {
Keith Packarde948e992008-05-07 12:27:53 +10001065 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001066 u32 saveFBC_CONTROL;
Keith Packard1f84e552008-02-16 19:19:29 -08001067 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -08001068 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001069 u32 saveSWF0[16];
1070 u32 saveSWF1[16];
Ville Syrjälä85fa7922015-09-18 20:03:43 +03001071 u32 saveSWF3[3];
Daniel Vetter4b9de732011-10-09 21:52:02 +02001072 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Adam Jacksoncda2bb72011-07-26 16:53:06 -04001073 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -08001074 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001075};
Daniel Vetterc85aa882012-11-02 19:55:03 +01001076
Imre Deakddeea5b2014-05-05 15:19:56 +03001077struct vlv_s0ix_state {
1078 /* GAM */
1079 u32 wr_watermark;
1080 u32 gfx_prio_ctrl;
1081 u32 arb_mode;
1082 u32 gfx_pend_tlb0;
1083 u32 gfx_pend_tlb1;
1084 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1085 u32 media_max_req_count;
1086 u32 gfx_max_req_count;
1087 u32 render_hwsp;
1088 u32 ecochk;
1089 u32 bsd_hwsp;
1090 u32 blt_hwsp;
1091 u32 tlb_rd_addr;
1092
1093 /* MBC */
1094 u32 g3dctl;
1095 u32 gsckgctl;
1096 u32 mbctl;
1097
1098 /* GCP */
1099 u32 ucgctl1;
1100 u32 ucgctl3;
1101 u32 rcgctl1;
1102 u32 rcgctl2;
1103 u32 rstctl;
1104 u32 misccpctl;
1105
1106 /* GPM */
1107 u32 gfxpause;
1108 u32 rpdeuhwtc;
1109 u32 rpdeuc;
1110 u32 ecobus;
1111 u32 pwrdwnupctl;
1112 u32 rp_down_timeout;
1113 u32 rp_deucsw;
1114 u32 rcubmabdtmr;
1115 u32 rcedata;
1116 u32 spare2gh;
1117
1118 /* Display 1 CZ domain */
1119 u32 gt_imr;
1120 u32 gt_ier;
1121 u32 pm_imr;
1122 u32 pm_ier;
1123 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1124
1125 /* GT SA CZ domain */
1126 u32 tilectl;
1127 u32 gt_fifoctl;
1128 u32 gtlc_wake_ctrl;
1129 u32 gtlc_survive;
1130 u32 pmwgicz;
1131
1132 /* Display 2 CZ domain */
1133 u32 gu_ctl0;
1134 u32 gu_ctl1;
Jesse Barnes9c252102015-04-01 14:22:57 -07001135 u32 pcbr;
Imre Deakddeea5b2014-05-05 15:19:56 +03001136 u32 clock_gate_dis2;
1137};
1138
Chris Wilsonbf225f22014-07-10 20:31:18 +01001139struct intel_rps_ei {
1140 u32 cz_clock;
1141 u32 render_c0;
1142 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001143};
1144
Daniel Vetterc85aa882012-11-02 19:55:03 +01001145struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001146 /*
1147 * work, interrupts_enabled and pm_iir are protected by
1148 * dev_priv->irq_lock
1149 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001150 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001151 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001152 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001153
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05301154 u32 pm_intr_keep;
1155
Ben Widawskyb39fb292014-03-19 18:31:11 -07001156 /* Frequencies are stored in potentially platform dependent multiples.
1157 * In other words, *_freq needs to be multiplied by X to be interesting.
1158 * Soft limits are those which are used for the dynamic reclocking done
1159 * by the driver (raise frequencies under heavy loads, and lower for
1160 * lighter loads). Hard limits are those imposed by the hardware.
1161 *
1162 * A distinction is made for overclocking, which is never enabled by
1163 * default, and is considered to be above the hard limit if it's
1164 * possible at all.
1165 */
1166 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1167 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1168 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1169 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1170 u8 min_freq; /* AKA RPn. Minimum frequency */
Chris Wilson29ecd78d2016-07-13 09:10:35 +01001171 u8 boost_freq; /* Frequency to request when wait boosting */
Chris Wilsonaed242f2015-03-18 09:48:21 +00001172 u8 idle_freq; /* Frequency to request when we are idle */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001173 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1174 u8 rp1_freq; /* "less than" RP0 power/freqency */
1175 u8 rp0_freq; /* Non-overclocked max frequency. */
Ville Syrjäläc30fec62016-03-04 21:43:02 +02001176 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001177
Chris Wilson8fb55192015-04-07 16:20:28 +01001178 u8 up_threshold; /* Current %busy required to uplock */
1179 u8 down_threshold; /* Current %busy required to downclock */
1180
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001181 int last_adj;
1182 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1183
Chris Wilson8d3afd72015-05-21 21:01:47 +01001184 spinlock_t client_lock;
1185 struct list_head clients;
1186 bool client_boost;
1187
Chris Wilsonc0951f02013-10-10 21:58:50 +01001188 bool enabled;
Chris Wilson54b4f682016-07-21 21:16:19 +01001189 struct delayed_work autoenable_work;
Chris Wilson1854d5c2015-04-07 16:20:32 +01001190 unsigned boosts;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001191
Chris Wilsonbf225f22014-07-10 20:31:18 +01001192 /* manual wa residency calculations */
1193 struct intel_rps_ei up_ei, down_ei;
1194
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001195 /*
1196 * Protects RPS/RC6 register access and PCU communication.
Chris Wilson8d3afd72015-05-21 21:01:47 +01001197 * Must be taken after struct_mutex if nested. Note that
1198 * this lock may be held for long periods of time when
1199 * talking to hw - so only take it when talking to hw!
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001200 */
1201 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001202};
1203
Daniel Vetter1a240d42012-11-29 22:18:51 +01001204/* defined intel_pm.c */
1205extern spinlock_t mchdev_lock;
1206
Daniel Vetterc85aa882012-11-02 19:55:03 +01001207struct intel_ilk_power_mgmt {
1208 u8 cur_delay;
1209 u8 min_delay;
1210 u8 max_delay;
1211 u8 fmax;
1212 u8 fstart;
1213
1214 u64 last_count1;
1215 unsigned long last_time1;
1216 unsigned long chipset_power;
1217 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001218 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001219 unsigned long gfx_power;
1220 u8 corr;
1221
1222 int c_m;
1223 int r_t;
1224};
1225
Imre Deakc6cb5822014-03-04 19:22:55 +02001226struct drm_i915_private;
1227struct i915_power_well;
1228
1229struct i915_power_well_ops {
1230 /*
1231 * Synchronize the well's hw state to match the current sw state, for
1232 * example enable/disable it based on the current refcount. Called
1233 * during driver init and resume time, possibly after first calling
1234 * the enable/disable handlers.
1235 */
1236 void (*sync_hw)(struct drm_i915_private *dev_priv,
1237 struct i915_power_well *power_well);
1238 /*
1239 * Enable the well and resources that depend on it (for example
1240 * interrupts located on the well). Called after the 0->1 refcount
1241 * transition.
1242 */
1243 void (*enable)(struct drm_i915_private *dev_priv,
1244 struct i915_power_well *power_well);
1245 /*
1246 * Disable the well and resources that depend on it. Called after
1247 * the 1->0 refcount transition.
1248 */
1249 void (*disable)(struct drm_i915_private *dev_priv,
1250 struct i915_power_well *power_well);
1251 /* Returns the hw enabled state. */
1252 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1253 struct i915_power_well *power_well);
1254};
1255
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001256/* Power well structure for haswell */
1257struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001258 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001259 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001260 /* power well enable/disable usage count */
1261 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001262 /* cached hw enabled state */
1263 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001264 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001265 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001266 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001267};
1268
Imre Deak83c00f52013-10-25 17:36:47 +03001269struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001270 /*
1271 * Power wells needed for initialization at driver init and suspend
1272 * time are on. They are kept on until after the first modeset.
1273 */
1274 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001275 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001276 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001277
Imre Deak83c00f52013-10-25 17:36:47 +03001278 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001279 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001280 struct i915_power_well *power_wells;
Imre Deak83c00f52013-10-25 17:36:47 +03001281};
1282
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001283#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001284struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001285 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001286 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001287 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001288};
1289
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001290struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001291 /** Memory allocator for GTT stolen memory */
1292 struct drm_mm stolen;
Paulo Zanoni92e97d22015-07-02 19:25:09 -03001293 /** Protects the usage of the GTT stolen memory allocator. This is
1294 * always the inner lock when overlapping with struct_mutex. */
1295 struct mutex stolen_lock;
1296
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001297 /** List of all objects in gtt_space. Used to restore gtt
1298 * mappings on resume */
1299 struct list_head bound_list;
1300 /**
1301 * List of objects which are not bound to the GTT (thus
1302 * are idle and not used by the GPU) but still have
1303 * (presumably uncached) pages still attached.
1304 */
1305 struct list_head unbound_list;
1306
1307 /** Usable portion of the GTT for GEM */
1308 unsigned long stolen_base; /* limited to low memory (32-bit) */
1309
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001310 /** PPGTT used for aliasing the PPGTT with the GTT */
1311 struct i915_hw_ppgtt *aliasing_ppgtt;
1312
Chris Wilson2cfcd322014-05-20 08:28:43 +01001313 struct notifier_block oom_notifier;
Chris Wilsone87666b2016-04-04 14:46:43 +01001314 struct notifier_block vmap_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001315 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001316
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001317 /** LRU list of objects with fence regs on them. */
1318 struct list_head fence_list;
1319
1320 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001321 * Are we in a non-interruptible section of code like
1322 * modesetting?
1323 */
1324 bool interruptible;
1325
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001326 /* the indicator for dispatch video commands on two BSD rings */
Chris Wilsonc80ff162016-07-27 09:07:27 +01001327 unsigned int bsd_engine_dispatch_index;
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001328
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001329 /** Bit 6 swizzling required for X tiling */
1330 uint32_t bit_6_swizzle_x;
1331 /** Bit 6 swizzling required for Y tiling */
1332 uint32_t bit_6_swizzle_y;
1333
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001334 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001335 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001336 size_t object_memory;
1337 u32 object_count;
1338};
1339
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001340struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001341 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001342 unsigned bytes;
1343 unsigned size;
1344 int err;
1345 u8 *buf;
1346 loff_t start;
1347 loff_t pos;
1348};
1349
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001350struct i915_error_state_file_priv {
1351 struct drm_device *dev;
1352 struct drm_i915_error_state *error;
1353};
1354
Daniel Vetter99584db2012-11-14 17:14:04 +01001355struct i915_gpu_error {
1356 /* For hangcheck timer */
1357#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1358#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001359 /* Hang gpu twice in this window and your context gets banned */
1360#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1361
Chris Wilson737b1502015-01-26 18:03:03 +02001362 struct delayed_work hangcheck_work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001363
1364 /* For reset and error_state handling. */
1365 spinlock_t lock;
1366 /* Protected by the above dev->gpu_error.lock. */
1367 struct drm_i915_error_state *first_error;
Chris Wilson094f9a52013-09-25 17:34:55 +01001368
1369 unsigned long missed_irq_rings;
1370
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001371 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001372 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001373 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001374 * This is a counter which gets incremented when reset is triggered,
1375 * and again when reset has been handled. So odd values (lowest bit set)
1376 * means that reset is in progress and even values that
1377 * (reset_counter >> 1):th reset was successfully completed.
1378 *
1379 * If reset is not completed succesfully, the I915_WEDGE bit is
1380 * set meaning that hardware is terminally sour and there is no
1381 * recovery. All waiters on the reset_queue will be woken when
1382 * that happens.
1383 *
1384 * This counter is used by the wait_seqno code to notice that reset
1385 * event happened and it needs to restart the entire ioctl (since most
1386 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001387 *
1388 * This is important for lock-free wait paths, where no contended lock
1389 * naturally enforces the correct ordering between the bail-out of the
1390 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001391 */
1392 atomic_t reset_counter;
1393
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001394#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001395#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001396
1397 /**
Chris Wilson1f15b762016-07-01 17:23:14 +01001398 * Waitqueue to signal when a hang is detected. Used to for waiters
1399 * to release the struct_mutex for the reset to procede.
1400 */
1401 wait_queue_head_t wait_queue;
1402
1403 /**
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001404 * Waitqueue to signal when the reset has completed. Used by clients
1405 * that wait for dev_priv->mm.wedged to settle.
1406 */
1407 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001408
Chris Wilson094f9a52013-09-25 17:34:55 +01001409 /* For missed irq/seqno simulation. */
Chris Wilson688e6c72016-07-01 17:23:15 +01001410 unsigned long test_irq_rings;
Daniel Vetter99584db2012-11-14 17:14:04 +01001411};
1412
Zhang Ruib8efb172013-02-05 15:41:53 +08001413enum modeset_restore {
1414 MODESET_ON_LID_OPEN,
1415 MODESET_DONE,
1416 MODESET_SUSPENDED,
1417};
1418
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001419#define DP_AUX_A 0x40
1420#define DP_AUX_B 0x10
1421#define DP_AUX_C 0x20
1422#define DP_AUX_D 0x30
1423
Xiong Zhang11c1b652015-08-17 16:04:04 +08001424#define DDC_PIN_B 0x05
1425#define DDC_PIN_C 0x04
1426#define DDC_PIN_D 0x06
1427
Paulo Zanoni6acab152013-09-12 17:06:24 -03001428struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001429 /*
1430 * This is an index in the HDMI/DVI DDI buffer translation table.
1431 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1432 * populate this field.
1433 */
1434#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001435 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001436
1437 uint8_t supports_dvi:1;
1438 uint8_t supports_hdmi:1;
1439 uint8_t supports_dp:1;
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001440
1441 uint8_t alternate_aux_channel;
Xiong Zhang11c1b652015-08-17 16:04:04 +08001442 uint8_t alternate_ddc_pin;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001443
1444 uint8_t dp_boost_level;
1445 uint8_t hdmi_boost_level;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001446};
1447
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001448enum psr_lines_to_wait {
1449 PSR_0_LINES_TO_WAIT = 0,
1450 PSR_1_LINE_TO_WAIT,
1451 PSR_4_LINES_TO_WAIT,
1452 PSR_8_LINES_TO_WAIT
Pradeep Bhat83a72802014-03-28 10:14:57 +05301453};
1454
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001455struct intel_vbt_data {
1456 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1457 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1458
1459 /* Feature bits */
1460 unsigned int int_tv_support:1;
1461 unsigned int lvds_dither:1;
1462 unsigned int lvds_vbt:1;
1463 unsigned int int_crt_support:1;
1464 unsigned int lvds_use_ssc:1;
1465 unsigned int display_clock_mode:1;
1466 unsigned int fdi_rx_polarity_inverted:1;
Ville Syrjälä3e845c72016-04-08 16:28:12 +03001467 unsigned int panel_type:4;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001468 int lvds_ssc_freq;
1469 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1470
Pradeep Bhat83a72802014-03-28 10:14:57 +05301471 enum drrs_support_type drrs_type;
1472
Jani Nikula6aa23e62016-03-24 17:50:20 +02001473 struct {
1474 int rate;
1475 int lanes;
1476 int preemphasis;
1477 int vswing;
Jani Nikula06411f02016-03-24 17:50:21 +02001478 bool low_vswing;
Jani Nikula6aa23e62016-03-24 17:50:20 +02001479 bool initialized;
1480 bool support;
1481 int bpp;
1482 struct edp_power_seq pps;
1483 } edp;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001484
Jani Nikulaf00076d2013-12-14 20:38:29 -02001485 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001486 bool full_link;
1487 bool require_aux_wakeup;
1488 int idle_frames;
1489 enum psr_lines_to_wait lines_to_wait;
1490 int tp1_wakeup_time;
1491 int tp2_tp3_wakeup_time;
1492 } psr;
1493
1494 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001495 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001496 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001497 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001498 u8 min_brightness; /* min_brightness/255 of max */
Deepak M9a41e172016-04-26 16:14:24 +03001499 enum intel_backlight_type type;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001500 } backlight;
1501
Shobhit Kumard17c5442013-08-27 15:12:25 +03001502 /* MIPI DSI */
1503 struct {
1504 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301505 struct mipi_config *config;
1506 struct mipi_pps_data *pps;
1507 u8 seq_version;
1508 u32 size;
1509 u8 *data;
Jani Nikula8d3ed2f2015-12-21 15:10:57 +02001510 const u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001511 } dsi;
1512
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001513 int crt_ddc_pin;
1514
1515 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001516 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001517
1518 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Jani Nikula9d6c8752016-03-24 17:50:22 +02001519 struct sdvo_device_mapping sdvo_mappings[2];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001520};
1521
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001522enum intel_ddb_partitioning {
1523 INTEL_DDB_PART_1_2,
1524 INTEL_DDB_PART_5_6, /* IVB+ */
1525};
1526
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001527struct intel_wm_level {
1528 bool enable;
1529 uint32_t pri_val;
1530 uint32_t spr_val;
1531 uint32_t cur_val;
1532 uint32_t fbc_val;
1533};
1534
Imre Deak820c1982013-12-17 14:46:36 +02001535struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001536 uint32_t wm_pipe[3];
1537 uint32_t wm_lp[3];
1538 uint32_t wm_lp_spr[3];
1539 uint32_t wm_linetime[3];
1540 bool enable_fbc_wm;
1541 enum intel_ddb_partitioning partitioning;
1542};
1543
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001544struct vlv_pipe_wm {
1545 uint16_t primary;
1546 uint16_t sprite[2];
1547 uint8_t cursor;
1548};
1549
1550struct vlv_sr_wm {
1551 uint16_t plane;
1552 uint8_t cursor;
1553};
1554
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001555struct vlv_wm_values {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001556 struct vlv_pipe_wm pipe[3];
1557 struct vlv_sr_wm sr;
Ville Syrjäläae801522015-03-05 21:19:49 +02001558 struct {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001559 uint8_t cursor;
1560 uint8_t sprite[2];
1561 uint8_t primary;
1562 } ddl[3];
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03001563 uint8_t level;
1564 bool cxsr;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001565};
1566
Damien Lespiauc1939242014-11-04 17:06:41 +00001567struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001568 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001569};
1570
1571static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1572{
Damien Lespiau16160e32014-11-04 17:06:53 +00001573 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001574}
1575
Damien Lespiau08db6652014-11-04 17:06:52 +00001576static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1577 const struct skl_ddb_entry *e2)
1578{
1579 if (e1->start == e2->start && e1->end == e2->end)
1580 return true;
1581
1582 return false;
1583}
1584
Damien Lespiauc1939242014-11-04 17:06:41 +00001585struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001586 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Chandra Konduru2cd601c2015-04-27 15:47:37 -07001587 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
Matt Roper4969d332015-09-24 15:53:10 -07001588 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001589};
1590
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001591struct skl_wm_values {
Matt Roper2b4b9f32016-05-12 07:06:07 -07001592 unsigned dirty_pipes;
Damien Lespiauc1939242014-11-04 17:06:41 +00001593 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001594 uint32_t wm_linetime[I915_MAX_PIPES];
1595 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001596 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001597};
1598
1599struct skl_wm_level {
1600 bool plane_en[I915_MAX_PLANES];
1601 uint16_t plane_res_b[I915_MAX_PLANES];
1602 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001603};
1604
Paulo Zanonic67a4702013-08-19 13:18:09 -03001605/*
Paulo Zanoni765dab672014-03-07 20:08:18 -03001606 * This struct helps tracking the state needed for runtime PM, which puts the
1607 * device in PCI D3 state. Notice that when this happens, nothing on the
1608 * graphics device works, even register access, so we don't get interrupts nor
1609 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001610 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001611 * Every piece of our code that needs to actually touch the hardware needs to
1612 * either call intel_runtime_pm_get or call intel_display_power_get with the
1613 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001614 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001615 * Our driver uses the autosuspend delay feature, which means we'll only really
1616 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001617 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab672014-03-07 20:08:18 -03001618 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001619 *
1620 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1621 * goes back to false exactly before we reenable the IRQs. We use this variable
1622 * to check if someone is trying to enable/disable IRQs while they're supposed
1623 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001624 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001625 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001626 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001627 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001628struct i915_runtime_pm {
Imre Deak1f814da2015-12-16 02:52:19 +02001629 atomic_t wakeref_count;
Imre Deak2b19efe2015-12-15 20:10:37 +02001630 atomic_t atomic_seq;
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001631 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001632 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001633};
1634
Daniel Vetter926321d2013-10-16 13:30:34 +02001635enum intel_pipe_crc_source {
1636 INTEL_PIPE_CRC_SOURCE_NONE,
1637 INTEL_PIPE_CRC_SOURCE_PLANE1,
1638 INTEL_PIPE_CRC_SOURCE_PLANE2,
1639 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001640 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001641 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1642 INTEL_PIPE_CRC_SOURCE_TV,
1643 INTEL_PIPE_CRC_SOURCE_DP_B,
1644 INTEL_PIPE_CRC_SOURCE_DP_C,
1645 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001646 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001647 INTEL_PIPE_CRC_SOURCE_MAX,
1648};
1649
Shuang He8bf1e9f2013-10-15 18:55:27 +01001650struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001651 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001652 uint32_t crc[5];
1653};
1654
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001655#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001656struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001657 spinlock_t lock;
1658 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001659 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001660 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001661 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001662 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001663};
1664
Daniel Vetterf99d7062014-06-19 16:01:59 +02001665struct i915_frontbuffer_tracking {
Chris Wilsonb5add952016-08-04 16:32:36 +01001666 spinlock_t lock;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001667
1668 /*
1669 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1670 * scheduled flips.
1671 */
1672 unsigned busy_bits;
1673 unsigned flip_bits;
1674};
1675
Mika Kuoppala72253422014-10-07 17:21:26 +03001676struct i915_wa_reg {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001677 i915_reg_t addr;
Mika Kuoppala72253422014-10-07 17:21:26 +03001678 u32 value;
1679 /* bitmask representing WA bits */
1680 u32 mask;
1681};
1682
Arun Siluvery33136b02016-01-21 21:43:47 +00001683/*
1684 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1685 * allowing it for RCS as we don't foresee any requirement of having
1686 * a whitelist for other engines. When it is really required for
1687 * other engines then the limit need to be increased.
1688 */
1689#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
Mika Kuoppala72253422014-10-07 17:21:26 +03001690
1691struct i915_workarounds {
1692 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1693 u32 count;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001694 u32 hw_whitelist_count[I915_NUM_ENGINES];
Mika Kuoppala72253422014-10-07 17:21:26 +03001695};
1696
Yu Zhangcf9d2892015-02-10 19:05:47 +08001697struct i915_virtual_gpu {
1698 bool active;
1699};
1700
Matt Roperaa363132015-09-24 15:53:18 -07001701/* used in computing the new watermarks state */
1702struct intel_wm_config {
1703 unsigned int num_pipes_active;
1704 bool sprites_enabled;
1705 bool sprites_scaled;
1706};
1707
Jani Nikula77fec552014-03-31 14:27:22 +03001708struct drm_i915_private {
Chris Wilson8f460e22016-06-24 14:00:18 +01001709 struct drm_device drm;
1710
Chris Wilsonefab6d82015-04-07 16:20:57 +01001711 struct kmem_cache *objects;
Chris Wilsone20d2ab2015-04-07 16:20:58 +01001712 struct kmem_cache *vmas;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001713 struct kmem_cache *requests;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001714
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001715 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001716
1717 int relative_constants_mode;
1718
1719 void __iomem *regs;
1720
Chris Wilson907b28c2013-07-19 20:36:52 +01001721 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001722
Yu Zhangcf9d2892015-02-10 19:05:47 +08001723 struct i915_virtual_gpu vgpu;
1724
Zhi Wang0ad35fe2016-06-16 08:07:00 -04001725 struct intel_gvt gvt;
1726
Alex Dai33a732f2015-08-12 15:43:36 +01001727 struct intel_guc guc;
1728
Daniel Vettereb805622015-05-04 14:58:44 +02001729 struct intel_csr csr;
1730
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03001731 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
Daniel Vetter28c70f12012-12-01 13:53:45 +01001732
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001733 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1734 * controller on different i2c buses. */
1735 struct mutex gmbus_mutex;
1736
1737 /**
1738 * Base address of the gmbus and gpio block.
1739 */
1740 uint32_t gpio_mmio_base;
1741
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301742 /* MMIO base address for MIPI regs */
1743 uint32_t mipi_mmio_base;
1744
Ville Syrjälä443a3892015-11-11 20:34:15 +02001745 uint32_t psr_mmio_base;
1746
Imre Deak44cb7342016-08-10 14:07:29 +03001747 uint32_t pps_mmio_base;
1748
Daniel Vetter28c70f12012-12-01 13:53:45 +01001749 wait_queue_head_t gmbus_wait_queue;
1750
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001751 struct pci_dev *bridge_dev;
Chris Wilson0ca5fa32016-05-24 14:53:40 +01001752 struct i915_gem_context *kernel_context;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001753 struct intel_engine_cs engine[I915_NUM_ENGINES];
Ben Widawsky3e789982014-06-30 09:53:37 -07001754 struct drm_i915_gem_object *semaphore_obj;
Chris Wilsonddf07be2016-08-02 22:50:39 +01001755 u32 next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001756
Daniel Vetterba8286f2014-09-11 07:43:25 +02001757 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001758 struct resource mch_res;
1759
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001760 /* protects the irq masks */
1761 spinlock_t irq_lock;
1762
Sourab Gupta84c33a62014-06-02 16:47:17 +05301763 /* protects the mmio flip data */
1764 spinlock_t mmio_flip_lock;
1765
Imre Deakf8b79e52014-03-04 19:23:07 +02001766 bool display_irqs_enabled;
1767
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001768 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1769 struct pm_qos_request pm_qos;
1770
Ville Syrjäläa5805162015-05-26 20:42:30 +03001771 /* Sideband mailbox protection */
1772 struct mutex sb_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001773
1774 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001775 union {
1776 u32 irq_mask;
1777 u32 de_irq_mask[I915_MAX_PIPES];
1778 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001779 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001780 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301781 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001782 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001783
Jani Nikula5fcece82015-05-27 15:03:42 +03001784 struct i915_hotplug hotplug;
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001785 struct intel_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301786 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001787 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001788 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001789
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001790 bool preserve_bios_swizzle;
1791
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001792 /* overlay */
1793 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001794
Jani Nikula58c68772013-11-08 16:48:54 +02001795 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001796 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001797
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001798 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001799 bool no_aux_handshake;
1800
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001801 /* protects panel power sequencer state */
1802 struct mutex pps_mutex;
1803
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001804 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001805 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1806
1807 unsigned int fsb_freq, mem_freq, is_ddr3;
Ville Syrjäläb2045352016-05-13 23:41:27 +03001808 unsigned int skl_preferred_vco_freq;
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01001809 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
Mika Kaholaadafdc62015-08-18 14:36:59 +03001810 unsigned int max_dotclk_freq;
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +02001811 unsigned int rawclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001812 unsigned int hpll_freq;
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03001813 unsigned int czclk_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001814
Ville Syrjälä63911d72016-05-13 23:41:32 +03001815 struct {
Ville Syrjälä709e05c2016-05-13 23:41:33 +03001816 unsigned int vco, ref;
Ville Syrjälä63911d72016-05-13 23:41:32 +03001817 } cdclk_pll;
1818
Daniel Vetter645416f2013-09-02 16:22:25 +02001819 /**
1820 * wq - Driver workqueue for GEM.
1821 *
1822 * NOTE: Work items scheduled here are not allowed to grab any modeset
1823 * locks, for otherwise the flushing done in the pageflip code will
1824 * result in deadlocks.
1825 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001826 struct workqueue_struct *wq;
1827
1828 /* Display functions */
1829 struct drm_i915_display_funcs display;
1830
1831 /* PCH chipset type */
1832 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001833 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001834
1835 unsigned long quirks;
1836
Zhang Ruib8efb172013-02-05 15:41:53 +08001837 enum modeset_restore modeset_restore;
1838 struct mutex modeset_restore_lock;
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01001839 struct drm_atomic_state *modeset_restore_state;
Maarten Lankhorst73974892016-08-05 23:28:27 +03001840 struct drm_modeset_acquire_ctx reset_ctx;
Eric Anholt673a3942008-07-30 12:06:12 -07001841
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001842 struct list_head vm_list; /* Global list of all address spaces */
Joonas Lahtinen62106b42016-03-18 10:42:57 +02001843 struct i915_ggtt ggtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001844
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001845 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001846 DECLARE_HASHTABLE(mm_structs, 7);
1847 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001848
Chris Wilson5d1808e2016-04-28 09:56:51 +01001849 /* The hw wants to have a stable context identifier for the lifetime
1850 * of the context (for OA, PASID, faults, etc). This is limited
1851 * in execlists to 21 bits.
1852 */
1853 struct ida context_hw_ida;
1854#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1855
Daniel Vetter87813422012-05-02 11:49:32 +02001856 /* Kernel Modesetting */
1857
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001858 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1859 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001860 wait_queue_head_t pending_flip_queue;
1861
Daniel Vetterc4597872013-10-21 21:04:07 +02001862#ifdef CONFIG_DEBUG_FS
1863 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1864#endif
1865
Maarten Lankhorst565602d2015-12-10 12:33:57 +01001866 /* dpll and cdclk state is protected by connection_mutex */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001867 int num_shared_dpll;
1868 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Ander Conselvan de Oliveiraf9476a62016-03-08 17:46:22 +02001869 const struct intel_dpll_mgr *dpll_mgr;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01001870
Maarten Lankhorstfbf6d872016-03-23 14:51:12 +01001871 /*
1872 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1873 * Must be global rather than per dpll, because on some platforms
1874 * plls share registers.
1875 */
1876 struct mutex dpll_lock;
1877
Maarten Lankhorst565602d2015-12-10 12:33:57 +01001878 unsigned int active_crtcs;
1879 unsigned int min_pixclk[I915_MAX_PIPES];
1880
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001881 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001882
Mika Kuoppala72253422014-10-07 17:21:26 +03001883 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001884
Daniel Vetterf99d7062014-06-19 16:01:59 +02001885 struct i915_frontbuffer_tracking fb_tracking;
1886
Jesse Barnes652c3932009-08-17 13:31:43 -07001887 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001888
Zhenyu Wangc48044112009-12-17 14:48:43 +08001889 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001890
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001891 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001892
Ben Widawsky59124502013-07-04 11:02:05 -07001893 /* Cannot be determined by PCIID. You must always read a register. */
Mika Kuoppala3accaf72016-04-13 17:26:43 +03001894 u32 edram_cap;
Ben Widawsky59124502013-07-04 11:02:05 -07001895
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001896 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001897 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001898
Daniel Vetter20e4d402012-08-08 23:35:39 +02001899 /* ilk-only ips/rps state. Everything in here is protected by the global
1900 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001901 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001902
Imre Deak83c00f52013-10-25 17:36:47 +03001903 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001904
Rodrigo Vivia031d702013-10-03 16:15:06 -03001905 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001906
Daniel Vetter99584db2012-11-14 17:14:04 +01001907 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001908
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001909 struct drm_i915_gem_object *vlv_pctx;
1910
Daniel Vetter06957262015-08-10 13:34:08 +02001911#ifdef CONFIG_DRM_FBDEV_EMULATION
Dave Airlie8be48d92010-03-30 05:34:14 +00001912 /* list of fbdev register on this device */
1913 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001914 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001915#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001916
1917 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001918 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001919
Imre Deak58fddc22015-01-08 17:54:14 +02001920 /* hda/i915 audio component */
David Henningsson51e1d832015-08-19 10:48:56 +02001921 struct i915_audio_component *audio_component;
Imre Deak58fddc22015-01-08 17:54:14 +02001922 bool audio_component_registered;
Libin Yang4a21ef72015-09-02 14:11:39 +08001923 /**
1924 * av_mutex - mutex for audio/video sync
1925 *
1926 */
1927 struct mutex av_mutex;
Imre Deak58fddc22015-01-08 17:54:14 +02001928
Ben Widawsky254f9652012-06-04 14:42:42 -07001929 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001930 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001931
Damien Lespiau3e683202012-12-11 18:48:29 +00001932 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001933
Ville Syrjäläc2317752016-03-15 16:39:56 +02001934 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
Ville Syrjälä70722462015-04-10 18:21:28 +03001935 u32 chv_phy_control;
Ville Syrjäläc2317752016-03-15 16:39:56 +02001936 /*
1937 * Shadows for CHV DPLL_MD regs to keep the state
1938 * checker somewhat working in the presence hardware
1939 * crappiness (can't read out DPLL_MD for pipes B & C).
1940 */
1941 u32 chv_dpll_md[I915_MAX_PIPES];
Imre Deakadc7f042016-04-04 17:27:10 +03001942 u32 bxt_phy_grc;
Ville Syrjälä70722462015-04-10 18:21:28 +03001943
Daniel Vetter842f1c82014-03-10 10:01:44 +01001944 u32 suspend_count;
Imre Deakbc872292015-11-18 17:32:30 +02001945 bool suspended_to_idle;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001946 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001947 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001948
Ville Syrjälä53615a52013-08-01 16:18:50 +03001949 struct {
1950 /*
1951 * Raw watermark latency values:
1952 * in 0.1us units for WM0,
1953 * in 0.5us units for WM1+.
1954 */
1955 /* primary */
1956 uint16_t pri_latency[5];
1957 /* sprite */
1958 uint16_t spr_latency[5];
1959 /* cursor */
1960 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001961 /*
1962 * Raw watermark memory latency values
1963 * for SKL for all 8 levels
1964 * in 1us units.
1965 */
1966 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001967
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001968 /*
1969 * The skl_wm_values structure is a bit too big for stack
1970 * allocation, so we keep the staging struct where we store
1971 * intermediate results here instead.
1972 */
1973 struct skl_wm_values skl_results;
1974
Ville Syrjälä609cede2013-10-09 19:18:03 +03001975 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001976 union {
1977 struct ilk_wm_values hw;
1978 struct skl_wm_values skl_hw;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001979 struct vlv_wm_values vlv;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001980 };
Ville Syrjälä58590c12015-09-08 21:05:12 +03001981
1982 uint8_t max_level;
Matt Ropered4a6a72016-02-23 17:20:13 -08001983
1984 /*
1985 * Should be held around atomic WM register writing; also
1986 * protects * intel_crtc->wm.active and
1987 * cstate->wm.need_postvbl_update.
1988 */
1989 struct mutex wm_mutex;
Matt Roper279e99d2016-05-12 07:06:02 -07001990
1991 /*
1992 * Set during HW readout of watermarks/DDB. Some platforms
1993 * need to know when we're still using BIOS-provided values
1994 * (which we don't fully trust).
1995 */
1996 bool distrust_bios_wm;
Ville Syrjälä53615a52013-08-01 16:18:50 +03001997 } wm;
1998
Paulo Zanoni8a187452013-12-06 20:32:13 -02001999 struct i915_runtime_pm pm;
2000
Oscar Mateoa83014d2014-07-24 17:04:21 +01002001 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2002 struct {
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00002003 void (*cleanup_engine)(struct intel_engine_cs *engine);
Chris Wilson67d97da2016-07-04 08:08:31 +01002004
2005 /**
2006 * Is the GPU currently considered idle, or busy executing
2007 * userspace requests? Whilst idle, we allow runtime power
2008 * management to power down the hardware and display clocks.
2009 * In order to reduce the effect on performance, there
2010 * is a slight delay before we do so.
2011 */
2012 unsigned int active_engines;
2013 bool awake;
2014
2015 /**
2016 * We leave the user IRQ off as much as possible,
2017 * but this means that requests will finish and never
2018 * be retired once the system goes idle. Set a timer to
2019 * fire periodically while the ring is running. When it
2020 * fires, go retire requests.
2021 */
2022 struct delayed_work retire_work;
2023
2024 /**
2025 * When we detect an idle GPU, we want to turn on
2026 * powersaving features. So once we see that there
2027 * are no more requests outstanding and no more
2028 * arrive within a small period of time, we fire
2029 * off the idle_work.
2030 */
2031 struct delayed_work idle_work;
Oscar Mateoa83014d2014-07-24 17:04:21 +01002032 } gt;
2033
Ville Syrjälä3be60de2015-09-08 18:05:45 +03002034 /* perform PHY state sanity checks? */
2035 bool chv_phy_assert[2];
2036
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01002037 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2038
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02002039 /*
2040 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2041 * will be rejected. Instead look for a better place.
2042 */
Jani Nikula77fec552014-03-31 14:27:22 +03002043};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002044
Chris Wilson2c1792a2013-08-01 18:39:55 +01002045static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2046{
Chris Wilson091387c2016-06-24 14:00:21 +01002047 return container_of(dev, struct drm_i915_private, drm);
Chris Wilson2c1792a2013-08-01 18:39:55 +01002048}
2049
Imre Deak888d0d42015-01-08 17:54:13 +02002050static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2051{
2052 return to_i915(dev_get_drvdata(dev));
2053}
2054
Alex Dai33a732f2015-08-12 15:43:36 +01002055static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2056{
2057 return container_of(guc, struct drm_i915_private, guc);
2058}
2059
Dave Gordonb4ac5af2016-03-24 11:20:38 +00002060/* Simple iterator over all initialised engines */
2061#define for_each_engine(engine__, dev_priv__) \
2062 for ((engine__) = &(dev_priv__)->engine[0]; \
2063 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2064 (engine__)++) \
2065 for_each_if (intel_engine_initialized(engine__))
Chris Wilsonb4519512012-05-11 14:29:30 +01002066
Dave Gordonc3232b12016-03-23 18:19:53 +00002067/* Iterator with engine_id */
2068#define for_each_engine_id(engine__, dev_priv__, id__) \
2069 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2070 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2071 (engine__)++) \
2072 for_each_if (((id__) = (engine__)->id, \
2073 intel_engine_initialized(engine__)))
2074
2075/* Iterator over subset of engines selected by mask */
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002076#define for_each_engine_masked(engine__, dev_priv__, mask__) \
Dave Gordonb4ac5af2016-03-24 11:20:38 +00002077 for ((engine__) = &(dev_priv__)->engine[0]; \
2078 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2079 (engine__)++) \
2080 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2081 intel_engine_initialized(engine__))
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002082
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08002083enum hdmi_force_audio {
2084 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2085 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2086 HDMI_AUDIO_AUTO, /* trust EDID */
2087 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2088};
2089
Daniel Vetter190d6cd2013-07-04 13:06:28 +02002090#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00002091
Chris Wilson37e680a2012-06-07 15:38:42 +01002092struct drm_i915_gem_object_ops {
Chris Wilsonde472662016-01-22 18:32:31 +00002093 unsigned int flags;
2094#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2095
Chris Wilson37e680a2012-06-07 15:38:42 +01002096 /* Interface between the GEM object and its backing storage.
2097 * get_pages() is called once prior to the use of the associated set
2098 * of pages before to binding them into the GTT, and put_pages() is
2099 * called after we no longer need them. As we expect there to be
2100 * associated cost with migrating pages between the backing storage
2101 * and making them available for the GPU (e.g. clflush), we may hold
2102 * onto the pages after they are no longer referenced by the GPU
2103 * in case they may be used again shortly (for example migrating the
2104 * pages to a different memory domain within the GTT). put_pages()
2105 * will therefore most likely be called when the object itself is
2106 * being released or under memory pressure (where we attempt to
2107 * reap pages for the shrinker).
2108 */
2109 int (*get_pages)(struct drm_i915_gem_object *);
2110 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilsonde472662016-01-22 18:32:31 +00002111
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002112 int (*dmabuf_export)(struct drm_i915_gem_object *);
2113 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01002114};
2115
Daniel Vettera071fa02014-06-18 23:28:09 +02002116/*
2117 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302118 * considered to be the frontbuffer for the given plane interface-wise. This
Daniel Vettera071fa02014-06-18 23:28:09 +02002119 * doesn't mean that the hw necessarily already scans it out, but that any
2120 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2121 *
2122 * We have one bit per pipe and per scanout plane type.
2123 */
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302124#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2125#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
Daniel Vettera071fa02014-06-18 23:28:09 +02002126#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2127 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2128#define INTEL_FRONTBUFFER_CURSOR(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302129 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2130#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2131 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettera071fa02014-06-18 23:28:09 +02002132#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302133 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02002134#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302135 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02002136
Eric Anholt673a3942008-07-30 12:06:12 -07002137struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00002138 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07002139
Chris Wilson37e680a2012-06-07 15:38:42 +01002140 const struct drm_i915_gem_object_ops *ops;
2141
Ben Widawsky2f633152013-07-17 12:19:03 -07002142 /** List of VMAs backed by this object */
2143 struct list_head vma_list;
2144
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00002145 /** Stolen memory for this object, instead of being backed by shmem. */
2146 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07002147 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07002148
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02002149 /** Used in execbuf to temporarily hold a ref */
2150 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07002151
Chris Wilson8d9d5742015-04-07 16:20:38 +01002152 struct list_head batch_pool_link;
Brad Volkin493018d2014-12-11 12:13:08 -08002153
Chris Wilson573adb32016-08-04 16:32:39 +01002154 unsigned long flags;
Eric Anholt673a3942008-07-30 12:06:12 -07002155 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01002156 * This is set if the object is on the active lists (has pending
2157 * rendering and so a non-zero seqno), and is not set if it i s on
2158 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07002159 */
Chris Wilson573adb32016-08-04 16:32:39 +01002160#define I915_BO_ACTIVE_SHIFT 0
2161#define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2162#define __I915_BO_ACTIVE(bo) \
2163 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
Eric Anholt673a3942008-07-30 12:06:12 -07002164
2165 /**
2166 * This is set if the object has been written to since last bound
2167 * to the GTT
2168 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002169 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002170
2171 /**
2172 * Fence register bits (if any) for this object. Will be set
2173 * as needed when mapped into the GTT.
2174 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02002175 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02002176 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02002177
2178 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002179 * Advice: are the backing pages purgeable?
2180 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002181 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02002182
2183 /**
Chris Wilson5d82e3e2012-04-21 16:23:23 +01002184 * Whether the tiling parameters for the currently associated fence
2185 * register have changed. Note that for the purposes of tracking
2186 * tiling changes we also treat the unfenced register, the register
2187 * slot that the object occupies whilst it executes a fenced
2188 * command (such as BLT on gen2/3), as a "fence".
2189 */
2190 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002191
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002192 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01002193 * Is the object at the current location in the gtt mappable and
2194 * fenceable? Used to avoid costly recalculations.
2195 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002196 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01002197
2198 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002199 * Whether the current gtt mapping needs to be mappable (and isn't just
2200 * mappable by accident). Track pin and fault separate for a more
2201 * accurate mappable working set.
2202 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002203 unsigned int fault_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002204
Chris Wilsoncaea7472010-11-12 13:53:37 +00002205 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05302206 * Is the object to be mapped as read-only to the GPU
2207 * Only honoured if hardware has relevant pte bit
2208 */
2209 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01002210 unsigned int cache_level:3;
Chris Wilson0f719792015-01-13 13:32:52 +00002211 unsigned int cache_dirty:1;
Chris Wilson93dfb402011-03-29 16:59:50 -07002212
Chris Wilsonfaf5bf02016-08-04 16:32:37 +01002213 atomic_t frontbuffer_bits;
Daniel Vettera071fa02014-06-18 23:28:09 +02002214
Chris Wilson9ad36762016-08-05 10:14:21 +01002215 /** Current tiling stride for the object, if it's tiled. */
Chris Wilson3e510a82016-08-05 10:14:23 +01002216 unsigned int tiling_and_stride;
2217#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2218#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2219#define STRIDE_MASK (~TILING_MASK)
Chris Wilson9ad36762016-08-05 10:14:21 +01002220
Chris Wilsonaeecc962016-06-17 14:46:39 -03002221 unsigned int has_wc_mmap;
Chris Wilson15717de2016-08-04 07:52:26 +01002222 /** Count of VMA actually bound by this object */
2223 unsigned int bind_count;
Tvrtko Ursulin8a0c39b2015-04-13 11:50:09 +01002224 unsigned int pin_display;
2225
Chris Wilson9da3da62012-06-01 15:20:22 +01002226 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01002227 int pages_pin_count;
Chris Wilsonee286372015-04-07 16:20:25 +01002228 struct get_page {
2229 struct scatterlist *sg;
2230 int last;
2231 } get_page;
Chris Wilson0a798eb2016-04-08 12:11:11 +01002232 void *mapping;
Dave Airlie9a70cc22012-05-22 13:09:21 +01002233
Chris Wilsonb4716182015-04-27 13:41:17 +01002234 /** Breadcrumb of last rendering to the buffer.
2235 * There can only be one writer, but we allow for multiple readers.
2236 * If there is a writer that necessarily implies that all other
2237 * read requests are complete - but we may only be lazily clearing
2238 * the read requests. A read request is naturally the most recent
2239 * request on a ring, so we may have two different write and read
2240 * requests on one ring where the write request is older than the
2241 * read request. This allows for the CPU to read from an active
2242 * buffer by only waiting for the write to complete.
Chris Wilson381f3712016-08-04 07:52:29 +01002243 */
2244 struct i915_gem_active last_read[I915_NUM_ENGINES];
2245 struct i915_gem_active last_write;
2246 struct i915_gem_active last_fence;
Eric Anholt673a3942008-07-30 12:06:12 -07002247
Daniel Vetter80075d42013-10-09 21:23:52 +02002248 /** References from framebuffers, locks out tiling changes. */
2249 unsigned long framebuffer_references;
2250
Eric Anholt280b7132009-03-12 16:56:27 -07002251 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01002252 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07002253
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002254 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08002255 /** for phy allocated objects */
2256 struct drm_dma_handle *phys_handle;
2257
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002258 struct i915_gem_userptr {
2259 uintptr_t ptr;
2260 unsigned read_only :1;
2261 unsigned workers :4;
2262#define I915_GEM_USERPTR_MAX_WORKERS 15
2263
Chris Wilsonad46cb52014-08-07 14:20:40 +01002264 struct i915_mm_struct *mm;
2265 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002266 struct work_struct *work;
2267 } userptr;
2268 };
2269};
Chris Wilson03ac0642016-07-20 13:31:51 +01002270
2271static inline struct drm_i915_gem_object *
2272to_intel_bo(struct drm_gem_object *gem)
2273{
2274 /* Assert that to_intel_bo(NULL) == NULL */
2275 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
2276
2277 return container_of(gem, struct drm_i915_gem_object, base);
2278}
2279
2280static inline struct drm_i915_gem_object *
2281i915_gem_object_lookup(struct drm_file *file, u32 handle)
2282{
2283 return to_intel_bo(drm_gem_object_lookup(file, handle));
2284}
2285
2286__deprecated
2287extern struct drm_gem_object *
2288drm_gem_object_lookup(struct drm_file *file, u32 handle);
Daniel Vetter23010e42010-03-08 13:35:02 +01002289
Chris Wilson25dc5562016-07-20 13:31:52 +01002290__attribute__((nonnull))
2291static inline struct drm_i915_gem_object *
2292i915_gem_object_get(struct drm_i915_gem_object *obj)
2293{
2294 drm_gem_object_reference(&obj->base);
2295 return obj;
2296}
2297
2298__deprecated
2299extern void drm_gem_object_reference(struct drm_gem_object *);
2300
Chris Wilsonf8c417c2016-07-20 13:31:53 +01002301__attribute__((nonnull))
2302static inline void
2303i915_gem_object_put(struct drm_i915_gem_object *obj)
2304{
2305 drm_gem_object_unreference(&obj->base);
2306}
2307
2308__deprecated
2309extern void drm_gem_object_unreference(struct drm_gem_object *);
2310
Chris Wilson34911fd2016-07-20 13:31:54 +01002311__attribute__((nonnull))
2312static inline void
2313i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
2314{
2315 drm_gem_object_unreference_unlocked(&obj->base);
2316}
2317
2318__deprecated
2319extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
2320
Chris Wilsonb9bcd142016-06-20 15:05:51 +01002321static inline bool
2322i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2323{
2324 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2325}
2326
Chris Wilson573adb32016-08-04 16:32:39 +01002327static inline unsigned long
2328i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
2329{
2330 return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
2331}
2332
2333static inline bool
2334i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
2335{
2336 return i915_gem_object_get_active(obj);
2337}
2338
2339static inline void
2340i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
2341{
2342 obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
2343}
2344
2345static inline void
2346i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
2347{
2348 obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
2349}
2350
2351static inline bool
2352i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
2353 int engine)
2354{
2355 return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
2356}
2357
Chris Wilson3e510a82016-08-05 10:14:23 +01002358static inline unsigned int
2359i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
2360{
2361 return obj->tiling_and_stride & TILING_MASK;
2362}
2363
2364static inline bool
2365i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
2366{
2367 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
2368}
2369
2370static inline unsigned int
2371i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
2372{
2373 return obj->tiling_and_stride & STRIDE_MASK;
2374}
2375
Chris Wilson624192c2016-08-15 10:48:50 +01002376static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
2377{
2378 i915_gem_object_get(vma->obj);
2379 return vma;
2380}
2381
2382static inline void i915_vma_put(struct i915_vma *vma)
2383{
2384 lockdep_assert_held(&vma->vm->dev->struct_mutex);
2385 i915_gem_object_put(vma->obj);
2386}
2387
Dave Gordon85d12252016-05-20 11:54:06 +01002388/*
2389 * Optimised SGL iterator for GEM objects
2390 */
2391static __always_inline struct sgt_iter {
2392 struct scatterlist *sgp;
2393 union {
2394 unsigned long pfn;
2395 dma_addr_t dma;
2396 };
2397 unsigned int curr;
2398 unsigned int max;
2399} __sgt_iter(struct scatterlist *sgl, bool dma) {
2400 struct sgt_iter s = { .sgp = sgl };
2401
2402 if (s.sgp) {
2403 s.max = s.curr = s.sgp->offset;
2404 s.max += s.sgp->length;
2405 if (dma)
2406 s.dma = sg_dma_address(s.sgp);
2407 else
2408 s.pfn = page_to_pfn(sg_page(s.sgp));
2409 }
2410
2411 return s;
2412}
2413
2414/**
Dave Gordon63d15322016-05-20 11:54:07 +01002415 * __sg_next - return the next scatterlist entry in a list
2416 * @sg: The current sg entry
2417 *
2418 * Description:
2419 * If the entry is the last, return NULL; otherwise, step to the next
2420 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2421 * otherwise just return the pointer to the current element.
2422 **/
2423static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2424{
2425#ifdef CONFIG_DEBUG_SG
2426 BUG_ON(sg->sg_magic != SG_MAGIC);
2427#endif
2428 return sg_is_last(sg) ? NULL :
2429 likely(!sg_is_chain(++sg)) ? sg :
2430 sg_chain_ptr(sg);
2431}
2432
2433/**
Dave Gordon85d12252016-05-20 11:54:06 +01002434 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2435 * @__dmap: DMA address (output)
2436 * @__iter: 'struct sgt_iter' (iterator state, internal)
2437 * @__sgt: sg_table to iterate over (input)
2438 */
2439#define for_each_sgt_dma(__dmap, __iter, __sgt) \
2440 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2441 ((__dmap) = (__iter).dma + (__iter).curr); \
2442 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
Dave Gordon63d15322016-05-20 11:54:07 +01002443 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
Dave Gordon85d12252016-05-20 11:54:06 +01002444
2445/**
2446 * for_each_sgt_page - iterate over the pages of the given sg_table
2447 * @__pp: page pointer (output)
2448 * @__iter: 'struct sgt_iter' (iterator state, internal)
2449 * @__sgt: sg_table to iterate over (input)
2450 */
2451#define for_each_sgt_page(__pp, __iter, __sgt) \
2452 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2453 ((__pp) = (__iter).pfn == 0 ? NULL : \
2454 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2455 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
Dave Gordon63d15322016-05-20 11:54:07 +01002456 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
Daniel Vettera071fa02014-06-18 23:28:09 +02002457
Brad Volkin351e3db2014-02-18 10:15:46 -08002458/*
2459 * A command that requires special handling by the command parser.
2460 */
2461struct drm_i915_cmd_descriptor {
2462 /*
2463 * Flags describing how the command parser processes the command.
2464 *
2465 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2466 * a length mask if not set
2467 * CMD_DESC_SKIP: The command is allowed but does not follow the
2468 * standard length encoding for the opcode range in
2469 * which it falls
2470 * CMD_DESC_REJECT: The command is never allowed
2471 * CMD_DESC_REGISTER: The command should be checked against the
2472 * register whitelist for the appropriate ring
2473 * CMD_DESC_MASTER: The command is allowed if the submitting process
2474 * is the DRM master
2475 */
2476 u32 flags;
2477#define CMD_DESC_FIXED (1<<0)
2478#define CMD_DESC_SKIP (1<<1)
2479#define CMD_DESC_REJECT (1<<2)
2480#define CMD_DESC_REGISTER (1<<3)
2481#define CMD_DESC_BITMASK (1<<4)
2482#define CMD_DESC_MASTER (1<<5)
2483
2484 /*
2485 * The command's unique identification bits and the bitmask to get them.
2486 * This isn't strictly the opcode field as defined in the spec and may
2487 * also include type, subtype, and/or subop fields.
2488 */
2489 struct {
2490 u32 value;
2491 u32 mask;
2492 } cmd;
2493
2494 /*
2495 * The command's length. The command is either fixed length (i.e. does
2496 * not include a length field) or has a length field mask. The flag
2497 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2498 * a length mask. All command entries in a command table must include
2499 * length information.
2500 */
2501 union {
2502 u32 fixed;
2503 u32 mask;
2504 } length;
2505
2506 /*
2507 * Describes where to find a register address in the command to check
2508 * against the ring's register whitelist. Only valid if flags has the
2509 * CMD_DESC_REGISTER bit set.
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002510 *
2511 * A non-zero step value implies that the command may access multiple
2512 * registers in sequence (e.g. LRI), in that case step gives the
2513 * distance in dwords between individual offset fields.
Brad Volkin351e3db2014-02-18 10:15:46 -08002514 */
2515 struct {
2516 u32 offset;
2517 u32 mask;
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002518 u32 step;
Brad Volkin351e3db2014-02-18 10:15:46 -08002519 } reg;
2520
2521#define MAX_CMD_DESC_BITMASKS 3
2522 /*
2523 * Describes command checks where a particular dword is masked and
2524 * compared against an expected value. If the command does not match
2525 * the expected value, the parser rejects it. Only valid if flags has
2526 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2527 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002528 *
2529 * If the check specifies a non-zero condition_mask then the parser
2530 * only performs the check when the bits specified by condition_mask
2531 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002532 */
2533 struct {
2534 u32 offset;
2535 u32 mask;
2536 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002537 u32 condition_offset;
2538 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002539 } bits[MAX_CMD_DESC_BITMASKS];
2540};
2541
2542/*
2543 * A table of commands requiring special handling by the command parser.
2544 *
Chris Wilson33a051a2016-07-27 09:07:26 +01002545 * Each engine has an array of tables. Each table consists of an array of
2546 * command descriptors, which must be sorted with command opcodes in
2547 * ascending order.
Brad Volkin351e3db2014-02-18 10:15:46 -08002548 */
2549struct drm_i915_cmd_table {
2550 const struct drm_i915_cmd_descriptor *table;
2551 int count;
2552};
2553
Chris Wilsondbbe9122014-08-09 19:18:43 +01002554/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002555#define __I915__(p) ({ \
2556 struct drm_i915_private *__p; \
2557 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2558 __p = (struct drm_i915_private *)p; \
2559 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2560 __p = to_i915((struct drm_device *)p); \
2561 else \
2562 BUILD_BUG(); \
2563 __p; \
2564})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002565#define INTEL_INFO(p) (&__I915__(p)->info)
Jani Nikula3f10e822016-04-07 12:48:17 +03002566#define INTEL_GEN(p) (INTEL_INFO(p)->gen)
Chris Wilson87f1f462014-08-09 19:18:42 +01002567#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Zou Nan haicae58522010-11-09 17:17:32 +08002568
Jani Nikulae87a0052015-10-20 15:22:02 +03002569#define REVID_FOREVER 0xff
Chris Wilson091387c2016-06-24 14:00:21 +01002570#define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
Tvrtko Ursulinac657f62016-05-10 10:57:08 +01002571
2572#define GEN_FOREVER (0)
2573/*
2574 * Returns true if Gen is in inclusive range [Start, End].
2575 *
2576 * Use GEN_FOREVER for unbound start and or end.
2577 */
2578#define IS_GEN(p, s, e) ({ \
2579 unsigned int __s = (s), __e = (e); \
2580 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2581 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2582 if ((__s) != GEN_FOREVER) \
2583 __s = (s) - 1; \
2584 if ((__e) == GEN_FOREVER) \
2585 __e = BITS_PER_LONG - 1; \
2586 else \
2587 __e = (e) - 1; \
2588 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2589})
2590
Jani Nikulae87a0052015-10-20 15:22:02 +03002591/*
2592 * Return true if revision is in range [since,until] inclusive.
2593 *
2594 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2595 */
2596#define IS_REVID(p, since, until) \
2597 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2598
Chris Wilson87f1f462014-08-09 19:18:42 +01002599#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2600#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002601#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002602#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002603#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002604#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2605#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002606#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2607#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2608#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002609#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002610#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002611#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2612#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002613#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2614#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002615#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002616#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002617#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2618 INTEL_DEVID(dev) == 0x0152 || \
2619 INTEL_DEVID(dev) == 0x015a)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002620#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Wayne Boyer666a4532015-12-09 12:29:35 -08002621#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002622#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Tvrtko Ursulinab0d24a2016-05-10 10:57:05 +01002623#define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302624#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Rodrigo Vivi7526ac12015-10-27 10:14:54 -07002625#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002626#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
Zou Nan haicae58522010-11-09 17:17:32 +08002627#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002628#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002629 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002630#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Rodrigo Vivi6b96d702015-01-19 16:16:15 -08002631 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
Rodrigo Vivi0dc6f202015-01-21 11:46:32 -08002632 (INTEL_DEVID(dev) & 0xf) == 0xb || \
Chris Wilson87f1f462014-08-09 19:18:42 +01002633 (INTEL_DEVID(dev) & 0xf) == 0xe))
Ville Syrjäläebb72aa2015-06-03 15:45:12 +03002634/* ULX machines are also considered ULT. */
2635#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2636 (INTEL_DEVID(dev) & 0xf) == 0xe)
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002637#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2638 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002639#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002640 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002641#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002642 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002643/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002644#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2645 INTEL_DEVID(dev) == 0x0A1E)
David Weinehallf8896f52015-06-25 11:11:03 +03002646#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2647 INTEL_DEVID(dev) == 0x1913 || \
2648 INTEL_DEVID(dev) == 0x1916 || \
2649 INTEL_DEVID(dev) == 0x1921 || \
2650 INTEL_DEVID(dev) == 0x1926)
2651#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2652 INTEL_DEVID(dev) == 0x1915 || \
2653 INTEL_DEVID(dev) == 0x191E)
Rodrigo Vivia5b79912015-12-08 16:58:37 -08002654#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2655 INTEL_DEVID(dev) == 0x5913 || \
2656 INTEL_DEVID(dev) == 0x5916 || \
2657 INTEL_DEVID(dev) == 0x5921 || \
2658 INTEL_DEVID(dev) == 0x5926)
2659#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2660 INTEL_DEVID(dev) == 0x5915 || \
2661 INTEL_DEVID(dev) == 0x591E)
Sagar Arun Kamble7a58bad2015-09-12 10:17:50 +05302662#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2663 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2664#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2665 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2666
Ben Widawskyb833d682013-08-23 16:00:07 -07002667#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002668
Jani Nikulaef712bb2015-10-20 15:22:00 +03002669#define SKL_REVID_A0 0x0
2670#define SKL_REVID_B0 0x1
2671#define SKL_REVID_C0 0x2
2672#define SKL_REVID_D0 0x3
2673#define SKL_REVID_E0 0x4
2674#define SKL_REVID_F0 0x5
Mika Kuoppala4ba9c1f2016-07-20 14:26:12 +03002675#define SKL_REVID_G0 0x6
2676#define SKL_REVID_H0 0x7
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002677
Jani Nikulae87a0052015-10-20 15:22:02 +03002678#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2679
Jani Nikulaef712bb2015-10-20 15:22:00 +03002680#define BXT_REVID_A0 0x0
Jani Nikulafffda3f2015-10-20 15:22:01 +03002681#define BXT_REVID_A1 0x1
Jani Nikulaef712bb2015-10-20 15:22:00 +03002682#define BXT_REVID_B0 0x3
2683#define BXT_REVID_C0 0x9
Nick Hoath6c74c872015-03-20 09:03:52 +00002684
Jani Nikulae87a0052015-10-20 15:22:02 +03002685#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2686
Mika Kuoppalac033a372016-06-07 17:18:55 +03002687#define KBL_REVID_A0 0x0
2688#define KBL_REVID_B0 0x1
Mika Kuoppalafe905812016-06-07 17:19:03 +03002689#define KBL_REVID_C0 0x2
2690#define KBL_REVID_D0 0x3
2691#define KBL_REVID_E0 0x4
Mika Kuoppalac033a372016-06-07 17:18:55 +03002692
2693#define IS_KBL_REVID(p, since, until) \
2694 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2695
Jesse Barnes85436692011-04-06 12:11:14 -07002696/*
2697 * The genX designation typically refers to the render engine, so render
2698 * capability related checks should use IS_GEN, while display and other checks
2699 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2700 * chips, etc.).
2701 */
Tvrtko Ursulinaf1346a2016-07-04 15:50:23 +01002702#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2703#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2704#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2705#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2706#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2707#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2708#define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2709#define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
Zou Nan haicae58522010-11-09 17:17:32 +08002710
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002711#define ENGINE_MASK(id) BIT(id)
2712#define RENDER_RING ENGINE_MASK(RCS)
2713#define BSD_RING ENGINE_MASK(VCS)
2714#define BLT_RING ENGINE_MASK(BCS)
2715#define VEBOX_RING ENGINE_MASK(VECS)
2716#define BSD2_RING ENGINE_MASK(VCS2)
2717#define ALL_ENGINES (~0)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002718
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002719#define HAS_ENGINE(dev_priv, id) \
Tvrtko Ursulinaf1346a2016-07-04 15:50:23 +01002720 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002721
2722#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2723#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2724#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2725#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2726
Ben Widawsky63c42e52014-04-18 18:04:27 -03002727#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Tvrtko Ursulinca377802016-03-02 12:10:31 +00002728#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
Tvrtko Ursulinaf1346a2016-07-04 15:50:23 +01002729#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
Ben Widawsky63c42e52014-04-18 18:04:27 -03002730#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Mika Kuoppala3accaf72016-04-13 17:26:43 +03002731 HAS_EDRAM(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08002732#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2733
Ben Widawsky254f9652012-06-04 14:42:42 -07002734#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002735#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002736#define USES_PPGTT(dev) (i915.enable_ppgtt)
Michel Thierry81ba8aef2015-08-03 09:52:01 +01002737#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2738#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002739
Chris Wilson05394f32010-11-08 19:18:58 +00002740#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002741#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2742
Daniel Vetterb45305f2012-12-17 16:21:27 +01002743/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2744#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Mika Kuoppala06e668a2015-12-16 19:18:37 +02002745
2746/* WaRsDisableCoarsePowerGating:skl,bxt */
Tvrtko Ursulin61251512016-06-21 15:07:14 +01002747#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2748 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2749 IS_SKL_GT3(dev_priv) || \
2750 IS_SKL_GT4(dev_priv))
Mika Kuoppala185c66e2016-04-05 15:56:16 +03002751
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002752/*
2753 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2754 * even when in MSI mode. This results in spurious interrupt warnings if the
2755 * legacy irq no. is shared with another device. The kernel then disables that
2756 * interrupt source and so prevents the other device from working properly.
2757 */
2758#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2759#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002760
Zou Nan haicae58522010-11-09 17:17:32 +08002761/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2762 * rows, which changed the alignment requirements and fence programming.
2763 */
2764#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2765 IS_I915GM(dev)))
Zou Nan haicae58522010-11-09 17:17:32 +08002766#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2767#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002768
2769#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2770#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002771#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002772
Damien Lespiaudbf77862014-10-01 20:04:14 +01002773#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002774
Jani Nikula0c9b3712015-05-18 17:10:01 +03002775#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2776 INTEL_INFO(dev)->gen >= 9)
2777
Damien Lespiaudd93be52013-04-22 18:40:39 +01002778#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002779#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002780#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
Sonika Jindale3d99842015-01-22 14:30:54 +05302781 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002782 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002783#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Suketu Shah00776512015-04-16 14:22:14 +05302784 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
Wayne Boyer666a4532015-12-09 12:29:35 -08002785 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
Imre Deak8f6d8552016-04-01 16:02:47 +03002786 IS_KABYLAKE(dev) || IS_BROXTON(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002787#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01002788#define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002789
Animesh Manna7b403ff2015-08-04 22:02:42 +05302790#define HAS_CSR(dev) (IS_GEN9(dev))
Daniel Vettereb805622015-05-04 14:58:44 +02002791
Dave Gordon1a3d1892016-05-13 15:36:30 +01002792/*
2793 * For now, anything with a GuC requires uCode loading, and then supports
2794 * command submission once loaded. But these are logically independent
2795 * properties, so we have separate macros to test them.
2796 */
Peter Antoine6f8be282016-06-30 09:37:51 -07002797#define HAS_GUC(dev) (IS_GEN9(dev))
Dave Gordon1a3d1892016-05-13 15:36:30 +01002798#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2799#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
Alex Dai33a732f2015-08-12 15:43:36 +01002800
Abdiel Janulguea9ed33c2015-07-01 10:12:23 +03002801#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2802 INTEL_INFO(dev)->gen >= 8)
2803
Akash Goel97d33082015-06-29 14:50:23 +05302804#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
Wayne Boyer666a4532015-12-09 12:29:35 -08002805 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2806 !IS_BROXTON(dev))
Akash Goel97d33082015-06-29 14:50:23 +05302807
arun.siluvery@linux.intel.com33e141e2016-06-03 06:34:33 +01002808#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2809
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002810#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2811#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2812#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2813#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2814#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2815#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302816#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2817#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Rodrigo Vivi22dea0b2016-07-01 17:07:12 -07002818#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
Robert Beckett30c964a2015-08-28 13:10:22 +01002819#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
Jesse Barnes1844a662016-03-16 13:31:30 -07002820#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
Gerd Hoffmann39bfcd522015-11-26 12:03:51 +01002821#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002822
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002823#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Rodrigo Vivi22dea0b2016-07-01 17:07:12 -07002824#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302825#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002826#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Ville Syrjäläc2699522015-08-27 23:55:59 +03002827#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
Ville Syrjälä56f5f702015-11-30 16:23:44 +02002828#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
Zou Nan haicae58522010-11-09 17:17:32 +08002829#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2830#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002831#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002832#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002833
Wayne Boyer666a4532015-12-09 12:29:35 -08002834#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2835 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Sonika Jindal5fafe292014-07-21 15:23:38 +05302836
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002837/* DPF == dynamic parity feature */
2838#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2839#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002840
Ben Widawskyc8735b02012-09-07 19:43:39 -07002841#define GT_FREQUENCY_MULTIPLIER 50
Akash Goelde43ae92015-03-06 11:07:14 +05302842#define GEN9_FREQ_SCALER 3
Ben Widawskyc8735b02012-09-07 19:43:39 -07002843
Chris Wilson05394f32010-11-08 19:18:58 +00002844#include "i915_trace.h"
2845
Chris Wilson48f112f2016-06-24 14:07:14 +01002846static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2847{
2848#ifdef CONFIG_INTEL_IOMMU
2849 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2850 return true;
2851#endif
2852 return false;
2853}
2854
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +02002855extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2856extern int i915_resume_switcheroo(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002857
Chris Wilsonc0336662016-05-06 15:40:21 +01002858int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2859 int enable_ppgtt);
Chris Wilson0e4ca102016-04-29 13:18:22 +01002860
Chris Wilson39df9192016-07-20 13:31:57 +01002861bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2862
Chris Wilson0673ad42016-06-24 14:00:22 +01002863/* i915_drv.c */
Imre Deakd15d7532016-03-18 10:46:10 +02002864void __printf(3, 4)
2865__i915_printk(struct drm_i915_private *dev_priv, const char *level,
2866 const char *fmt, ...);
2867
2868#define i915_report_error(dev_priv, fmt, ...) \
2869 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2870
Ben Widawskyc43b5632012-04-16 14:07:40 -07002871#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002872extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2873 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002874#endif
Chris Wilsondc979972016-05-10 14:10:04 +01002875extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2876extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
Chris Wilsonc0336662016-05-06 15:40:21 +01002877extern int i915_reset(struct drm_i915_private *dev_priv);
Arun Siluvery6b332fa2016-04-04 18:50:56 +01002878extern int intel_guc_reset(struct drm_i915_private *dev_priv);
Tomas Elffc0768c2016-03-21 16:26:59 +00002879extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002880extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2881extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2882extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2883extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002884int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002885
Jani Nikula77913b32015-06-18 13:06:16 +03002886/* intel_hotplug.c */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002887void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2888 u32 pin_mask, u32 long_mask);
Jani Nikula77913b32015-06-18 13:06:16 +03002889void intel_hpd_init(struct drm_i915_private *dev_priv);
2890void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2891void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Imre Deakcc24fcd2015-07-21 15:32:45 -07002892bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
Lyudeb236d7c82016-06-21 17:03:43 -04002893bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2894void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
Jani Nikula77913b32015-06-18 13:06:16 +03002895
Linus Torvalds1da177e2005-04-16 15:20:36 -07002896/* i915_irq.c */
Chris Wilson26a02b82016-07-01 17:23:13 +01002897static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2898{
2899 unsigned long delay;
2900
2901 if (unlikely(!i915.enable_hangcheck))
2902 return;
2903
2904 /* Don't continually defer the hangcheck so that it is always run at
2905 * least once after work has been scheduled on any ring. Otherwise,
2906 * we will ignore a hung ring if a second ring is kept busy.
2907 */
2908
2909 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2910 queue_delayed_work(system_long_wq,
2911 &dev_priv->gpu_error.hangcheck_work, delay);
2912}
2913
Mika Kuoppala58174462014-02-25 17:11:26 +02002914__printf(3, 4)
Chris Wilsonc0336662016-05-06 15:40:21 +01002915void i915_handle_error(struct drm_i915_private *dev_priv,
2916 u32 engine_mask,
Mika Kuoppala58174462014-02-25 17:11:26 +02002917 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002918
Daniel Vetterb9632912014-09-30 10:56:44 +02002919extern void intel_irq_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002920int intel_irq_install(struct drm_i915_private *dev_priv);
2921void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002922
Chris Wilsondc979972016-05-10 14:10:04 +01002923extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2924extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
Imre Deak10018602014-06-06 12:59:39 +03002925 bool restore_forcewake);
Chris Wilsondc979972016-05-10 14:10:04 +01002926extern void intel_uncore_init(struct drm_i915_private *dev_priv);
Mika Kuoppalafc976182015-12-15 16:25:07 +02002927extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
Mika Kuoppalabc3b9342016-01-08 15:51:20 +02002928extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
Chris Wilsondc979972016-05-10 14:10:04 +01002929extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2930extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2931 bool restore);
Mika Kuoppala48c10262015-01-16 11:34:41 +02002932const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002933void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002934 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002935void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002936 enum forcewake_domains domains);
Chris Wilsona6111f72015-04-07 16:21:02 +01002937/* Like above but the caller must manage the uncore.lock itself.
2938 * Must be used with I915_READ_FW and friends.
2939 */
2940void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2941 enum forcewake_domains domains);
2942void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2943 enum forcewake_domains domains);
Mika Kuoppala3accaf72016-04-13 17:26:43 +03002944u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2945
Mika Kuoppala59bad942015-01-16 11:34:40 +02002946void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
Zhi Wang0ad35fe2016-06-16 08:07:00 -04002947
Chris Wilson1758b902016-06-30 15:32:44 +01002948int intel_wait_for_register(struct drm_i915_private *dev_priv,
2949 i915_reg_t reg,
2950 const u32 mask,
2951 const u32 value,
2952 const unsigned long timeout_ms);
2953int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2954 i915_reg_t reg,
2955 const u32 mask,
2956 const u32 value,
2957 const unsigned long timeout_ms);
2958
Zhi Wang0ad35fe2016-06-16 08:07:00 -04002959static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2960{
2961 return dev_priv->gvt.initialized;
2962}
2963
Chris Wilsonc0336662016-05-06 15:40:21 +01002964static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
Yu Zhangcf9d2892015-02-10 19:05:47 +08002965{
Chris Wilsonc0336662016-05-06 15:40:21 +01002966 return dev_priv->vgpu.active;
Yu Zhangcf9d2892015-02-10 19:05:47 +08002967}
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002968
Keith Packard7c463582008-11-04 02:03:27 -08002969void
Jani Nikula50227e12014-03-31 14:27:21 +03002970i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002971 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002972
2973void
Jani Nikula50227e12014-03-31 14:27:21 +03002974i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002975 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002976
Imre Deakf8b79e52014-03-04 19:23:07 +02002977void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2978void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Egbert Eich0706f172015-09-23 16:15:27 +02002979void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2980 uint32_t mask,
2981 uint32_t bits);
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +02002982void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2983 uint32_t interrupt_mask,
2984 uint32_t enabled_irq_mask);
2985static inline void
2986ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2987{
2988 ilk_update_display_irq(dev_priv, bits, bits);
2989}
2990static inline void
2991ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2992{
2993 ilk_update_display_irq(dev_priv, bits, 0);
2994}
Ville Syrjälä013d3752015-11-23 18:06:17 +02002995void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2996 enum pipe pipe,
2997 uint32_t interrupt_mask,
2998 uint32_t enabled_irq_mask);
2999static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3000 enum pipe pipe, uint32_t bits)
3001{
3002 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3003}
3004static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3005 enum pipe pipe, uint32_t bits)
3006{
3007 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3008}
Daniel Vetter47339cd2014-09-30 10:56:46 +02003009void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3010 uint32_t interrupt_mask,
3011 uint32_t enabled_irq_mask);
Ville Syrjälä14443262015-11-23 18:06:15 +02003012static inline void
3013ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3014{
3015 ibx_display_interrupt_update(dev_priv, bits, bits);
3016}
3017static inline void
3018ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3019{
3020 ibx_display_interrupt_update(dev_priv, bits, 0);
3021}
3022
Eric Anholt673a3942008-07-30 12:06:12 -07003023/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07003024int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3025 struct drm_file *file_priv);
3026int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3027 struct drm_file *file_priv);
3028int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3029 struct drm_file *file_priv);
3030int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3031 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003032int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3033 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07003034int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3035 struct drm_file *file_priv);
3036int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3037 struct drm_file *file_priv);
3038int i915_gem_execbuffer(struct drm_device *dev, void *data,
3039 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003040int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3041 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07003042int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3043 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07003044int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3045 struct drm_file *file);
3046int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3047 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003048int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3049 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01003050int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3051 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07003052int i915_gem_set_tiling(struct drm_device *dev, void *data,
3053 struct drm_file *file_priv);
3054int i915_gem_get_tiling(struct drm_device *dev, void *data,
3055 struct drm_file *file_priv);
Chris Wilson72778cb2016-05-19 16:17:16 +01003056void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01003057int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3058 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07003059int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3060 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07003061int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3062 struct drm_file *file_priv);
Imre Deakd64aa092016-01-19 15:26:29 +02003063void i915_gem_load_init(struct drm_device *dev);
3064void i915_gem_load_cleanup(struct drm_device *dev);
Imre Deak40ae4e12016-03-16 14:54:03 +02003065void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
Chris Wilson461fb992016-05-14 07:26:33 +01003066int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3067
Chris Wilson42dcedd2012-11-15 11:32:30 +00003068void *i915_gem_object_alloc(struct drm_device *dev);
3069void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01003070void i915_gem_object_init(struct drm_i915_gem_object *obj,
3071 const struct drm_i915_gem_object_ops *ops);
Dave Gordond37cd8a2016-04-22 19:14:32 +01003072struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00003073 size_t size);
Dave Gordonea702992015-07-09 19:29:02 +01003074struct drm_i915_gem_object *i915_gem_object_create_from_data(
3075 struct drm_device *dev, const void *data, size_t size);
Chris Wilsonb1f788c2016-08-04 07:52:45 +01003076void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003077void i915_gem_free_object(struct drm_gem_object *obj);
Chris Wilson42dcedd2012-11-15 11:32:30 +00003078
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003079int __must_check
3080i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3081 const struct i915_ggtt_view *view,
Chris Wilson91b2db62016-08-04 16:32:23 +01003082 u64 size,
Chris Wilson2ffffd02016-08-04 16:32:22 +01003083 u64 alignment,
3084 u64 flags);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003085
3086int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3087 u32 flags);
Chris Wilsond0710ab2015-11-20 14:16:39 +00003088void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003089int __must_check i915_vma_unbind(struct i915_vma *vma);
Chris Wilsonb1f788c2016-08-04 07:52:45 +01003090void i915_vma_close(struct i915_vma *vma);
3091void i915_vma_destroy(struct i915_vma *vma);
Chris Wilsonaa653a62016-08-04 07:52:27 +01003092
3093int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
Chris Wilsondd624af2013-01-15 12:39:35 +00003094int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02003095void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00003096void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01003097
Brad Volkin4c914c02014-02-18 10:15:45 -08003098int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3099 int *needs_clflush);
3100
Chris Wilson37e680a2012-06-07 15:38:42 +01003101int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilsonee286372015-04-07 16:20:25 +01003102
3103static inline int __sg_page_count(struct scatterlist *sg)
Chris Wilson9da3da62012-06-01 15:20:22 +01003104{
Chris Wilsonee286372015-04-07 16:20:25 +01003105 return sg->length >> PAGE_SHIFT;
Chris Wilson9da3da62012-06-01 15:20:22 +01003106}
Chris Wilsonee286372015-04-07 16:20:25 +01003107
Dave Gordon033908a2015-12-10 18:51:23 +00003108struct page *
3109i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3110
Chris Wilson341be1c2016-06-10 14:23:00 +05303111static inline dma_addr_t
3112i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3113{
3114 if (n < obj->get_page.last) {
3115 obj->get_page.sg = obj->pages->sgl;
3116 obj->get_page.last = 0;
3117 }
3118
3119 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3120 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3121 if (unlikely(sg_is_chain(obj->get_page.sg)))
3122 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3123 }
3124
3125 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3126}
3127
Chris Wilsonee286372015-04-07 16:20:25 +01003128static inline struct page *
3129i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3130{
3131 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3132 return NULL;
3133
3134 if (n < obj->get_page.last) {
3135 obj->get_page.sg = obj->pages->sgl;
3136 obj->get_page.last = 0;
3137 }
3138
3139 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3140 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3141 if (unlikely(sg_is_chain(obj->get_page.sg)))
3142 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3143 }
3144
3145 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3146}
3147
Chris Wilsona5570172012-09-04 21:02:54 +01003148static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3149{
3150 BUG_ON(obj->pages == NULL);
3151 obj->pages_pin_count++;
3152}
Chris Wilson0a798eb2016-04-08 12:11:11 +01003153
Chris Wilsona5570172012-09-04 21:02:54 +01003154static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3155{
3156 BUG_ON(obj->pages_pin_count == 0);
3157 obj->pages_pin_count--;
3158}
3159
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003160enum i915_map_type {
3161 I915_MAP_WB = 0,
3162 I915_MAP_WC,
3163};
3164
Chris Wilson0a798eb2016-04-08 12:11:11 +01003165/**
3166 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3167 * @obj - the object to map into kernel address space
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003168 * @type - the type of mapping, used to select pgprot_t
Chris Wilson0a798eb2016-04-08 12:11:11 +01003169 *
3170 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3171 * pages and then returns a contiguous mapping of the backing storage into
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003172 * the kernel address space. Based on the @type of mapping, the PTE will be
3173 * set to either WriteBack or WriteCombine (via pgprot_t).
Chris Wilson0a798eb2016-04-08 12:11:11 +01003174 *
Dave Gordon83052162016-04-12 14:46:16 +01003175 * The caller must hold the struct_mutex, and is responsible for calling
3176 * i915_gem_object_unpin_map() when the mapping is no longer required.
Chris Wilson0a798eb2016-04-08 12:11:11 +01003177 *
Dave Gordon83052162016-04-12 14:46:16 +01003178 * Returns the pointer through which to access the mapped object, or an
3179 * ERR_PTR() on error.
Chris Wilson0a798eb2016-04-08 12:11:11 +01003180 */
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003181void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3182 enum i915_map_type type);
Chris Wilson0a798eb2016-04-08 12:11:11 +01003183
3184/**
3185 * i915_gem_object_unpin_map - releases an earlier mapping
3186 * @obj - the object to unmap
3187 *
3188 * After pinning the object and mapping its pages, once you are finished
3189 * with your access, call i915_gem_object_unpin_map() to release the pin
3190 * upon the mapping. Once the pin count reaches zero, that mapping may be
3191 * removed.
3192 *
3193 * The caller must hold the struct_mutex.
3194 */
3195static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3196{
3197 lockdep_assert_held(&obj->base.dev->struct_mutex);
3198 i915_gem_object_unpin_pages(obj);
3199}
3200
Chris Wilson54cf91d2010-11-25 18:00:26 +00003201int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07003202int i915_gem_object_sync(struct drm_i915_gem_object *obj,
Chris Wilson8e637172016-08-02 22:50:26 +01003203 struct drm_i915_gem_request *to);
Ben Widawskye2d05a82013-09-24 09:57:58 -07003204void i915_vma_move_to_active(struct i915_vma *vma,
Chris Wilson5cf3d282016-08-04 07:52:43 +01003205 struct drm_i915_gem_request *req,
3206 unsigned int flags);
Dave Airlieff72145b2011-02-07 12:16:14 +10003207int i915_gem_dumb_create(struct drm_file *file_priv,
3208 struct drm_device *dev,
3209 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10003210int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3211 uint32_t handle, uint64_t *offset);
Dave Gordon85d12252016-05-20 11:54:06 +01003212
3213void i915_gem_track_fb(struct drm_i915_gem_object *old,
3214 struct drm_i915_gem_object *new,
3215 unsigned frontbuffer_bits);
3216
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02003217int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003218
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02003219struct drm_i915_gem_request *
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00003220i915_gem_find_active_request(struct intel_engine_cs *engine);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02003221
Chris Wilson67d97da2016-07-04 08:08:31 +01003222void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
Sourab Gupta84c33a62014-06-02 16:47:17 +05303223
Chris Wilsonc19ae982016-04-13 17:35:03 +01003224static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3225{
3226 return atomic_read(&error->reset_counter);
3227}
3228
3229static inline bool __i915_reset_in_progress(u32 reset)
3230{
3231 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3232}
3233
3234static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3235{
3236 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3237}
3238
3239static inline bool __i915_terminally_wedged(u32 reset)
3240{
3241 return unlikely(reset & I915_WEDGED);
3242}
3243
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003244static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3245{
Chris Wilsonc19ae982016-04-13 17:35:03 +01003246 return __i915_reset_in_progress(i915_reset_counter(error));
3247}
3248
3249static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3250{
3251 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003252}
3253
3254static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3255{
Chris Wilsonc19ae982016-04-13 17:35:03 +01003256 return __i915_terminally_wedged(i915_reset_counter(error));
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02003257}
3258
3259static inline u32 i915_reset_count(struct i915_gpu_error *error)
3260{
Chris Wilsonc19ae982016-04-13 17:35:03 +01003261 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003262}
Chris Wilsona71d8d92012-02-15 11:25:36 +00003263
Chris Wilson069efc12010-09-30 16:53:18 +01003264void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01003265bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilson1070a422012-04-24 15:47:41 +01003266int __must_check i915_gem_init(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003267int __must_check i915_gem_init_hw(struct drm_device *dev);
3268void i915_gem_init_swizzling(struct drm_device *dev);
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00003269void i915_gem_cleanup_engines(struct drm_device *dev);
Chris Wilsondcff85c2016-08-05 10:14:11 +01003270int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3271 bool interruptible);
Chris Wilson45c5f202013-10-16 11:50:01 +01003272int __must_check i915_gem_suspend(struct drm_device *dev);
Chris Wilson5ab57c72016-07-15 14:56:20 +01003273void i915_gem_resume(struct drm_device *dev);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003274int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00003275int __must_check
Chris Wilson2e2f3512015-04-27 13:41:14 +01003276i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3277 bool readonly);
3278int __must_check
Chris Wilson20217462010-11-23 15:26:33 +00003279i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3280 bool write);
3281int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02003282i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3283int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003284i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3285 u32 alignment,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003286 const struct i915_ggtt_view *view);
3287void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3288 const struct i915_ggtt_view *view);
Chris Wilson00731152014-05-21 12:42:56 +01003289int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01003290 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01003291int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00003292void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003293
Chris Wilsona9f14812016-08-04 16:32:28 +01003294u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3295 int tiling_mode);
3296u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
Chris Wilsonad1a7d22016-08-04 16:32:27 +01003297 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00003298
Chris Wilsone4ffd172011-04-04 09:44:39 +01003299int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3300 enum i915_cache_level cache_level);
3301
Daniel Vetter1286ff72012-05-10 15:25:09 +02003302struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3303 struct dma_buf *dma_buf);
3304
3305struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3306 struct drm_gem_object *gem_obj, int flags);
3307
Michel Thierry088e0df2015-08-07 17:40:17 +01003308u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3309 const struct i915_ggtt_view *view);
3310u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3311 struct i915_address_space *vm);
3312static inline u64
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003313i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003314{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003315 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003316}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003317
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003318bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003319 const struct i915_ggtt_view *view);
Ben Widawskya70a3142013-07-31 16:59:56 -07003320bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003321 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003322
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003323struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003324i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3325 struct i915_address_space *vm);
3326struct i915_vma *
3327i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3328 const struct i915_ggtt_view *view);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003329
Ben Widawskyaccfef22013-08-14 11:38:35 +02003330struct i915_vma *
3331i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003332 struct i915_address_space *vm);
3333struct i915_vma *
3334i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3335 const struct i915_ggtt_view *view);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003336
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003337static inline struct i915_vma *
3338i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3339{
3340 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003341}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003342bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003343
Ben Widawskya70a3142013-07-31 16:59:56 -07003344/* Some GGTT VM helpers */
Daniel Vetter841cd772014-08-06 15:04:48 +02003345static inline struct i915_hw_ppgtt *
3346i915_vm_to_ppgtt(struct i915_address_space *vm)
3347{
Daniel Vetter841cd772014-08-06 15:04:48 +02003348 return container_of(vm, struct i915_hw_ppgtt, base);
3349}
3350
Ben Widawskya70a3142013-07-31 16:59:56 -07003351static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3352{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003353 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
Ben Widawskya70a3142013-07-31 16:59:56 -07003354}
3355
Tvrtko Ursulin8da32722016-04-21 13:04:43 +01003356unsigned long
3357i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
Ben Widawskyc37e2202013-07-31 16:59:58 -07003358
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003359void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3360 const struct i915_ggtt_view *view);
3361static inline void
3362i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3363{
3364 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3365}
Daniel Vetterb2871102014-02-14 14:01:19 +01003366
Daniel Vetter41a36b72015-07-24 13:55:11 +02003367/* i915_gem_fence.c */
3368int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3369int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3370
3371bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3372void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3373
3374void i915_gem_restore_fences(struct drm_device *dev);
3375
Daniel Vetter7f96eca2015-07-24 17:40:14 +02003376void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3377void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3378void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3379
Ben Widawsky254f9652012-06-04 14:42:42 -07003380/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02003381int __must_check i915_gem_context_init(struct drm_device *dev);
Chris Wilsonb2e862d2016-04-28 09:56:41 +01003382void i915_gem_context_lost(struct drm_i915_private *dev_priv);
Ben Widawsky254f9652012-06-04 14:42:42 -07003383void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08003384void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08003385int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
Ben Widawsky254f9652012-06-04 14:42:42 -07003386void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
John Harrisonba01cc92015-05-29 17:43:41 +01003387int i915_switch_context(struct drm_i915_gem_request *req);
Chris Wilson945657b2016-07-15 14:56:19 +01003388int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003389void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01003390struct drm_i915_gem_object *
3391i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Zhi Wangc8c35792016-06-16 08:07:05 -04003392struct i915_gem_context *
3393i915_gem_context_create_gvt(struct drm_device *dev);
Chris Wilsonca585b52016-05-24 14:53:36 +01003394
3395static inline struct i915_gem_context *
3396i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3397{
3398 struct i915_gem_context *ctx;
3399
Chris Wilson091387c2016-06-24 14:00:21 +01003400 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
Chris Wilsonca585b52016-05-24 14:53:36 +01003401
3402 ctx = idr_find(&file_priv->context_idr, id);
3403 if (!ctx)
3404 return ERR_PTR(-ENOENT);
3405
3406 return ctx;
3407}
3408
Chris Wilson9a6feaf2016-07-20 13:31:50 +01003409static inline struct i915_gem_context *
3410i915_gem_context_get(struct i915_gem_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003411{
Chris Wilson691e6412014-04-09 09:07:36 +01003412 kref_get(&ctx->ref);
Chris Wilson9a6feaf2016-07-20 13:31:50 +01003413 return ctx;
Mika Kuoppaladce32712013-04-30 13:30:33 +03003414}
3415
Chris Wilson9a6feaf2016-07-20 13:31:50 +01003416static inline void i915_gem_context_put(struct i915_gem_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003417{
Chris Wilson091387c2016-06-24 14:00:21 +01003418 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
Chris Wilson691e6412014-04-09 09:07:36 +01003419 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003420}
3421
Chris Wilsone2efd132016-05-24 14:53:34 +01003422static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003423{
Oscar Mateo821d66d2014-07-03 16:28:00 +01003424 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003425}
3426
Ben Widawsky84624812012-06-04 14:42:54 -07003427int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3428 struct drm_file *file);
3429int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3430 struct drm_file *file);
Chris Wilsonc9dc0f32014-12-24 08:13:40 -08003431int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3432 struct drm_file *file_priv);
3433int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3434 struct drm_file *file_priv);
Chris Wilsond5387042016-05-13 11:57:19 +01003435int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3436 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02003437
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003438/* i915_gem_evict.c */
Chris Wilsone522ac22016-08-04 16:32:18 +01003439int __must_check i915_gem_evict_something(struct i915_address_space *vm,
Chris Wilson2ffffd02016-08-04 16:32:22 +01003440 u64 min_size, u64 alignment,
Chris Wilson42d6ab42012-07-26 11:49:32 +01003441 unsigned cache_level,
Chris Wilson2ffffd02016-08-04 16:32:22 +01003442 u64 start, u64 end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003443 unsigned flags);
Chris Wilson506a8e82015-12-08 11:55:07 +00003444int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
Ben Widawsky68c8c172013-09-11 14:57:50 -07003445int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003446
Ben Widawsky0260c422014-03-22 22:47:21 -07003447/* belongs in i915_gem_gtt.h */
Chris Wilsonc0336662016-05-06 15:40:21 +01003448static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
Eric Anholt673a3942008-07-30 12:06:12 -07003449{
Chris Wilsonc0336662016-05-06 15:40:21 +01003450 if (INTEL_GEN(dev_priv) < 6)
Eric Anholt673a3942008-07-30 12:06:12 -07003451 intel_gtt_chipset_flush();
3452}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08003453
Chris Wilson9797fbf2012-04-24 15:47:39 +01003454/* i915_gem_stolen.c */
Paulo Zanonid713fd42015-07-02 19:25:07 -03003455int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3456 struct drm_mm_node *node, u64 size,
3457 unsigned alignment);
Paulo Zanonia9da5122015-09-14 15:19:57 -03003458int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3459 struct drm_mm_node *node, u64 size,
3460 unsigned alignment, u64 start,
3461 u64 end);
Paulo Zanonid713fd42015-07-02 19:25:07 -03003462void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3463 struct drm_mm_node *node);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003464int i915_gem_init_stolen(struct drm_device *dev);
3465void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00003466struct drm_i915_gem_object *
3467i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08003468struct drm_i915_gem_object *
3469i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3470 u32 stolen_offset,
3471 u32 gtt_offset,
3472 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003473
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003474/* i915_gem_shrinker.c */
3475unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
Chris Wilson14387542015-10-01 12:18:25 +01003476 unsigned long target,
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003477 unsigned flags);
3478#define I915_SHRINK_PURGEABLE 0x1
3479#define I915_SHRINK_UNBOUND 0x2
3480#define I915_SHRINK_BOUND 0x4
Chris Wilson5763ff02015-10-01 12:18:29 +01003481#define I915_SHRINK_ACTIVE 0x8
Chris Wilsoneae2c432016-04-08 12:11:12 +01003482#define I915_SHRINK_VMAPS 0x10
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003483unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3484void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
Imre Deaka8a40582016-01-19 15:26:28 +02003485void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003486
3487
Eric Anholt673a3942008-07-30 12:06:12 -07003488/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01003489static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00003490{
Chris Wilson091387c2016-06-24 14:00:21 +01003491 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
Chris Wilsone9b73c62012-12-03 21:03:14 +00003492
3493 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
Chris Wilson3e510a82016-08-05 10:14:23 +01003494 i915_gem_object_is_tiled(obj);
Chris Wilsone9b73c62012-12-03 21:03:14 +00003495}
3496
Ben Gamari20172632009-02-17 20:08:50 -05003497/* i915_debugfs.c */
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003498#ifdef CONFIG_DEBUG_FS
Chris Wilson1dac8912016-06-24 14:00:17 +01003499int i915_debugfs_register(struct drm_i915_private *dev_priv);
3500void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
Jani Nikula249e87d2015-04-10 16:59:32 +03003501int i915_debugfs_connector_add(struct drm_connector *connector);
Damien Lespiau07144422013-10-15 18:55:40 +01003502void intel_display_crc_init(struct drm_device *dev);
3503#else
Chris Wilson8d35acb2016-07-12 12:55:29 +01003504static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3505static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
Daniel Vetter101057f2015-07-13 09:23:19 +02003506static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3507{ return 0; }
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003508static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01003509#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03003510
3511/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003512__printf(2, 3)
3513void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03003514int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3515 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003516int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003517 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003518 size_t count, loff_t pos);
3519static inline void i915_error_state_buf_release(
3520 struct drm_i915_error_state_buf *eb)
3521{
3522 kfree(eb->buf);
3523}
Chris Wilsonc0336662016-05-06 15:40:21 +01003524void i915_capture_error_state(struct drm_i915_private *dev_priv,
3525 u32 engine_mask,
Mika Kuoppala58174462014-02-25 17:11:26 +02003526 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003527void i915_error_state_get(struct drm_device *dev,
3528 struct i915_error_state_file_priv *error_priv);
3529void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3530void i915_destroy_error_state(struct drm_device *dev);
3531
Chris Wilsonc0336662016-05-06 15:40:21 +01003532void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003533const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003534
Brad Volkin351e3db2014-02-18 10:15:46 -08003535/* i915_cmd_parser.c */
Chris Wilson1ca37122016-05-04 14:25:36 +01003536int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
Chris Wilson33a051a2016-07-27 09:07:26 +01003537int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3538void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3539bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3540int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3541 struct drm_i915_gem_object *batch_obj,
3542 struct drm_i915_gem_object *shadow_batch_obj,
3543 u32 batch_start_offset,
3544 u32 batch_len,
3545 bool is_master);
Brad Volkin351e3db2014-02-18 10:15:46 -08003546
Jesse Barnes317c35d2008-08-25 15:11:06 -07003547/* i915_suspend.c */
3548extern int i915_save_state(struct drm_device *dev);
3549extern int i915_restore_state(struct drm_device *dev);
3550
Ben Widawsky0136db52012-04-10 21:17:01 -07003551/* i915_sysfs.c */
3552void i915_setup_sysfs(struct drm_device *dev_priv);
3553void i915_teardown_sysfs(struct drm_device *dev_priv);
3554
Chris Wilsonf899fc62010-07-20 15:44:45 -07003555/* intel_i2c.c */
3556extern int intel_setup_gmbus(struct drm_device *dev);
3557extern void intel_teardown_gmbus(struct drm_device *dev);
Jani Nikula88ac7932015-03-27 00:20:22 +02003558extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3559 unsigned int pin);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003560
Jani Nikula0184df42015-03-27 00:20:20 +02003561extern struct i2c_adapter *
3562intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
Chris Wilsone957d772010-09-24 12:52:03 +01003563extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3564extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003565static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003566{
3567 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3568}
Chris Wilsonf899fc62010-07-20 15:44:45 -07003569extern void intel_i2c_reset(struct drm_device *dev);
3570
Jani Nikula8b8e1a82015-12-14 12:50:49 +02003571/* intel_bios.c */
Jani Nikula98f3a1d2015-12-16 15:04:20 +02003572int intel_bios_init(struct drm_i915_private *dev_priv);
Jani Nikulaf0067a32015-12-15 13:16:15 +02003573bool intel_bios_is_valid_vbt(const void *buf, size_t size);
Jani Nikula3bdd14d2016-03-16 12:43:29 +02003574bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
Jani Nikula5a69d132016-03-16 12:43:30 +02003575bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
Ville Syrjälä22f350422016-06-03 12:17:43 +03003576bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
Jani Nikula951d9ef2016-03-16 12:43:31 +02003577bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
Ville Syrjäläd6199252016-05-04 14:45:22 +03003578bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
Jani Nikula7137aec2016-03-16 12:43:32 +02003579bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05303580bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3581 enum port port);
Jani Nikula8b8e1a82015-12-14 12:50:49 +02003582
Chris Wilson3b617962010-08-24 09:02:58 +01003583/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003584#ifdef CONFIG_ACPI
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003585extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
Chris Wilson03d92e42016-05-23 15:08:10 +01003586extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3587extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003588extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003589extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3590 bool enable);
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003591extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003592 pci_power_t state);
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003593extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
Len Brown65e082c2008-10-24 17:18:10 -04003594#else
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003595static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
Randy Dunlapbdaa2df2016-06-27 14:53:19 +03003596static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3597static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003598static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3599{
3600}
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003601static inline int
3602intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3603{
3604 return 0;
3605}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003606static inline int
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003607intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003608{
3609 return 0;
3610}
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003611static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
Ville Syrjäläa0562812016-04-11 10:23:51 +03003612{
3613 return -ENODEV;
3614}
Len Brown65e082c2008-10-24 17:18:10 -04003615#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003616
Jesse Barnes723bfd72010-10-07 16:01:13 -07003617/* intel_acpi.c */
3618#ifdef CONFIG_ACPI
3619extern void intel_register_dsm_handler(void);
3620extern void intel_unregister_dsm_handler(void);
3621#else
3622static inline void intel_register_dsm_handler(void) { return; }
3623static inline void intel_unregister_dsm_handler(void) { return; }
3624#endif /* CONFIG_ACPI */
3625
Chris Wilson94b4f3b2016-07-05 10:40:20 +01003626/* intel_device_info.c */
3627static inline struct intel_device_info *
3628mkwrite_device_info(struct drm_i915_private *dev_priv)
3629{
3630 return (struct intel_device_info *)&dev_priv->info;
3631}
3632
3633void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3634void intel_device_info_dump(struct drm_i915_private *dev_priv);
3635
Jesse Barnes79e53942008-11-07 14:24:08 -08003636/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003637extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003638extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01003639extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003640extern void intel_modeset_cleanup(struct drm_device *dev);
Chris Wilson1ebaa0b2016-06-24 14:00:15 +01003641extern int intel_connector_register(struct drm_connector *);
Chris Wilsonc191eca2016-06-17 11:40:33 +01003642extern void intel_connector_unregister(struct drm_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10003643extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +02003644extern void intel_display_resume(struct drm_device *dev);
Daniel Vetter44cec742013-01-25 17:53:21 +01003645extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02003646extern void i915_redisable_vga_power_on(struct drm_device *dev);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003647extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02003648extern void intel_init_pch_refclk(struct drm_device *dev);
Chris Wilsondc979972016-05-10 14:10:04 +01003649extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03003650extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3651 bool enable);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003652
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003653int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3654 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003655
Chris Wilson6ef3d422010-08-04 20:26:07 +01003656/* overlay */
Chris Wilsonc0336662016-05-06 15:40:21 +01003657extern struct intel_overlay_error_state *
3658intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003659extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3660 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003661
Chris Wilsonc0336662016-05-06 15:40:21 +01003662extern struct intel_display_error_state *
3663intel_display_capture_error_state(struct drm_i915_private *dev_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003664extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003665 struct drm_device *dev,
3666 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003667
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003668int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3669int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003670
3671/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303672u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3673void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003674u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Deepak Mdfb19ed2016-02-04 18:55:15 +02003675u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3676void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003677u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3678void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3679u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3680void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003681u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3682void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003683u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3684void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003685u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3686 enum intel_sbi_destination destination);
3687void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3688 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303689u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3690void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003691
Ander Conselvan de Oliveirab7fa22d2016-04-27 15:44:17 +03003692/* intel_dpio_phy.c */
3693void chv_set_phy_signal_level(struct intel_encoder *encoder,
3694 u32 deemph_reg_value, u32 margin_reg_value,
3695 bool uniq_trans_scale);
Ander Conselvan de Oliveira844b2f92016-04-27 15:44:18 +03003696void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3697 bool reset);
Ander Conselvan de Oliveira419b1b72016-04-27 15:44:19 +03003698void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
Ander Conselvan de Oliveirae7d2a7172016-04-27 15:44:20 +03003699void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3700void chv_phy_release_cl2_override(struct intel_encoder *encoder);
Ander Conselvan de Oliveira204970b2016-04-27 15:44:21 +03003701void chv_phy_post_pll_disable(struct intel_encoder *encoder);
Ander Conselvan de Oliveirab7fa22d2016-04-27 15:44:17 +03003702
Ander Conselvan de Oliveira53d98722016-04-27 15:44:22 +03003703void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3704 u32 demph_reg_value, u32 preemph_reg_value,
3705 u32 uniqtranscale_reg_value, u32 tx3_demph);
Ander Conselvan de Oliveira6da2e612016-04-27 15:44:23 +03003706void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
Ander Conselvan de Oliveira5f68c272016-04-27 15:44:24 +03003707void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
Ander Conselvan de Oliveira0f572eb2016-04-27 15:44:25 +03003708void vlv_phy_reset_lanes(struct intel_encoder *encoder);
Ander Conselvan de Oliveira53d98722016-04-27 15:44:22 +03003709
Ville Syrjälä616bc822015-01-23 21:04:25 +02003710int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3711int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
Deepak Sc8d9a592013-11-23 14:55:42 +05303712
Ben Widawsky0b274482013-10-04 21:22:51 -07003713#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3714#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003715
Ben Widawsky0b274482013-10-04 21:22:51 -07003716#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3717#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3718#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3719#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003720
Ben Widawsky0b274482013-10-04 21:22:51 -07003721#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3722#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3723#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3724#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003725
Chris Wilson698b3132014-03-21 13:16:43 +00003726/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3727 * will be implemented using 2 32-bit writes in an arbitrary order with
3728 * an arbitrary delay between them. This can cause the hardware to
3729 * act upon the intermediate value, possibly leading to corruption and
3730 * machine death. You have been warned.
3731 */
Ben Widawsky0b274482013-10-04 21:22:51 -07003732#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3733#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08003734
Chris Wilson50877442014-03-21 12:41:53 +00003735#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003736 u32 upper, lower, old_upper, loop = 0; \
3737 upper = I915_READ(upper_reg); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003738 do { \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003739 old_upper = upper; \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003740 lower = I915_READ(lower_reg); \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003741 upper = I915_READ(upper_reg); \
3742 } while (upper != old_upper && loop++ < 2); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003743 (u64)upper << 32 | lower; })
Chris Wilson50877442014-03-21 12:41:53 +00003744
Zou Nan haicae58522010-11-09 17:17:32 +08003745#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3746#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3747
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003748#define __raw_read(x, s) \
3749static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003750 i915_reg_t reg) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003751{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003752 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003753}
3754
3755#define __raw_write(x, s) \
3756static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003757 i915_reg_t reg, uint##x##_t val) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003758{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003759 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003760}
3761__raw_read(8, b)
3762__raw_read(16, w)
3763__raw_read(32, l)
3764__raw_read(64, q)
3765
3766__raw_write(8, b)
3767__raw_write(16, w)
3768__raw_write(32, l)
3769__raw_write(64, q)
3770
3771#undef __raw_read
3772#undef __raw_write
3773
Chris Wilsona6111f72015-04-07 16:21:02 +01003774/* These are untraced mmio-accessors that are only valid to be used inside
3775 * criticial sections inside IRQ handlers where forcewake is explicitly
3776 * controlled.
3777 * Think twice, and think again, before using these.
3778 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3779 * intel_uncore_forcewake_irqunlock().
3780 */
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003781#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3782#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
Chris Wilson76f84212016-06-30 15:33:45 +01003783#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
Chris Wilsona6111f72015-04-07 16:21:02 +01003784#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3785
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003786/* "Broadcast RGB" property */
3787#define INTEL_BROADCAST_RGB_AUTO 0
3788#define INTEL_BROADCAST_RGB_FULL 1
3789#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003790
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003791static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003792{
Wayne Boyer666a4532015-12-09 12:29:35 -08003793 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003794 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303795 else if (INTEL_INFO(dev)->gen >= 5)
3796 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003797 else
3798 return VGACNTRL;
3799}
3800
Imre Deakdf977292013-05-21 20:03:17 +03003801static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3802{
3803 unsigned long j = msecs_to_jiffies(m);
3804
3805 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3806}
3807
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003808static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3809{
3810 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3811}
3812
Imre Deakdf977292013-05-21 20:03:17 +03003813static inline unsigned long
3814timespec_to_jiffies_timeout(const struct timespec *value)
3815{
3816 unsigned long j = timespec_to_jiffies(value);
3817
3818 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3819}
3820
Paulo Zanonidce56b32013-12-19 14:29:40 -02003821/*
3822 * If you need to wait X milliseconds between events A and B, but event B
3823 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3824 * when event A happened, then just before event B you call this function and
3825 * pass the timestamp as the first argument, and X as the second argument.
3826 */
3827static inline void
3828wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3829{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003830 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003831
3832 /*
3833 * Don't re-read the value of "jiffies" every time since it may change
3834 * behind our back and break the math.
3835 */
3836 tmp_jiffies = jiffies;
3837 target_jiffies = timestamp_jiffies +
3838 msecs_to_jiffies_timeout(to_wait_ms);
3839
3840 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003841 remaining_jiffies = target_jiffies - tmp_jiffies;
3842 while (remaining_jiffies)
3843 remaining_jiffies =
3844 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003845 }
3846}
Chris Wilson688e6c72016-07-01 17:23:15 +01003847static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
3848{
Chris Wilsonf69a02c2016-07-01 17:23:16 +01003849 struct intel_engine_cs *engine = req->engine;
3850
Chris Wilson7ec2c732016-07-01 17:23:22 +01003851 /* Before we do the heavier coherent read of the seqno,
3852 * check the value (hopefully) in the CPU cacheline.
3853 */
3854 if (i915_gem_request_completed(req))
3855 return true;
3856
Chris Wilson688e6c72016-07-01 17:23:15 +01003857 /* Ensure our read of the seqno is coherent so that we
3858 * do not "miss an interrupt" (i.e. if this is the last
3859 * request and the seqno write from the GPU is not visible
3860 * by the time the interrupt fires, we will see that the
3861 * request is incomplete and go back to sleep awaiting
3862 * another interrupt that will never come.)
3863 *
3864 * Strictly, we only need to do this once after an interrupt,
3865 * but it is easier and safer to do it every time the waiter
3866 * is woken.
3867 */
Chris Wilson3d5564e2016-07-01 17:23:23 +01003868 if (engine->irq_seqno_barrier &&
Chris Wilsondbd6ef22016-08-09 17:47:52 +01003869 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
Chris Wilsonaca34b62016-07-06 12:39:02 +01003870 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
Chris Wilson99fe4a52016-07-06 12:39:01 +01003871 struct task_struct *tsk;
3872
Chris Wilson3d5564e2016-07-01 17:23:23 +01003873 /* The ordering of irq_posted versus applying the barrier
3874 * is crucial. The clearing of the current irq_posted must
3875 * be visible before we perform the barrier operation,
3876 * such that if a subsequent interrupt arrives, irq_posted
3877 * is reasserted and our task rewoken (which causes us to
3878 * do another __i915_request_irq_complete() immediately
3879 * and reapply the barrier). Conversely, if the clear
3880 * occurs after the barrier, then an interrupt that arrived
3881 * whilst we waited on the barrier would not trigger a
3882 * barrier on the next pass, and the read may not see the
3883 * seqno update.
3884 */
Chris Wilsonf69a02c2016-07-01 17:23:16 +01003885 engine->irq_seqno_barrier(engine);
Chris Wilson99fe4a52016-07-06 12:39:01 +01003886
3887 /* If we consume the irq, but we are no longer the bottom-half,
3888 * the real bottom-half may not have serialised their own
3889 * seqno check with the irq-barrier (i.e. may have inspected
3890 * the seqno before we believe it coherent since they see
3891 * irq_posted == false but we are still running).
3892 */
3893 rcu_read_lock();
Chris Wilsondbd6ef22016-08-09 17:47:52 +01003894 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
Chris Wilson99fe4a52016-07-06 12:39:01 +01003895 if (tsk && tsk != current)
3896 /* Note that if the bottom-half is changed as we
3897 * are sending the wake-up, the new bottom-half will
3898 * be woken by whomever made the change. We only have
3899 * to worry about when we steal the irq-posted for
3900 * ourself.
3901 */
3902 wake_up_process(tsk);
3903 rcu_read_unlock();
3904
Chris Wilson7ec2c732016-07-01 17:23:22 +01003905 if (i915_gem_request_completed(req))
3906 return true;
3907 }
Chris Wilson688e6c72016-07-01 17:23:15 +01003908
3909 /* We need to check whether any gpu reset happened in between
3910 * the request being submitted and now. If a reset has occurred,
3911 * the seqno will have been advance past ours and our request
3912 * is complete. If we are in the process of handling a reset,
3913 * the request is effectively complete as the rendering will
3914 * be discarded, but we need to return in order to drop the
3915 * struct_mutex.
3916 */
3917 if (i915_reset_in_progress(&req->i915->gpu_error))
3918 return true;
3919
3920 return false;
3921}
3922
Chris Wilson0b1de5d2016-08-12 12:39:59 +01003923void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3924bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3925
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003926#define ptr_unpack_bits(ptr, bits) ({ \
3927 unsigned long __v = (unsigned long)(ptr); \
3928 (bits) = __v & ~PAGE_MASK; \
3929 (typeof(ptr))(__v & PAGE_MASK); \
3930})
3931
3932#define ptr_pack_bits(ptr, bits) \
3933 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3934
Chris Wilson78ef2d92016-08-15 10:48:49 +01003935#define fetch_and_zero(ptr) ({ \
3936 typeof(*ptr) __T = *(ptr); \
3937 *(ptr) = (typeof(*ptr))0; \
3938 __T; \
3939})
3940
Linus Torvalds1da177e2005-04-16 15:20:36 -07003941#endif