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Michael Ellermand800ba12015-02-17 20:01:53 +11001/*
Michael Ellermand7cf83f2015-02-17 20:01:54 +11002 * OPAL API definitions.
Michael Ellermand800ba12015-02-17 20:01:53 +11003 *
Michael Ellermand7cf83f2015-02-17 20:01:54 +11004 * Copyright 2011-2015 IBM Corp.
Michael Ellermand800ba12015-02-17 20:01:53 +11005 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __OPAL_API_H
13#define __OPAL_API_H
14
15/****** OPAL APIs ******/
16
17/* Return codes */
Michael Ellermand7cf83f2015-02-17 20:01:54 +110018#define OPAL_SUCCESS 0
Michael Ellermand800ba12015-02-17 20:01:53 +110019#define OPAL_PARAMETER -1
20#define OPAL_BUSY -2
21#define OPAL_PARTIAL -3
22#define OPAL_CONSTRAINED -4
23#define OPAL_CLOSED -5
24#define OPAL_HARDWARE -6
25#define OPAL_UNSUPPORTED -7
26#define OPAL_PERMISSION -8
27#define OPAL_NO_MEM -9
28#define OPAL_RESOURCE -10
29#define OPAL_INTERNAL_ERROR -11
30#define OPAL_BUSY_EVENT -12
31#define OPAL_HARDWARE_FROZEN -13
32#define OPAL_WRONG_STATE -14
33#define OPAL_ASYNC_COMPLETION -15
Michael Ellermand7cf83f2015-02-17 20:01:54 +110034#define OPAL_EMPTY -16
Michael Ellermand800ba12015-02-17 20:01:53 +110035#define OPAL_I2C_TIMEOUT -17
36#define OPAL_I2C_INVALID_CMD -18
37#define OPAL_I2C_LBUS_PARITY -19
38#define OPAL_I2C_BKEND_OVERRUN -20
39#define OPAL_I2C_BKEND_ACCESS -21
40#define OPAL_I2C_ARBT_LOST -22
41#define OPAL_I2C_NACK_RCVD -23
42#define OPAL_I2C_STOP_ERR -24
43
44/* API Tokens (in r0) */
Michael Ellermand7cf83f2015-02-17 20:01:54 +110045#define OPAL_INVALID_CALL -1
46#define OPAL_TEST 0
Michael Ellermand800ba12015-02-17 20:01:53 +110047#define OPAL_CONSOLE_WRITE 1
48#define OPAL_CONSOLE_READ 2
49#define OPAL_RTC_READ 3
50#define OPAL_RTC_WRITE 4
51#define OPAL_CEC_POWER_DOWN 5
52#define OPAL_CEC_REBOOT 6
53#define OPAL_READ_NVRAM 7
54#define OPAL_WRITE_NVRAM 8
55#define OPAL_HANDLE_INTERRUPT 9
56#define OPAL_POLL_EVENTS 10
57#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
58#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
59#define OPAL_PCI_CONFIG_READ_BYTE 13
60#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
61#define OPAL_PCI_CONFIG_READ_WORD 15
62#define OPAL_PCI_CONFIG_WRITE_BYTE 16
63#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
64#define OPAL_PCI_CONFIG_WRITE_WORD 18
65#define OPAL_SET_XIVE 19
66#define OPAL_GET_XIVE 20
67#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
68#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
69#define OPAL_PCI_EEH_FREEZE_STATUS 23
70#define OPAL_PCI_SHPC 24
71#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
72#define OPAL_PCI_EEH_FREEZE_CLEAR 26
73#define OPAL_PCI_PHB_MMIO_ENABLE 27
74#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
75#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
76#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
77#define OPAL_PCI_SET_PE 31
78#define OPAL_PCI_SET_PELTV 32
79#define OPAL_PCI_SET_MVE 33
80#define OPAL_PCI_SET_MVE_ENABLE 34
81#define OPAL_PCI_GET_XIVE_REISSUE 35
82#define OPAL_PCI_SET_XIVE_REISSUE 36
83#define OPAL_PCI_SET_XIVE_PE 37
84#define OPAL_GET_XIVE_SOURCE 38
85#define OPAL_GET_MSI_32 39
86#define OPAL_GET_MSI_64 40
87#define OPAL_START_CPU 41
88#define OPAL_QUERY_CPU_STATUS 42
Michael Ellermand7cf83f2015-02-17 20:01:54 +110089#define OPAL_WRITE_OPPANEL 43 /* unimplemented */
Michael Ellermand800ba12015-02-17 20:01:53 +110090#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
91#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
92#define OPAL_PCI_RESET 49
93#define OPAL_PCI_GET_HUB_DIAG_DATA 50
94#define OPAL_PCI_GET_PHB_DIAG_DATA 51
95#define OPAL_PCI_FENCE_PHB 52
96#define OPAL_PCI_REINIT 53
97#define OPAL_PCI_MASK_PE_ERROR 54
98#define OPAL_SET_SLOT_LED_STATUS 55
99#define OPAL_GET_EPOW_STATUS 56
100#define OPAL_SET_SYSTEM_ATTENTION_LED 57
101#define OPAL_RESERVED1 58
102#define OPAL_RESERVED2 59
103#define OPAL_PCI_NEXT_ERROR 60
104#define OPAL_PCI_EEH_FREEZE_STATUS2 61
105#define OPAL_PCI_POLL 62
106#define OPAL_PCI_MSI_EOI 63
107#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
108#define OPAL_XSCOM_READ 65
109#define OPAL_XSCOM_WRITE 66
110#define OPAL_LPC_READ 67
111#define OPAL_LPC_WRITE 68
112#define OPAL_RETURN_CPU 69
113#define OPAL_REINIT_CPUS 70
114#define OPAL_ELOG_READ 71
115#define OPAL_ELOG_WRITE 72
116#define OPAL_ELOG_ACK 73
117#define OPAL_ELOG_RESEND 74
118#define OPAL_ELOG_SIZE 75
119#define OPAL_FLASH_VALIDATE 76
120#define OPAL_FLASH_MANAGE 77
121#define OPAL_FLASH_UPDATE 78
122#define OPAL_RESYNC_TIMEBASE 79
123#define OPAL_CHECK_TOKEN 80
124#define OPAL_DUMP_INIT 81
125#define OPAL_DUMP_INFO 82
126#define OPAL_DUMP_READ 83
127#define OPAL_DUMP_ACK 84
128#define OPAL_GET_MSG 85
129#define OPAL_CHECK_ASYNC_COMPLETION 86
130#define OPAL_SYNC_HOST_REBOOT 87
131#define OPAL_SENSOR_READ 88
132#define OPAL_GET_PARAM 89
133#define OPAL_SET_PARAM 90
134#define OPAL_DUMP_RESEND 91
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100135#define OPAL_ELOG_SEND 92 /* Deprecated */
136#define OPAL_PCI_SET_PHB_CAPI_MODE 93
Michael Ellermand800ba12015-02-17 20:01:53 +1100137#define OPAL_DUMP_INFO2 94
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100138#define OPAL_WRITE_OPPANEL_ASYNC 95
Michael Ellermand800ba12015-02-17 20:01:53 +1100139#define OPAL_PCI_ERR_INJECT 96
140#define OPAL_PCI_EEH_FREEZE_SET 97
141#define OPAL_HANDLE_HMI 98
142#define OPAL_CONFIG_CPU_IDLE_STATE 99
143#define OPAL_SLW_SET_REG 100
144#define OPAL_REGISTER_DUMP_REGION 101
145#define OPAL_UNREGISTER_DUMP_REGION 102
146#define OPAL_WRITE_TPO 103
147#define OPAL_READ_TPO 104
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100148#define OPAL_GET_DPO_STATUS 105
149#define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
Michael Ellermand800ba12015-02-17 20:01:53 +1100150#define OPAL_IPMI_SEND 107
151#define OPAL_IPMI_RECV 108
152#define OPAL_I2C_REQUEST 109
Cyril Bured591902015-04-01 14:05:30 +0800153#define OPAL_FLASH_READ 110
154#define OPAL_FLASH_WRITE 111
155#define OPAL_FLASH_ERASE 112
Jeremy Kerr0d7cd852015-06-04 21:51:47 +0800156#define OPAL_PRD_MSG 113
157#define OPAL_LAST 113
Michael Ellermand800ba12015-02-17 20:01:53 +1100158
159/* Device tree flags */
160
161/* Flags set in power-mgmt nodes in device tree if
162 * respective idle states are supported in the platform.
163 */
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100164#define OPAL_PM_NAP_ENABLED 0x00010000
165#define OPAL_PM_SLEEP_ENABLED 0x00020000
166#define OPAL_PM_WINKLE_ENABLED 0x00040000
167#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
Michael Ellermand800ba12015-02-17 20:01:53 +1100168
Shreyas B. Prabhu5703d2f2015-04-20 10:32:58 +0530169/*
170 * OPAL_CONFIG_CPU_IDLE_STATE parameters
171 */
172#define OPAL_CONFIG_IDLE_FASTSLEEP 1
173#define OPAL_CONFIG_IDLE_UNDO 0
174#define OPAL_CONFIG_IDLE_APPLY 1
175
Michael Ellermand800ba12015-02-17 20:01:53 +1100176#ifndef __ASSEMBLY__
177
178/* Other enums */
Michael Ellermand800ba12015-02-17 20:01:53 +1100179enum OpalFreezeState {
180 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
181 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
182 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
183 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
184 OPAL_EEH_STOPPED_RESET = 4,
185 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
186 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
187};
188
189enum OpalEehFreezeActionToken {
190 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
191 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
192 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
193
194 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
195 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
196 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
197};
198
199enum OpalPciStatusToken {
200 OPAL_EEH_NO_ERROR = 0,
201 OPAL_EEH_IOC_ERROR = 1,
202 OPAL_EEH_PHB_ERROR = 2,
203 OPAL_EEH_PE_ERROR = 3,
204 OPAL_EEH_PE_MMIO_ERROR = 4,
205 OPAL_EEH_PE_DMA_ERROR = 5
206};
207
208enum OpalPciErrorSeverity {
209 OPAL_EEH_SEV_NO_ERROR = 0,
210 OPAL_EEH_SEV_IOC_DEAD = 1,
211 OPAL_EEH_SEV_PHB_DEAD = 2,
212 OPAL_EEH_SEV_PHB_FENCED = 3,
213 OPAL_EEH_SEV_PE_ER = 4,
214 OPAL_EEH_SEV_INF = 5
215};
216
217enum OpalErrinjectType {
218 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
219 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
220};
221
222enum OpalErrinjectFunc {
223 /* IOA bus specific errors */
224 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
225 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
226 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
227 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
228 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
229 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
230 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
231 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
232 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
233 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
234 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
235 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
236 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
237 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
238 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
239 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
240 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
241 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
242 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
243 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
244};
245
Michael Ellermand800ba12015-02-17 20:01:53 +1100246enum OpalMmioWindowType {
247 OPAL_M32_WINDOW_TYPE = 1,
248 OPAL_M64_WINDOW_TYPE = 2,
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100249 OPAL_IO_WINDOW_TYPE = 3
Michael Ellermand800ba12015-02-17 20:01:53 +1100250};
251
Michael Ellermand800ba12015-02-17 20:01:53 +1100252enum OpalExceptionHandler {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100253 OPAL_MACHINE_CHECK_HANDLER = 1,
Michael Ellermand800ba12015-02-17 20:01:53 +1100254 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100255 OPAL_SOFTPATCH_HANDLER = 3
Michael Ellermand800ba12015-02-17 20:01:53 +1100256};
257
258enum OpalPendingState {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100259 OPAL_EVENT_OPAL_INTERNAL = 0x1,
260 OPAL_EVENT_NVRAM = 0x2,
261 OPAL_EVENT_RTC = 0x4,
262 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
263 OPAL_EVENT_CONSOLE_INPUT = 0x10,
264 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
265 OPAL_EVENT_ERROR_LOG = 0x40,
266 OPAL_EVENT_EPOW = 0x80,
267 OPAL_EVENT_LED_STATUS = 0x100,
268 OPAL_EVENT_PCI_ERROR = 0x200,
269 OPAL_EVENT_DUMP_AVAIL = 0x400,
270 OPAL_EVENT_MSG_PENDING = 0x800,
Michael Ellermand800ba12015-02-17 20:01:53 +1100271};
272
273enum OpalThreadStatus {
274 OPAL_THREAD_INACTIVE = 0x0,
275 OPAL_THREAD_STARTED = 0x1,
276 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
277};
278
279enum OpalPciBusCompare {
280 OpalPciBusAny = 0, /* Any bus number match */
281 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
282 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
283 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
284 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
285 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
286 OpalPciBusAll = 7, /* Match bus number exactly */
287};
288
289enum OpalDeviceCompare {
290 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
291 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
292};
293
294enum OpalFuncCompare {
295 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
296 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
297};
298
299enum OpalPeAction {
300 OPAL_UNMAP_PE = 0,
301 OPAL_MAP_PE = 1
302};
303
304enum OpalPeltvAction {
305 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
306 OPAL_ADD_PE_TO_DOMAIN = 1
307};
308
309enum OpalMveEnableAction {
310 OPAL_DISABLE_MVE = 0,
311 OPAL_ENABLE_MVE = 1
312};
313
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100314enum OpalM64Action {
Michael Ellermand800ba12015-02-17 20:01:53 +1100315 OPAL_DISABLE_M64 = 0,
316 OPAL_ENABLE_M64_SPLIT = 1,
317 OPAL_ENABLE_M64_NON_SPLIT = 2
318};
319
320enum OpalPciResetScope {
321 OPAL_RESET_PHB_COMPLETE = 1,
322 OPAL_RESET_PCI_LINK = 2,
323 OPAL_RESET_PHB_ERROR = 3,
324 OPAL_RESET_PCI_HOT = 4,
325 OPAL_RESET_PCI_FUNDAMENTAL = 5,
326 OPAL_RESET_PCI_IODA_TABLE = 6
327};
328
329enum OpalPciReinitScope {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100330 /*
331 * Note: we chose values that do not overlap
332 * OpalPciResetScope as OPAL v2 used the same
333 * enum for both
334 */
Michael Ellermand800ba12015-02-17 20:01:53 +1100335 OPAL_REINIT_PCI_DEV = 1000
336};
337
338enum OpalPciResetState {
339 OPAL_DEASSERT_RESET = 0,
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100340 OPAL_ASSERT_RESET = 1
Michael Ellermand800ba12015-02-17 20:01:53 +1100341};
342
Michael Ellermand800ba12015-02-17 20:01:53 +1100343/*
344 * Address cycle types for LPC accesses. These also correspond
345 * to the content of the first cell of the "reg" property for
346 * device nodes on the LPC bus
347 */
348enum OpalLPCAddressType {
349 OPAL_LPC_MEM = 0,
350 OPAL_LPC_IO = 1,
351 OPAL_LPC_FW = 2,
352};
353
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100354enum opal_msg_type {
355 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
356 * additional params function-specific
357 */
358 OPAL_MSG_MEM_ERR,
359 OPAL_MSG_EPOW,
360 OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
361 OPAL_MSG_HMI_EVT,
362 OPAL_MSG_DPO,
Jeremy Kerr0d7cd852015-06-04 21:51:47 +0800363 OPAL_MSG_PRD,
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100364 OPAL_MSG_TYPE_MAX,
Michael Ellermand800ba12015-02-17 20:01:53 +1100365};
366
367struct opal_msg {
368 __be32 msg_type;
369 __be32 reserved;
370 __be64 params[8];
371};
372
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100373/* System parameter permission */
374enum OpalSysparamPerm {
375 OPAL_SYSPARAM_READ = 0x1,
376 OPAL_SYSPARAM_WRITE = 0x2,
377 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
378};
379
Michael Ellermand800ba12015-02-17 20:01:53 +1100380enum {
381 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
382};
383
384struct opal_ipmi_msg {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100385 uint8_t version;
386 uint8_t netfn;
387 uint8_t cmd;
388 uint8_t data[];
Michael Ellermand800ba12015-02-17 20:01:53 +1100389};
390
391/* FSP memory errors handling */
392enum OpalMemErr_Version {
393 OpalMemErr_V1 = 1,
394};
395
396enum OpalMemErrType {
397 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
398 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
Michael Ellermand800ba12015-02-17 20:01:53 +1100399};
400
401/* Memory Reilience error type */
402enum OpalMemErr_ResilErrType {
403 OPAL_MEM_RESILIENCE_CE = 0,
404 OPAL_MEM_RESILIENCE_UE,
405 OPAL_MEM_RESILIENCE_UE_SCRUB,
406};
407
408/* Dynamic Memory Deallocation type */
409enum OpalMemErr_DynErrType {
410 OPAL_MEM_DYNAMIC_DEALLOC = 0,
411};
412
Michael Ellermand800ba12015-02-17 20:01:53 +1100413struct OpalMemoryErrorData {
414 enum OpalMemErr_Version version:8; /* 0x00 */
415 enum OpalMemErrType type:8; /* 0x01 */
416 __be16 flags; /* 0x02 */
417 uint8_t reserved_1[4]; /* 0x04 */
418
419 union {
420 /* Memory Resilience corrected/uncorrected error info */
421 struct {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100422 enum OpalMemErr_ResilErrType resil_err_type:8;
423 uint8_t reserved_1[7];
424 __be64 physical_address_start;
425 __be64 physical_address_end;
Michael Ellermand800ba12015-02-17 20:01:53 +1100426 } resilience;
427 /* Dynamic memory deallocation error info */
428 struct {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100429 enum OpalMemErr_DynErrType dyn_err_type:8;
430 uint8_t reserved_1[7];
431 __be64 physical_address_start;
432 __be64 physical_address_end;
Michael Ellermand800ba12015-02-17 20:01:53 +1100433 } dyn_dealloc;
434 } u;
435};
436
437/* HMI interrupt event */
438enum OpalHMI_Version {
439 OpalHMIEvt_V1 = 1,
Mahesh Salgaonkarc33e11d2015-05-05 13:34:58 +0530440 OpalHMIEvt_V2 = 2,
Michael Ellermand800ba12015-02-17 20:01:53 +1100441};
442
443enum OpalHMI_Severity {
444 OpalHMI_SEV_NO_ERROR = 0,
445 OpalHMI_SEV_WARNING = 1,
446 OpalHMI_SEV_ERROR_SYNC = 2,
447 OpalHMI_SEV_FATAL = 3,
448};
449
450enum OpalHMI_Disposition {
451 OpalHMI_DISPOSITION_RECOVERED = 0,
452 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
453};
454
455enum OpalHMI_ErrType {
456 OpalHMI_ERROR_MALFUNC_ALERT = 0,
457 OpalHMI_ERROR_PROC_RECOV_DONE,
458 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
459 OpalHMI_ERROR_PROC_RECOV_MASKED,
460 OpalHMI_ERROR_TFAC,
461 OpalHMI_ERROR_TFMR_PARITY,
462 OpalHMI_ERROR_HA_OVERFLOW_WARN,
463 OpalHMI_ERROR_XSCOM_FAIL,
464 OpalHMI_ERROR_XSCOM_DONE,
465 OpalHMI_ERROR_SCOM_FIR,
466 OpalHMI_ERROR_DEBUG_TRIG_FIR,
467 OpalHMI_ERROR_HYP_RESOURCE,
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100468 OpalHMI_ERROR_CAPP_RECOVERY,
Michael Ellermand800ba12015-02-17 20:01:53 +1100469};
470
Mahesh Salgaonkarc33e11d2015-05-05 13:34:58 +0530471enum OpalHMI_XstopType {
472 CHECKSTOP_TYPE_UNKNOWN = 0,
473 CHECKSTOP_TYPE_CORE = 1,
474 CHECKSTOP_TYPE_NX = 2,
475};
476
477enum OpalHMI_CoreXstopReason {
478 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
479 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
480 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
481 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
482 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
483 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
484 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
485 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
486 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
487 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
488 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
489 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
490 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
491 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
492 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
493 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
494 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
495};
496
497enum OpalHMI_NestAccelXstopReason {
498 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
499 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
500 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
501 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
502 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
503 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
504 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
505 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
506 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
507 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
508 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
509 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
510 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
511 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
512};
513
Michael Ellermand800ba12015-02-17 20:01:53 +1100514struct OpalHMIEvent {
515 uint8_t version; /* 0x00 */
516 uint8_t severity; /* 0x01 */
517 uint8_t type; /* 0x02 */
518 uint8_t disposition; /* 0x03 */
519 uint8_t reserved_1[4]; /* 0x04 */
520
521 __be64 hmer;
522 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
523 __be64 tfmr;
Mahesh Salgaonkarc33e11d2015-05-05 13:34:58 +0530524
525 /* version 2 and later */
526 union {
527 /*
528 * checkstop info (Core/NX).
529 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
530 */
531 struct {
532 uint8_t xstop_type; /* enum OpalHMI_XstopType */
533 uint8_t reserved_1[3];
534 __be32 xstop_reason;
535 union {
536 __be32 pir; /* for CHECKSTOP_TYPE_CORE */
537 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
538 } u;
539 } xstop_error;
540 } u;
Michael Ellermand800ba12015-02-17 20:01:53 +1100541};
542
543enum {
544 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
545 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
546 OPAL_P7IOC_DIAG_TYPE_BI = 2,
547 OPAL_P7IOC_DIAG_TYPE_CI = 3,
548 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
549 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
550 OPAL_P7IOC_DIAG_TYPE_LAST = 6
551};
552
553struct OpalIoP7IOCErrorData {
554 __be16 type;
555
556 /* GEM */
557 __be64 gemXfir;
558 __be64 gemRfir;
559 __be64 gemRirqfir;
560 __be64 gemMask;
561 __be64 gemRwof;
562
563 /* LEM */
564 __be64 lemFir;
565 __be64 lemErrMask;
566 __be64 lemAction0;
567 __be64 lemAction1;
568 __be64 lemWof;
569
570 union {
571 struct OpalIoP7IOCRgcErrorData {
572 __be64 rgcStatus; /* 3E1C10 */
573 __be64 rgcLdcp; /* 3E1C18 */
574 }rgc;
575 struct OpalIoP7IOCBiErrorData {
576 __be64 biLdcp0; /* 3C0100, 3C0118 */
577 __be64 biLdcp1; /* 3C0108, 3C0120 */
578 __be64 biLdcp2; /* 3C0110, 3C0128 */
579 __be64 biFenceStatus; /* 3C0130, 3C0130 */
580
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100581 uint8_t biDownbound; /* BI Downbound or Upbound */
Michael Ellermand800ba12015-02-17 20:01:53 +1100582 }bi;
583 struct OpalIoP7IOCCiErrorData {
584 __be64 ciPortStatus; /* 3Dn008 */
585 __be64 ciPortLdcp; /* 3Dn010 */
586
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100587 uint8_t ciPort; /* Index of CI port: 0/1 */
Michael Ellermand800ba12015-02-17 20:01:53 +1100588 }ci;
589 };
590};
591
592/**
593 * This structure defines the overlay which will be used to store PHB error
594 * data upon request.
595 */
596enum {
597 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
598};
599
600enum {
601 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
602 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
603};
604
605enum {
606 OPAL_P7IOC_NUM_PEST_REGS = 128,
607 OPAL_PHB3_NUM_PEST_REGS = 256
608};
609
Michael Ellermand800ba12015-02-17 20:01:53 +1100610struct OpalIoPhbErrorCommon {
611 __be32 version;
612 __be32 ioType;
613 __be32 len;
614};
615
616struct OpalIoP7IOCPhbErrorData {
617 struct OpalIoPhbErrorCommon common;
618
619 __be32 brdgCtl;
620
621 // P7IOC utl regs
622 __be32 portStatusReg;
623 __be32 rootCmplxStatus;
624 __be32 busAgentStatus;
625
626 // P7IOC cfg regs
627 __be32 deviceStatus;
628 __be32 slotStatus;
629 __be32 linkStatus;
630 __be32 devCmdStatus;
631 __be32 devSecStatus;
632
633 // cfg AER regs
634 __be32 rootErrorStatus;
635 __be32 uncorrErrorStatus;
636 __be32 corrErrorStatus;
637 __be32 tlpHdr1;
638 __be32 tlpHdr2;
639 __be32 tlpHdr3;
640 __be32 tlpHdr4;
641 __be32 sourceId;
642
643 __be32 rsv3;
644
645 // Record data about the call to allocate a buffer.
646 __be64 errorClass;
647 __be64 correlator;
648
649 //P7IOC MMIO Error Regs
650 __be64 p7iocPlssr; // n120
651 __be64 p7iocCsr; // n110
652 __be64 lemFir; // nC00
653 __be64 lemErrorMask; // nC18
654 __be64 lemWOF; // nC40
655 __be64 phbErrorStatus; // nC80
656 __be64 phbFirstErrorStatus; // nC88
657 __be64 phbErrorLog0; // nCC0
658 __be64 phbErrorLog1; // nCC8
659 __be64 mmioErrorStatus; // nD00
660 __be64 mmioFirstErrorStatus; // nD08
661 __be64 mmioErrorLog0; // nD40
662 __be64 mmioErrorLog1; // nD48
663 __be64 dma0ErrorStatus; // nD80
664 __be64 dma0FirstErrorStatus; // nD88
665 __be64 dma0ErrorLog0; // nDC0
666 __be64 dma0ErrorLog1; // nDC8
667 __be64 dma1ErrorStatus; // nE00
668 __be64 dma1FirstErrorStatus; // nE08
669 __be64 dma1ErrorLog0; // nE40
670 __be64 dma1ErrorLog1; // nE48
671 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
672 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
673};
674
675struct OpalIoPhb3ErrorData {
676 struct OpalIoPhbErrorCommon common;
677
678 __be32 brdgCtl;
679
680 /* PHB3 UTL regs */
681 __be32 portStatusReg;
682 __be32 rootCmplxStatus;
683 __be32 busAgentStatus;
684
685 /* PHB3 cfg regs */
686 __be32 deviceStatus;
687 __be32 slotStatus;
688 __be32 linkStatus;
689 __be32 devCmdStatus;
690 __be32 devSecStatus;
691
692 /* cfg AER regs */
693 __be32 rootErrorStatus;
694 __be32 uncorrErrorStatus;
695 __be32 corrErrorStatus;
696 __be32 tlpHdr1;
697 __be32 tlpHdr2;
698 __be32 tlpHdr3;
699 __be32 tlpHdr4;
700 __be32 sourceId;
701
702 __be32 rsv3;
703
704 /* Record data about the call to allocate a buffer */
705 __be64 errorClass;
706 __be64 correlator;
707
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100708 /* PHB3 MMIO Error Regs */
Michael Ellermand800ba12015-02-17 20:01:53 +1100709 __be64 nFir; /* 000 */
710 __be64 nFirMask; /* 003 */
711 __be64 nFirWOF; /* 008 */
Michael Ellermand800ba12015-02-17 20:01:53 +1100712 __be64 phbPlssr; /* 120 */
713 __be64 phbCsr; /* 110 */
714 __be64 lemFir; /* C00 */
715 __be64 lemErrorMask; /* C18 */
716 __be64 lemWOF; /* C40 */
717 __be64 phbErrorStatus; /* C80 */
718 __be64 phbFirstErrorStatus; /* C88 */
719 __be64 phbErrorLog0; /* CC0 */
720 __be64 phbErrorLog1; /* CC8 */
721 __be64 mmioErrorStatus; /* D00 */
722 __be64 mmioFirstErrorStatus; /* D08 */
723 __be64 mmioErrorLog0; /* D40 */
724 __be64 mmioErrorLog1; /* D48 */
725 __be64 dma0ErrorStatus; /* D80 */
726 __be64 dma0FirstErrorStatus; /* D88 */
727 __be64 dma0ErrorLog0; /* DC0 */
728 __be64 dma0ErrorLog1; /* DC8 */
729 __be64 dma1ErrorStatus; /* E00 */
730 __be64 dma1FirstErrorStatus; /* E08 */
731 __be64 dma1ErrorLog0; /* E40 */
732 __be64 dma1ErrorLog1; /* E48 */
733 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
734 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
735};
736
737enum {
738 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
739 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
740};
741
742typedef struct oppanel_line {
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100743 __be64 line;
744 __be64 line_len;
Michael Ellermand800ba12015-02-17 20:01:53 +1100745} oppanel_line_t;
746
Jeremy Kerr0d7cd852015-06-04 21:51:47 +0800747enum opal_prd_msg_type {
748 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
749 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
750 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
751 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
752 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
753 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
754};
755
756struct opal_prd_msg_header {
757 uint8_t type;
758 uint8_t pad[1];
759 __be16 size;
760};
761
762struct opal_prd_msg;
763
Michael Ellermand800ba12015-02-17 20:01:53 +1100764/*
765 * SG entries
766 *
767 * WARNING: The current implementation requires each entry
768 * to represent a block that is 4k aligned *and* each block
769 * size except the last one in the list to be as well.
770 */
771struct opal_sg_entry {
772 __be64 data;
773 __be64 length;
774};
775
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100776/*
777 * Candiate image SG list.
778 *
779 * length = VER | length
780 */
Michael Ellermand800ba12015-02-17 20:01:53 +1100781struct opal_sg_list {
782 __be64 length;
783 __be64 next;
784 struct opal_sg_entry entry[];
785};
786
787/*
788 * Dump region ID range usable by the OS
789 */
790#define OPAL_DUMP_REGION_HOST_START 0x80
791#define OPAL_DUMP_REGION_LOG_BUF 0x80
792#define OPAL_DUMP_REGION_HOST_END 0xFF
793
Michael Ellermand7cf83f2015-02-17 20:01:54 +1100794/* CAPI modes for PHB */
795enum {
796 OPAL_PHB_CAPI_MODE_PCIE = 0,
797 OPAL_PHB_CAPI_MODE_CAPI = 1,
798 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
799 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
800};
801
Michael Ellermand800ba12015-02-17 20:01:53 +1100802/* OPAL I2C request */
803struct opal_i2c_request {
804 uint8_t type;
805#define OPAL_I2C_RAW_READ 0
806#define OPAL_I2C_RAW_WRITE 1
807#define OPAL_I2C_SM_READ 2
808#define OPAL_I2C_SM_WRITE 3
809 uint8_t flags;
810#define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
811 uint8_t subaddr_sz; /* Max 4 */
812 uint8_t reserved;
813 __be16 addr; /* 7 or 10 bit address */
814 __be16 reserved2;
815 __be32 subaddr; /* Sub-address if any */
816 __be32 size; /* Data size */
817 __be64 buffer_ra; /* Buffer real address */
818};
819
Vipin K Parashar3b476aad2015-07-08 16:36:01 +0530820/*
821 * EPOW status sharing (OPAL and the host)
822 *
823 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
824 * with individual elements being 16 bits wide to fetch the system
825 * wide EPOW status. Each element in the buffer will contain the
826 * EPOW status in it's bit representation for a particular EPOW sub
827 * class as defiend here. So multiple detailed EPOW status bits
828 * specific for any sub class can be represented in a single buffer
829 * element as it's bit representation.
830 */
831
832/* System EPOW type */
833enum OpalSysEpow {
834 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
835 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
836 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
837 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
838};
839
840/* Power EPOW */
841enum OpalSysPower {
842 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
843 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
844 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
845 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
846};
847
848/* Temperature EPOW */
849enum OpalSysTemp {
850 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
851 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
852 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
853};
854
855/* Cooling EPOW */
856enum OpalSysCooling {
857 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
858};
859
Michael Ellermand800ba12015-02-17 20:01:53 +1100860#endif /* __ASSEMBLY__ */
861
862#endif /* __OPAL_API_H */