blob: 03ec5e86d1a1fe0a4619ef0fe33d2122ea7190b1 [file] [log] [blame]
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27#include <linux/list_sort.h>
28#include <drm/drmP.h>
29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h"
31#include "amdgpu_trace.h"
32
33#define AMDGPU_CS_MAX_PRIORITY 32u
34#define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1)
35
36/* This is based on the bucket sort with O(n) time complexity.
37 * An item with priority "i" is added to bucket[i]. The lists are then
38 * concatenated in descending order.
39 */
40struct amdgpu_cs_buckets {
41 struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
42};
43
44static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
45{
46 unsigned i;
47
48 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
49 INIT_LIST_HEAD(&b->bucket[i]);
50}
51
52static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
53 struct list_head *item, unsigned priority)
54{
55 /* Since buffers which appear sooner in the relocation list are
56 * likely to be used more often than buffers which appear later
57 * in the list, the sort mustn't change the ordering of buffers
58 * with the same priority, i.e. it must be stable.
59 */
60 list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
61}
62
63static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
64 struct list_head *out_list)
65{
66 unsigned i;
67
68 /* Connect the sorted buckets in the output list. */
69 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
70 list_splice(&b->bucket[i], out_list);
71 }
72}
73
74int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
75 u32 ip_instance, u32 ring,
76 struct amdgpu_ring **out_ring)
77{
78 /* Right now all IPs have only one instance - multiple rings. */
79 if (ip_instance != 0) {
80 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
81 return -EINVAL;
82 }
83
84 switch (ip_type) {
85 default:
86 DRM_ERROR("unknown ip type: %d\n", ip_type);
87 return -EINVAL;
88 case AMDGPU_HW_IP_GFX:
89 if (ring < adev->gfx.num_gfx_rings) {
90 *out_ring = &adev->gfx.gfx_ring[ring];
91 } else {
92 DRM_ERROR("only %d gfx rings are supported now\n",
93 adev->gfx.num_gfx_rings);
94 return -EINVAL;
95 }
96 break;
97 case AMDGPU_HW_IP_COMPUTE:
98 if (ring < adev->gfx.num_compute_rings) {
99 *out_ring = &adev->gfx.compute_ring[ring];
100 } else {
101 DRM_ERROR("only %d compute rings are supported now\n",
102 adev->gfx.num_compute_rings);
103 return -EINVAL;
104 }
105 break;
106 case AMDGPU_HW_IP_DMA:
Alex Deucherc113ea12015-10-08 16:30:37 -0400107 if (ring < adev->sdma.num_instances) {
108 *out_ring = &adev->sdma.instance[ring].ring;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400109 } else {
Alex Deucherc113ea12015-10-08 16:30:37 -0400110 DRM_ERROR("only %d SDMA rings are supported\n",
111 adev->sdma.num_instances);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400112 return -EINVAL;
113 }
114 break;
115 case AMDGPU_HW_IP_UVD:
116 *out_ring = &adev->uvd.ring;
117 break;
118 case AMDGPU_HW_IP_VCE:
119 if (ring < 2){
120 *out_ring = &adev->vce.ring[ring];
121 } else {
122 DRM_ERROR("only two VCE rings are supported\n");
123 return -EINVAL;
124 }
125 break;
126 }
127 return 0;
128}
129
Christian König91acbeb2015-12-14 16:42:31 +0100130static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
131 struct drm_amdgpu_cs_chunk_fence *fence_data)
132{
133 struct drm_gem_object *gobj;
134 uint32_t handle;
135
136 handle = fence_data->handle;
137 gobj = drm_gem_object_lookup(p->adev->ddev, p->filp,
138 fence_data->handle);
139 if (gobj == NULL)
140 return -EINVAL;
141
142 p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
143 p->uf.offset = fence_data->offset;
144
145 if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) {
146 drm_gem_object_unreference_unlocked(gobj);
147 return -EINVAL;
148 }
149
150 p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo);
151 p->uf_entry.prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
152 p->uf_entry.allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
153 p->uf_entry.priority = 0;
154 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
155 p->uf_entry.tv.shared = true;
156
157 drm_gem_object_unreference_unlocked(gobj);
158 return 0;
159}
160
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400161int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
162{
163 union drm_amdgpu_cs *cs = data;
164 uint64_t *chunk_array_user;
Dan Carpenter1d263472015-09-23 13:59:28 +0300165 uint64_t *chunk_array;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400166 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
Dan Carpenter54313502015-09-25 14:36:55 +0300167 unsigned size;
168 int i;
Dan Carpenter1d263472015-09-23 13:59:28 +0300169 int ret;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400170
Dan Carpenter1d263472015-09-23 13:59:28 +0300171 if (cs->in.num_chunks == 0)
172 return 0;
173
174 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
175 if (!chunk_array)
176 return -ENOMEM;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400177
Christian König3cb485f2015-05-11 15:34:59 +0200178 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
179 if (!p->ctx) {
Dan Carpenter1d263472015-09-23 13:59:28 +0300180 ret = -EINVAL;
181 goto free_chunk;
Christian König3cb485f2015-05-11 15:34:59 +0200182 }
Dan Carpenter1d263472015-09-23 13:59:28 +0300183
Chunming Zhoua3348bb2015-08-18 16:25:46 +0800184 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400185
186 /* get chunks */
187 INIT_LIST_HEAD(&p->validated);
Arnd Bergmann028423b2015-10-07 09:41:27 +0200188 chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400189 if (copy_from_user(chunk_array, chunk_array_user,
190 sizeof(uint64_t)*cs->in.num_chunks)) {
Dan Carpenter1d263472015-09-23 13:59:28 +0300191 ret = -EFAULT;
192 goto put_bo_list;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400193 }
194
195 p->nchunks = cs->in.num_chunks;
monk.liue60b3442015-07-17 18:39:25 +0800196 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400197 GFP_KERNEL);
Dan Carpenter1d263472015-09-23 13:59:28 +0300198 if (!p->chunks) {
199 ret = -ENOMEM;
200 goto put_bo_list;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400201 }
202
203 for (i = 0; i < p->nchunks; i++) {
204 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
205 struct drm_amdgpu_cs_chunk user_chunk;
206 uint32_t __user *cdata;
207
Arnd Bergmann028423b2015-10-07 09:41:27 +0200208 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400209 if (copy_from_user(&user_chunk, chunk_ptr,
210 sizeof(struct drm_amdgpu_cs_chunk))) {
Dan Carpenter1d263472015-09-23 13:59:28 +0300211 ret = -EFAULT;
212 i--;
213 goto free_partial_kdata;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400214 }
215 p->chunks[i].chunk_id = user_chunk.chunk_id;
216 p->chunks[i].length_dw = user_chunk.length_dw;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400217
218 size = p->chunks[i].length_dw;
Arnd Bergmann028423b2015-10-07 09:41:27 +0200219 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400220
221 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
222 if (p->chunks[i].kdata == NULL) {
Dan Carpenter1d263472015-09-23 13:59:28 +0300223 ret = -ENOMEM;
224 i--;
225 goto free_partial_kdata;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400226 }
227 size *= sizeof(uint32_t);
228 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
Dan Carpenter1d263472015-09-23 13:59:28 +0300229 ret = -EFAULT;
230 goto free_partial_kdata;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400231 }
232
Christian König9a5e8fb2015-06-23 17:07:03 +0200233 switch (p->chunks[i].chunk_id) {
234 case AMDGPU_CHUNK_ID_IB:
235 p->num_ibs++;
236 break;
237
238 case AMDGPU_CHUNK_ID_FENCE:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400239 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
Christian König91acbeb2015-12-14 16:42:31 +0100240 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
Dan Carpenter1d263472015-09-23 13:59:28 +0300241 ret = -EINVAL;
242 goto free_partial_kdata;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400243 }
Christian König91acbeb2015-12-14 16:42:31 +0100244
245 ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata);
246 if (ret)
247 goto free_partial_kdata;
248
Christian König9a5e8fb2015-06-23 17:07:03 +0200249 break;
250
Christian König2b48d322015-06-19 17:31:29 +0200251 case AMDGPU_CHUNK_ID_DEPENDENCIES:
252 break;
253
Christian König9a5e8fb2015-06-23 17:07:03 +0200254 default:
Dan Carpenter1d263472015-09-23 13:59:28 +0300255 ret = -EINVAL;
256 goto free_partial_kdata;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400257 }
258 }
259
monk.liue60b3442015-07-17 18:39:25 +0800260
Christian Königb203dd92015-08-18 18:23:16 +0200261 p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
Dan Carpenter1d263472015-09-23 13:59:28 +0300262 if (!p->ibs) {
263 ret = -ENOMEM;
264 goto free_all_kdata;
265 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400266
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400267 kfree(chunk_array);
Dan Carpenter1d263472015-09-23 13:59:28 +0300268 return 0;
269
270free_all_kdata:
271 i = p->nchunks - 1;
272free_partial_kdata:
273 for (; i >= 0; i--)
274 drm_free_large(p->chunks[i].kdata);
275 kfree(p->chunks);
276put_bo_list:
277 if (p->bo_list)
278 amdgpu_bo_list_put(p->bo_list);
279 amdgpu_ctx_put(p->ctx);
280free_chunk:
281 kfree(chunk_array);
282
283 return ret;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400284}
285
286/* Returns how many bytes TTM can move per IB.
287 */
288static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
289{
290 u64 real_vram_size = adev->mc.real_vram_size;
291 u64 vram_usage = atomic64_read(&adev->vram_usage);
292
293 /* This function is based on the current VRAM usage.
294 *
295 * - If all of VRAM is free, allow relocating the number of bytes that
296 * is equal to 1/4 of the size of VRAM for this IB.
297
298 * - If more than one half of VRAM is occupied, only allow relocating
299 * 1 MB of data for this IB.
300 *
301 * - From 0 to one half of used VRAM, the threshold decreases
302 * linearly.
303 * __________________
304 * 1/4 of -|\ |
305 * VRAM | \ |
306 * | \ |
307 * | \ |
308 * | \ |
309 * | \ |
310 * | \ |
311 * | \________|1 MB
312 * |----------------|
313 * VRAM 0 % 100 %
314 * used used
315 *
316 * Note: It's a threshold, not a limit. The threshold must be crossed
317 * for buffer relocations to stop, so any buffer of an arbitrary size
318 * can be moved as long as the threshold isn't crossed before
319 * the relocation takes place. We don't want to disable buffer
320 * relocations completely.
321 *
322 * The idea is that buffers should be placed in VRAM at creation time
323 * and TTM should only do a minimum number of relocations during
324 * command submission. In practice, you need to submit at least
325 * a dozen IBs to move all buffers to VRAM if they are in GTT.
326 *
327 * Also, things can get pretty crazy under memory pressure and actual
328 * VRAM usage can change a lot, so playing safe even at 50% does
329 * consistently increase performance.
330 */
331
332 u64 half_vram = real_vram_size >> 1;
333 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
334 u64 bytes_moved_threshold = half_free_vram >> 1;
335 return max(bytes_moved_threshold, 1024*1024ull);
336}
337
Christian Königf69f90a12015-12-21 19:47:42 +0100338int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
Christian Königa5b75052015-09-03 16:40:39 +0200339 struct list_head *validated)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400340{
Christian Königf69f90a12015-12-21 19:47:42 +0100341 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
342 struct amdgpu_vm *vm = &fpriv->vm;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400343 struct amdgpu_bo_list_entry *lobj;
Christian Königf69f90a12015-12-21 19:47:42 +0100344 u64 initial_bytes_moved;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400345 int r;
346
Christian Königa5b75052015-09-03 16:40:39 +0200347 list_for_each_entry(lobj, validated, tv.head) {
Christian König36409d122015-12-21 20:31:35 +0100348 struct amdgpu_bo *bo = lobj->robj;
349 uint32_t domain;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400350
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400351 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
Christian König36409d122015-12-21 20:31:35 +0100352 if (bo->pin_count)
353 continue;
354
355 /* Avoid moving this one if we have moved too many buffers
356 * for this IB already.
357 *
358 * Note that this allows moving at least one buffer of
359 * any size, because it doesn't take the current "bo"
360 * into account. We don't want to disallow buffer moves
361 * completely.
362 */
363 if (p->bytes_moved <= p->bytes_moved_threshold)
364 domain = lobj->prefered_domains;
365 else
366 domain = lobj->allowed_domains;
367
368 retry:
369 amdgpu_ttm_placement_from_domain(bo, domain);
370 initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
371 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
372 p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
373 initial_bytes_moved;
374
375 if (unlikely(r)) {
376 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
377 domain = lobj->allowed_domains;
378 goto retry;
379 }
380 return r;
381 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400382 }
383 return 0;
384}
385
386static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
387{
388 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
389 struct amdgpu_cs_buckets buckets;
Christian Königa5b75052015-09-03 16:40:39 +0200390 struct list_head duplicates;
monk.liu840d5142015-04-27 15:19:20 +0800391 bool need_mmap_lock = false;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400392 int i, r;
393
monk.liu840d5142015-04-27 15:19:20 +0800394 if (p->bo_list) {
395 need_mmap_lock = p->bo_list->has_userptr;
396 amdgpu_cs_buckets_init(&buckets);
397 for (i = 0; i < p->bo_list->num_entries; i++)
398 amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
399 p->bo_list->array[i].priority);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400400
monk.liu840d5142015-04-27 15:19:20 +0800401 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
402 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400403
Christian König3c0eea62015-12-11 14:39:05 +0100404 INIT_LIST_HEAD(&duplicates);
Christian König56467eb2015-12-11 15:16:32 +0100405 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400406
Christian König91acbeb2015-12-14 16:42:31 +0100407 if (p->uf.bo)
408 list_add(&p->uf_entry.tv.head, &p->validated);
409
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400410 if (need_mmap_lock)
411 down_read(&current->mm->mmap_sem);
412
Christian Königa5b75052015-09-03 16:40:39 +0200413 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
414 if (unlikely(r != 0))
415 goto error_reserve;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400416
Christian Königee1782c2015-12-11 21:01:23 +0100417 amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
Christian König56467eb2015-12-11 15:16:32 +0100418
Christian Königf69f90a12015-12-21 19:47:42 +0100419 p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
420 p->bytes_moved = 0;
421
422 r = amdgpu_cs_list_validate(p, &duplicates);
Christian Königa5b75052015-09-03 16:40:39 +0200423 if (r)
424 goto error_validate;
425
Christian Königf69f90a12015-12-21 19:47:42 +0100426 r = amdgpu_cs_list_validate(p, &p->validated);
Christian Königa5b75052015-09-03 16:40:39 +0200427
428error_validate:
Christian Königeceb8a12016-01-11 15:35:21 +0100429 if (r) {
430 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
Christian Königa5b75052015-09-03 16:40:39 +0200431 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
Christian Königeceb8a12016-01-11 15:35:21 +0100432 }
Christian Königa5b75052015-09-03 16:40:39 +0200433
434error_reserve:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400435 if (need_mmap_lock)
436 up_read(&current->mm->mmap_sem);
437
438 return r;
439}
440
441static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
442{
443 struct amdgpu_bo_list_entry *e;
444 int r;
445
446 list_for_each_entry(e, &p->validated, tv.head) {
447 struct reservation_object *resv = e->robj->tbo.resv;
448 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
449
450 if (r)
451 return r;
452 }
453 return 0;
454}
455
456static int cmp_size_smaller_first(void *priv, struct list_head *a,
457 struct list_head *b)
458{
459 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
460 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
461
462 /* Sort A before B if A is smaller. */
463 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
464}
465
Christian König984810f2015-11-14 21:05:35 +0100466/**
467 * cs_parser_fini() - clean parser states
468 * @parser: parser structure holding parsing context.
469 * @error: error number
470 *
471 * If error is set than unvalidate buffer, otherwise just free memory
472 * used by parsing context.
473 **/
474static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
Chunming Zhou049fc522015-07-21 14:36:51 +0800475{
Christian Königeceb8a12016-01-11 15:35:21 +0100476 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
Christian König984810f2015-11-14 21:05:35 +0100477 unsigned i;
478
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400479 if (!error) {
Nicolai Hähnle28b8d662016-01-27 11:04:19 -0500480 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
481
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400482 /* Sort the buffer list from the smallest to largest buffer,
483 * which affects the order of buffers in the LRU list.
484 * This assures that the smallest buffers are added first
485 * to the LRU list, so they are likely to be later evicted
486 * first, instead of large buffers whose eviction is more
487 * expensive.
488 *
489 * This slightly lowers the number of bytes moved by TTM
490 * per frame under memory pressure.
491 */
492 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
493
494 ttm_eu_fence_buffer_objects(&parser->ticket,
Christian König984810f2015-11-14 21:05:35 +0100495 &parser->validated,
496 parser->fence);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400497 } else if (backoff) {
498 ttm_eu_backoff_reservation(&parser->ticket,
499 &parser->validated);
500 }
Christian König984810f2015-11-14 21:05:35 +0100501 fence_put(parser->fence);
Christian König7e52a812015-11-04 15:44:39 +0100502
Christian König3cb485f2015-05-11 15:34:59 +0200503 if (parser->ctx)
504 amdgpu_ctx_put(parser->ctx);
Chunming Zhoua3348bb2015-08-18 16:25:46 +0800505 if (parser->bo_list)
506 amdgpu_bo_list_put(parser->bo_list);
507
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400508 for (i = 0; i < parser->nchunks; i++)
509 drm_free_large(parser->chunks[i].kdata);
510 kfree(parser->chunks);
Christian Könige4a58a22015-11-05 17:00:25 +0100511 if (parser->ibs)
512 for (i = 0; i < parser->num_ibs; i++)
513 amdgpu_ib_free(parser->adev, &parser->ibs[i]);
514 kfree(parser->ibs);
Christian König91acbeb2015-12-14 16:42:31 +0100515 amdgpu_bo_unref(&parser->uf.bo);
516 amdgpu_bo_unref(&parser->uf_entry.robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400517}
518
519static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
520 struct amdgpu_vm *vm)
521{
522 struct amdgpu_device *adev = p->adev;
523 struct amdgpu_bo_va *bo_va;
524 struct amdgpu_bo *bo;
525 int i, r;
526
527 r = amdgpu_vm_update_page_directory(adev, vm);
528 if (r)
529 return r;
530
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +0200531 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
532 if (r)
533 return r;
534
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400535 r = amdgpu_vm_clear_freed(adev, vm);
536 if (r)
537 return r;
538
539 if (p->bo_list) {
540 for (i = 0; i < p->bo_list->num_entries; i++) {
Christian König91e1a522015-07-06 22:06:40 +0200541 struct fence *f;
542
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400543 /* ignore duplicates */
544 bo = p->bo_list->array[i].robj;
545 if (!bo)
546 continue;
547
548 bo_va = p->bo_list->array[i].bo_va;
549 if (bo_va == NULL)
550 continue;
551
552 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
553 if (r)
554 return r;
555
Chunming Zhoubb1e38a42015-08-03 18:19:38 +0800556 f = bo_va->last_pt_update;
Christian König91e1a522015-07-06 22:06:40 +0200557 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
558 if (r)
559 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400560 }
Christian Königb495bd32015-09-10 14:00:35 +0200561
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400562 }
563
Christian Königb495bd32015-09-10 14:00:35 +0200564 r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
565
566 if (amdgpu_vm_debug && p->bo_list) {
567 /* Invalidate all BOs to test for userspace bugs */
568 for (i = 0; i < p->bo_list->num_entries; i++) {
569 /* ignore duplicates */
570 bo = p->bo_list->array[i].robj;
571 if (!bo)
572 continue;
573
574 amdgpu_vm_bo_invalidate(adev, bo);
575 }
576 }
577
578 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400579}
580
581static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
582 struct amdgpu_cs_parser *parser)
583{
584 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
585 struct amdgpu_vm *vm = &fpriv->vm;
586 struct amdgpu_ring *ring;
587 int i, r;
588
589 if (parser->num_ibs == 0)
590 return 0;
591
592 /* Only for UVD/VCE VM emulation */
593 for (i = 0; i < parser->num_ibs; i++) {
594 ring = parser->ibs[i].ring;
595 if (ring->funcs->parse_cs) {
596 r = amdgpu_ring_parse_cs(ring, parser, i);
597 if (r)
598 return r;
599 }
600 }
601
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400602 r = amdgpu_bo_vm_update_pte(parser, vm);
Christian König984810f2015-11-14 21:05:35 +0100603 if (!r)
604 amdgpu_cs_sync_rings(parser);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400605
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400606 return r;
607}
608
609static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
610{
611 if (r == -EDEADLK) {
612 r = amdgpu_gpu_reset(adev);
613 if (!r)
614 r = -EAGAIN;
615 }
616 return r;
617}
618
619static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
620 struct amdgpu_cs_parser *parser)
621{
622 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
623 struct amdgpu_vm *vm = &fpriv->vm;
624 int i, j;
625 int r;
626
627 for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
628 struct amdgpu_cs_chunk *chunk;
629 struct amdgpu_ib *ib;
630 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400631 struct amdgpu_ring *ring;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400632
633 chunk = &parser->chunks[i];
634 ib = &parser->ibs[j];
635 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
636
637 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
638 continue;
639
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400640 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
641 chunk_ib->ip_instance, chunk_ib->ring,
642 &ring);
Marek Olšák3ccec532015-06-02 17:44:49 +0200643 if (r)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400644 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400645
646 if (ring->funcs->parse_cs) {
Christian König4802ce12015-06-10 17:20:11 +0200647 struct amdgpu_bo_va_mapping *m;
Marek Olšák3ccec532015-06-02 17:44:49 +0200648 struct amdgpu_bo *aobj = NULL;
Christian König4802ce12015-06-10 17:20:11 +0200649 uint64_t offset;
650 uint8_t *kptr;
Marek Olšák3ccec532015-06-02 17:44:49 +0200651
Christian König4802ce12015-06-10 17:20:11 +0200652 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
653 &aobj);
Marek Olšák3ccec532015-06-02 17:44:49 +0200654 if (!aobj) {
655 DRM_ERROR("IB va_start is invalid\n");
656 return -EINVAL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400657 }
658
Christian König4802ce12015-06-10 17:20:11 +0200659 if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
660 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
661 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
662 return -EINVAL;
663 }
664
Marek Olšák3ccec532015-06-02 17:44:49 +0200665 /* the IB should be reserved at this point */
Christian König4802ce12015-06-10 17:20:11 +0200666 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400667 if (r) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400668 return r;
669 }
670
Christian König4802ce12015-06-10 17:20:11 +0200671 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
672 kptr += chunk_ib->va_start - offset;
673
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400674 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
675 if (r) {
676 DRM_ERROR("Failed to get ib !\n");
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400677 return r;
678 }
679
680 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
681 amdgpu_bo_kunmap(aobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400682 } else {
683 r = amdgpu_ib_get(ring, vm, 0, ib);
684 if (r) {
685 DRM_ERROR("Failed to get ib !\n");
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400686 return r;
687 }
688
689 ib->gpu_addr = chunk_ib->va_start;
690 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400691
Marek Olšák3ccec532015-06-02 17:44:49 +0200692 ib->length_dw = chunk_ib->ib_bytes / 4;
Jammy Zhoude807f82015-05-11 23:41:41 +0800693 ib->flags = chunk_ib->flags;
Christian König3cb485f2015-05-11 15:34:59 +0200694 ib->ctx = parser->ctx;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400695 j++;
696 }
697
698 if (!parser->num_ibs)
699 return 0;
700
701 /* add GDS resources to first IB */
702 if (parser->bo_list) {
703 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
704 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
705 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
706 struct amdgpu_ib *ib = &parser->ibs[0];
707
708 if (gds) {
709 ib->gds_base = amdgpu_bo_gpu_offset(gds);
710 ib->gds_size = amdgpu_bo_size(gds);
711 }
712 if (gws) {
713 ib->gws_base = amdgpu_bo_gpu_offset(gws);
714 ib->gws_size = amdgpu_bo_size(gws);
715 }
716 if (oa) {
717 ib->oa_base = amdgpu_bo_gpu_offset(oa);
718 ib->oa_size = amdgpu_bo_size(oa);
719 }
720 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400721 /* wrap the last IB with user fence */
722 if (parser->uf.bo) {
723 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
724
725 /* UVD & VCE fw doesn't support user fences */
726 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
727 ib->ring->type == AMDGPU_RING_TYPE_VCE)
728 return -EINVAL;
729
730 ib->user = &parser->uf;
731 }
732
733 return 0;
734}
735
Christian König2b48d322015-06-19 17:31:29 +0200736static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
737 struct amdgpu_cs_parser *p)
738{
Christian König76a1ea62015-07-06 19:42:10 +0200739 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
Christian König2b48d322015-06-19 17:31:29 +0200740 struct amdgpu_ib *ib;
741 int i, j, r;
742
743 if (!p->num_ibs)
744 return 0;
745
746 /* Add dependencies to first IB */
747 ib = &p->ibs[0];
748 for (i = 0; i < p->nchunks; ++i) {
749 struct drm_amdgpu_cs_chunk_dep *deps;
750 struct amdgpu_cs_chunk *chunk;
751 unsigned num_deps;
752
753 chunk = &p->chunks[i];
754
755 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
756 continue;
757
758 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
759 num_deps = chunk->length_dw * 4 /
760 sizeof(struct drm_amdgpu_cs_chunk_dep);
761
762 for (j = 0; j < num_deps; ++j) {
Christian König2b48d322015-06-19 17:31:29 +0200763 struct amdgpu_ring *ring;
Christian König76a1ea62015-07-06 19:42:10 +0200764 struct amdgpu_ctx *ctx;
Christian König21c16bf2015-07-07 17:24:49 +0200765 struct fence *fence;
Christian König2b48d322015-06-19 17:31:29 +0200766
767 r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
768 deps[j].ip_instance,
769 deps[j].ring, &ring);
770 if (r)
771 return r;
772
Christian König76a1ea62015-07-06 19:42:10 +0200773 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
774 if (ctx == NULL)
775 return -EINVAL;
776
Christian König21c16bf2015-07-07 17:24:49 +0200777 fence = amdgpu_ctx_get_fence(ctx, ring,
778 deps[j].handle);
779 if (IS_ERR(fence)) {
780 r = PTR_ERR(fence);
Christian König76a1ea62015-07-06 19:42:10 +0200781 amdgpu_ctx_put(ctx);
Christian König2b48d322015-06-19 17:31:29 +0200782 return r;
Christian König21c16bf2015-07-07 17:24:49 +0200783
784 } else if (fence) {
785 r = amdgpu_sync_fence(adev, &ib->sync, fence);
786 fence_put(fence);
787 amdgpu_ctx_put(ctx);
788 if (r)
789 return r;
Christian König76a1ea62015-07-06 19:42:10 +0200790 }
Christian König2b48d322015-06-19 17:31:29 +0200791 }
792 }
793
794 return 0;
795}
796
Junwei Zhang4c7eb912015-09-09 09:05:55 +0800797static int amdgpu_cs_free_job(struct amdgpu_job *job)
Chunming Zhoubb977d32015-08-18 15:16:40 +0800798{
799 int i;
Junwei Zhang4c7eb912015-09-09 09:05:55 +0800800 if (job->ibs)
801 for (i = 0; i < job->num_ibs; i++)
802 amdgpu_ib_free(job->adev, &job->ibs[i]);
803 kfree(job->ibs);
804 if (job->uf.bo)
Christian Königf3f17692015-12-03 19:55:52 +0100805 amdgpu_bo_unref(&job->uf.bo);
Chunming Zhoubb977d32015-08-18 15:16:40 +0800806 return 0;
807}
808
Chunming Zhou049fc522015-07-21 14:36:51 +0800809int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
810{
811 struct amdgpu_device *adev = dev->dev_private;
812 union drm_amdgpu_cs *cs = data;
Christian König7e52a812015-11-04 15:44:39 +0100813 struct amdgpu_cs_parser parser = {};
Christian König26a69802015-08-18 21:09:33 +0200814 bool reserved_buffers = false;
815 int i, r;
Chunming Zhou049fc522015-07-21 14:36:51 +0800816
Christian König0c418f12015-09-01 15:13:53 +0200817 if (!adev->accel_working)
Chunming Zhou049fc522015-07-21 14:36:51 +0800818 return -EBUSY;
Chunming Zhou049fc522015-07-21 14:36:51 +0800819
Christian König7e52a812015-11-04 15:44:39 +0100820 parser.adev = adev;
821 parser.filp = filp;
822
823 r = amdgpu_cs_parser_init(&parser, data);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400824 if (r) {
Chunming Zhou049fc522015-07-21 14:36:51 +0800825 DRM_ERROR("Failed to initialize parser !\n");
Christian König7e52a812015-11-04 15:44:39 +0100826 amdgpu_cs_parser_fini(&parser, r, false);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400827 r = amdgpu_cs_handle_lockup(adev, r);
828 return r;
829 }
Christian König7e52a812015-11-04 15:44:39 +0100830 r = amdgpu_cs_parser_relocs(&parser);
Christian König26a69802015-08-18 21:09:33 +0200831 if (r == -ENOMEM)
832 DRM_ERROR("Not enough memory for command submission!\n");
833 else if (r && r != -ERESTARTSYS)
834 DRM_ERROR("Failed to process the buffer list %d!\n", r);
835 else if (!r) {
836 reserved_buffers = true;
Christian König7e52a812015-11-04 15:44:39 +0100837 r = amdgpu_cs_ib_fill(adev, &parser);
Christian König26a69802015-08-18 21:09:33 +0200838 }
839
840 if (!r) {
Christian König7e52a812015-11-04 15:44:39 +0100841 r = amdgpu_cs_dependencies(adev, &parser);
Christian König26a69802015-08-18 21:09:33 +0200842 if (r)
843 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
844 }
845
846 if (r)
847 goto out;
848
Christian König7e52a812015-11-04 15:44:39 +0100849 for (i = 0; i < parser.num_ibs; i++)
850 trace_amdgpu_cs(&parser, i);
Christian König26a69802015-08-18 21:09:33 +0200851
Christian König7e52a812015-11-04 15:44:39 +0100852 r = amdgpu_cs_ib_vm_chunk(adev, &parser);
Chunming Zhou4fe63112015-08-18 16:12:15 +0800853 if (r)
854 goto out;
855
Christian König7e52a812015-11-04 15:44:39 +0100856 if (amdgpu_enable_scheduler && parser.num_ibs) {
Christian König7e52a812015-11-04 15:44:39 +0100857 struct amdgpu_ring * ring = parser.ibs->ring;
Christian Könige2840222015-11-05 19:49:48 +0100858 struct amd_sched_fence *fence;
859 struct amdgpu_job *job;
Christian König7e52a812015-11-04 15:44:39 +0100860
Chunming Zhoubb977d32015-08-18 15:16:40 +0800861 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
Dan Carpenter4cfdcd92015-11-04 16:25:09 +0300862 if (!job) {
863 r = -ENOMEM;
864 goto out;
865 }
Christian König7e52a812015-11-04 15:44:39 +0100866
Christian König4f839a22015-09-08 20:22:31 +0200867 job->base.sched = &ring->sched;
Christian König7e52a812015-11-04 15:44:39 +0100868 job->base.s_entity = &parser.ctx->rings[ring->idx].entity;
869 job->adev = parser.adev;
Christian Könige2840222015-11-05 19:49:48 +0100870 job->owner = parser.filp;
871 job->free_job = amdgpu_cs_free_job;
872
Christian König5d827302015-11-13 13:04:50 +0100873 job->ibs = parser.ibs;
874 job->num_ibs = parser.num_ibs;
875 parser.ibs = NULL;
876 parser.num_ibs = 0;
877
Chunming Zhoubb977d32015-08-18 15:16:40 +0800878 if (job->ibs[job->num_ibs - 1].user) {
Christian König7e52a812015-11-04 15:44:39 +0100879 job->uf = parser.uf;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800880 job->ibs[job->num_ibs - 1].user = &job->uf;
Christian König7e52a812015-11-04 15:44:39 +0100881 parser.uf.bo = NULL;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800882 }
883
Christian Könige2840222015-11-05 19:49:48 +0100884 fence = amd_sched_fence_create(job->base.s_entity,
885 parser.filp);
886 if (!fence) {
887 r = -ENOMEM;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800888 amdgpu_cs_free_job(job);
889 kfree(job);
Chunming Zhouf556cb0c2015-08-02 11:18:04 +0800890 goto out;
891 }
Christian Könige2840222015-11-05 19:49:48 +0100892 job->base.s_fence = fence;
Christian König984810f2015-11-14 21:05:35 +0100893 parser.fence = fence_get(&fence->base);
Christian Könige2840222015-11-05 19:49:48 +0100894
895 cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring,
896 &fence->base);
Christian Könige4a58a22015-11-05 17:00:25 +0100897 job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
Christian Königeb98d1c2015-08-20 17:28:36 +0200898
Chunming Zhou7034dec2015-11-11 14:56:00 +0800899 trace_amdgpu_cs_ioctl(job);
Christian Könige2840222015-11-05 19:49:48 +0100900 amd_sched_entity_push_job(&job->base);
901
Christian König984810f2015-11-14 21:05:35 +0100902 } else {
903 struct amdgpu_fence *fence;
Christian Könige2840222015-11-05 19:49:48 +0100904
Christian König984810f2015-11-14 21:05:35 +0100905 r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs,
906 parser.filp);
907 fence = parser.ibs[parser.num_ibs - 1].fence;
908 parser.fence = fence_get(&fence->base);
909 cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400910 }
911
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400912out:
Christian König7e52a812015-11-04 15:44:39 +0100913 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400914 r = amdgpu_cs_handle_lockup(adev, r);
915 return r;
916}
917
918/**
919 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
920 *
921 * @dev: drm device
922 * @data: data from userspace
923 * @filp: file private
924 *
925 * Wait for the command submission identified by handle to finish.
926 */
927int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
928 struct drm_file *filp)
929{
930 union drm_amdgpu_wait_cs *wait = data;
931 struct amdgpu_device *adev = dev->dev_private;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400932 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
Christian König03507c42015-06-19 17:00:19 +0200933 struct amdgpu_ring *ring = NULL;
Jammy Zhou66b3cf22015-05-08 17:29:40 +0800934 struct amdgpu_ctx *ctx;
Christian König21c16bf2015-07-07 17:24:49 +0200935 struct fence *fence;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400936 long r;
937
Christian König21c16bf2015-07-07 17:24:49 +0200938 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
939 wait->in.ring, &ring);
940 if (r)
941 return r;
942
Jammy Zhou66b3cf22015-05-08 17:29:40 +0800943 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
944 if (ctx == NULL)
945 return -EINVAL;
Chunming Zhou4b559c92015-07-21 15:53:04 +0800946
947 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
948 if (IS_ERR(fence))
949 r = PTR_ERR(fence);
950 else if (fence) {
951 r = fence_wait_timeout(fence, true, timeout);
952 fence_put(fence);
953 } else
Christian König21c16bf2015-07-07 17:24:49 +0200954 r = 1;
955
Jammy Zhou66b3cf22015-05-08 17:29:40 +0800956 amdgpu_ctx_put(ctx);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400957 if (r < 0)
958 return r;
959
960 memset(wait, 0, sizeof(*wait));
961 wait->out.status = (r == 0);
962
963 return 0;
964}
965
966/**
967 * amdgpu_cs_find_bo_va - find bo_va for VM address
968 *
969 * @parser: command submission parser context
970 * @addr: VM address
971 * @bo: resulting BO of the mapping found
972 *
973 * Search the buffer objects in the command submission context for a certain
974 * virtual memory address. Returns allocation structure when found, NULL
975 * otherwise.
976 */
977struct amdgpu_bo_va_mapping *
978amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
979 uint64_t addr, struct amdgpu_bo **bo)
980{
981 struct amdgpu_bo_list_entry *reloc;
982 struct amdgpu_bo_va_mapping *mapping;
983
984 addr /= AMDGPU_GPU_PAGE_SIZE;
985
986 list_for_each_entry(reloc, &parser->validated, tv.head) {
987 if (!reloc->bo_va)
988 continue;
989
Christian König7fc11952015-07-30 11:53:42 +0200990 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
991 if (mapping->it.start > addr ||
992 addr > mapping->it.last)
993 continue;
994
995 *bo = reloc->bo_va->bo;
996 return mapping;
997 }
998
999 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001000 if (mapping->it.start > addr ||
1001 addr > mapping->it.last)
1002 continue;
1003
1004 *bo = reloc->bo_va->bo;
1005 return mapping;
1006 }
1007 }
1008
1009 return NULL;
1010}