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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Support for IDE interfaces on PowerMacs.
Bartlomiej Zolnierkiewicz58f189f2008-02-01 23:09:33 +01003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +02008 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/types.h>
26#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
Andrew Morton9e5755b2007-03-03 17:48:54 +010051#include "../ide-timing.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78#endif
79
80} pmac_ide_hwif_t;
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082enum {
83 controller_ohare, /* OHare based */
84 controller_heathrow, /* Heathrow/Paddington */
85 controller_kl_ata3, /* KeyLargo ATA-3 */
86 controller_kl_ata4, /* KeyLargo ATA-4 */
87 controller_un_ata6, /* UniNorth2 ATA-6 */
88 controller_k2_ata6, /* K2 ATA-6 */
89 controller_sh_ata6, /* Shasta ATA-6 */
90};
91
92static const char* model_name[] = {
93 "OHare ATA", /* OHare based */
94 "Heathrow ATA", /* Heathrow/Paddington */
95 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
96 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
97 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
98 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
99 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
100};
101
102/*
103 * Extra registers, both 32-bit little-endian
104 */
105#define IDE_TIMING_CONFIG 0x200
106#define IDE_INTERRUPT 0x300
107
108/* Kauai (U2) ATA has different register setup */
109#define IDE_KAUAI_PIO_CONFIG 0x200
110#define IDE_KAUAI_ULTRA_CONFIG 0x210
111#define IDE_KAUAI_POLL_CONFIG 0x220
112
113/*
114 * Timing configuration register definitions
115 */
116
117/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
118#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
119#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
120#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
121#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
122
123/* 133Mhz cell, found in shasta.
124 * See comments about 100 Mhz Uninorth 2...
125 * Note that PIO_MASK and MDMA_MASK seem to overlap
126 */
127#define TR_133_PIOREG_PIO_MASK 0xff000fff
128#define TR_133_PIOREG_MDMA_MASK 0x00fff800
129#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
130#define TR_133_UDMAREG_UDMA_EN 0x00000001
131
132/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
133 * this one yet, it appears as a pci device (106b/0033) on uninorth
134 * internal PCI bus and it's clock is controlled like gem or fw. It
135 * appears to be an evolution of keylargo ATA4 with a timing register
136 * extended to 2 32bits registers and a similar DBDMA channel. Other
137 * registers seem to exist but I can't tell much about them.
138 *
139 * So far, I'm using pre-calculated tables for this extracted from
140 * the values used by the MacOS X driver.
141 *
142 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
143 * register controls the UDMA timings. At least, it seems bit 0
144 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
145 * cycle time in units of 10ns. Bits 8..15 are used by I don't
146 * know their meaning yet
147 */
148#define TR_100_PIOREG_PIO_MASK 0xff000fff
149#define TR_100_PIOREG_MDMA_MASK 0x00fff000
150#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
151#define TR_100_UDMAREG_UDMA_EN 0x00000001
152
153
154/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
155 * 40 connector cable and to 4 on 80 connector one.
156 * Clock unit is 15ns (66Mhz)
157 *
158 * 3 Values can be programmed:
159 * - Write data setup, which appears to match the cycle time. They
160 * also call it DIOW setup.
161 * - Ready to pause time (from spec)
162 * - Address setup. That one is weird. I don't see where exactly
163 * it fits in UDMA cycles, I got it's name from an obscure piece
164 * of commented out code in Darwin. They leave it to 0, we do as
165 * well, despite a comment that would lead to think it has a
166 * min value of 45ns.
167 * Apple also add 60ns to the write data setup (or cycle time ?) on
168 * reads.
169 */
170#define TR_66_UDMA_MASK 0xfff00000
171#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
172#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
173#define TR_66_UDMA_ADDRSETUP_SHIFT 29
174#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
175#define TR_66_UDMA_RDY2PAUS_SHIFT 25
176#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
177#define TR_66_UDMA_WRDATASETUP_SHIFT 21
178#define TR_66_MDMA_MASK 0x000ffc00
179#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
180#define TR_66_MDMA_RECOVERY_SHIFT 15
181#define TR_66_MDMA_ACCESS_MASK 0x00007c00
182#define TR_66_MDMA_ACCESS_SHIFT 10
183#define TR_66_PIO_MASK 0x000003ff
184#define TR_66_PIO_RECOVERY_MASK 0x000003e0
185#define TR_66_PIO_RECOVERY_SHIFT 5
186#define TR_66_PIO_ACCESS_MASK 0x0000001f
187#define TR_66_PIO_ACCESS_SHIFT 0
188
189/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
190 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
191 *
192 * The access time and recovery time can be programmed. Some older
193 * Darwin code base limit OHare to 150ns cycle time. I decided to do
194 * the same here fore safety against broken old hardware ;)
195 * The HalfTick bit, when set, adds half a clock (15ns) to the access
196 * time and removes one from recovery. It's not supported on KeyLargo
197 * implementation afaik. The E bit appears to be set for PIO mode 0 and
198 * is used to reach long timings used in this mode.
199 */
200#define TR_33_MDMA_MASK 0x003ff800
201#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
202#define TR_33_MDMA_RECOVERY_SHIFT 16
203#define TR_33_MDMA_ACCESS_MASK 0x0000f800
204#define TR_33_MDMA_ACCESS_SHIFT 11
205#define TR_33_MDMA_HALFTICK 0x00200000
206#define TR_33_PIO_MASK 0x000007ff
207#define TR_33_PIO_E 0x00000400
208#define TR_33_PIO_RECOVERY_MASK 0x000003e0
209#define TR_33_PIO_RECOVERY_SHIFT 5
210#define TR_33_PIO_ACCESS_MASK 0x0000001f
211#define TR_33_PIO_ACCESS_SHIFT 0
212
213/*
214 * Interrupt register definitions
215 */
216#define IDE_INTR_DMA 0x80000000
217#define IDE_INTR_DEVICE 0x40000000
218
219/*
220 * FCR Register on Kauai. Not sure what bit 0x4 is ...
221 */
222#define KAUAI_FCR_UATA_MAGIC 0x00000004
223#define KAUAI_FCR_UATA_RESET_N 0x00000002
224#define KAUAI_FCR_UATA_ENABLE 0x00000001
225
226#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
227
228/* Rounded Multiword DMA timings
229 *
230 * I gave up finding a generic formula for all controller
231 * types and instead, built tables based on timing values
232 * used by Apple in Darwin's implementation.
233 */
234struct mdma_timings_t {
235 int accessTime;
236 int recoveryTime;
237 int cycleTime;
238};
239
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500240struct mdma_timings_t mdma_timings_33[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241{
242 { 240, 240, 480 },
243 { 180, 180, 360 },
244 { 135, 135, 270 },
245 { 120, 120, 240 },
246 { 105, 105, 210 },
247 { 90, 90, 180 },
248 { 75, 75, 150 },
249 { 75, 45, 120 },
250 { 0, 0, 0 }
251};
252
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500253struct mdma_timings_t mdma_timings_33k[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254{
255 { 240, 240, 480 },
256 { 180, 180, 360 },
257 { 150, 150, 300 },
258 { 120, 120, 240 },
259 { 90, 120, 210 },
260 { 90, 90, 180 },
261 { 90, 60, 150 },
262 { 90, 30, 120 },
263 { 0, 0, 0 }
264};
265
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500266struct mdma_timings_t mdma_timings_66[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267{
268 { 240, 240, 480 },
269 { 180, 180, 360 },
270 { 135, 135, 270 },
271 { 120, 120, 240 },
272 { 105, 105, 210 },
273 { 90, 90, 180 },
274 { 90, 75, 165 },
275 { 75, 45, 120 },
276 { 0, 0, 0 }
277};
278
279/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
280struct {
281 int addrSetup; /* ??? */
282 int rdy2pause;
283 int wrDataSetup;
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500284} kl66_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285{
286 { 0, 180, 120 }, /* Mode 0 */
287 { 0, 150, 90 }, /* 1 */
288 { 0, 120, 60 }, /* 2 */
289 { 0, 90, 45 }, /* 3 */
290 { 0, 90, 30 } /* 4 */
291};
292
293/* UniNorth 2 ATA/100 timings */
294struct kauai_timing {
295 int cycle_time;
296 u32 timing_reg;
297};
298
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500299static struct kauai_timing kauai_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300{
301 { 930 , 0x08000fff },
302 { 600 , 0x08000a92 },
303 { 383 , 0x0800060f },
304 { 360 , 0x08000492 },
305 { 330 , 0x0800048f },
306 { 300 , 0x080003cf },
307 { 270 , 0x080003cc },
308 { 240 , 0x0800038b },
309 { 239 , 0x0800030c },
310 { 180 , 0x05000249 },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200311 { 120 , 0x04000148 },
312 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313};
314
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500315static struct kauai_timing kauai_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316{
317 { 1260 , 0x00fff000 },
318 { 480 , 0x00618000 },
319 { 360 , 0x00492000 },
320 { 270 , 0x0038e000 },
321 { 240 , 0x0030c000 },
322 { 210 , 0x002cb000 },
323 { 180 , 0x00249000 },
324 { 150 , 0x00209000 },
325 { 120 , 0x00148000 },
326 { 0 , 0 },
327};
328
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500329static struct kauai_timing kauai_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330{
331 { 120 , 0x000070c0 },
332 { 90 , 0x00005d80 },
333 { 60 , 0x00004a60 },
334 { 45 , 0x00003a50 },
335 { 30 , 0x00002a30 },
336 { 20 , 0x00002921 },
337 { 0 , 0 },
338};
339
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500340static struct kauai_timing shasta_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341{
342 { 930 , 0x08000fff },
343 { 600 , 0x0A000c97 },
344 { 383 , 0x07000712 },
345 { 360 , 0x040003cd },
346 { 330 , 0x040003cd },
347 { 300 , 0x040003cd },
348 { 270 , 0x040003cd },
349 { 240 , 0x040003cd },
350 { 239 , 0x040003cd },
351 { 180 , 0x0400028b },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200352 { 120 , 0x0400010a },
353 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354};
355
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500356static struct kauai_timing shasta_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357{
358 { 1260 , 0x00fff000 },
359 { 480 , 0x00820800 },
360 { 360 , 0x00820800 },
361 { 270 , 0x00820800 },
362 { 240 , 0x00820800 },
363 { 210 , 0x00820800 },
364 { 180 , 0x00820800 },
365 { 150 , 0x0028b000 },
366 { 120 , 0x001ca000 },
367 { 0 , 0 },
368};
369
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500370static struct kauai_timing shasta_udma133_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371{
372 { 120 , 0x00035901, },
373 { 90 , 0x000348b1, },
374 { 60 , 0x00033881, },
375 { 45 , 0x00033861, },
376 { 30 , 0x00033841, },
377 { 20 , 0x00033031, },
378 { 15 , 0x00033021, },
379 { 0 , 0 },
380};
381
382
383static inline u32
384kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
385{
386 int i;
387
388 for (i=0; table[i].cycle_time; i++)
389 if (cycle_time > table[i+1].cycle_time)
390 return table[i].timing_reg;
Bartlomiej Zolnierkiewicz90a87ea2007-10-13 17:47:48 +0200391 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 return 0;
393}
394
395/* allow up to 256 DBDMA commands per xfer */
396#define MAX_DCMDS 256
397
398/*
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
401 *
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
409 */
410#define IDE_WAKEUP_DELAY (1*HZ)
411
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +0200412static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414static void pmac_ide_selectproc(ide_drive_t *drive);
415static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
416
417#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
418
Bartlomiej Zolnierkiewicz23579a22008-04-18 00:46:26 +0200419#define PMAC_IDE_REG(x) \
Bartlomiej Zolnierkiewicz4c3032d2008-04-27 15:38:32 +0200420 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422/*
423 * Apply the timings of the proper unit (master/slave) to the shared
424 * timing register when selecting that unit. This version is for
425 * ASICs with a single timing register
426 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500427static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428pmac_ide_selectproc(ide_drive_t *drive)
429{
430 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
431
432 if (pmif == NULL)
433 return;
434
435 if (drive->select.b.unit & 0x01)
436 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
437 else
438 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
439 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
440}
441
442/*
443 * Apply the timings of the proper unit (master/slave) to the shared
444 * timing register when selecting that unit. This version is for
445 * ASICs with a dual timing register (Kauai)
446 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500447static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448pmac_ide_kauai_selectproc(ide_drive_t *drive)
449{
450 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
451
452 if (pmif == NULL)
453 return;
454
455 if (drive->select.b.unit & 0x01) {
456 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
457 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
458 } else {
459 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
460 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
461 }
462 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
463}
464
465/*
466 * Force an update of controller timing values for a given drive
467 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500468static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469pmac_ide_do_update_timings(ide_drive_t *drive)
470{
471 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
472
473 if (pmif == NULL)
474 return;
475
476 if (pmif->kind == controller_sh_ata6 ||
477 pmif->kind == controller_un_ata6 ||
478 pmif->kind == controller_k2_ata6)
479 pmac_ide_kauai_selectproc(drive);
480 else
481 pmac_ide_selectproc(drive);
482}
483
484static void
485pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
486{
487 u32 tmp;
488
489 writeb(value, (void __iomem *) port);
490 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
491}
492
493/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
495 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500496static void
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200497pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498{
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200499 u32 *timings, t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 unsigned accessTicks, recTicks;
501 unsigned accessTime, recTime;
502 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200503 unsigned int cycle_time;
504
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 if (pmif == NULL)
506 return;
507
508 /* which drive is it ? */
509 timings = &pmif->timings[drive->select.b.unit & 0x01];
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200510 t = *timings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200512 cycle_time = ide_pio_cycle_time(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513
514 switch (pmif->kind) {
515 case controller_sh_ata6: {
516 /* 133Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200517 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200518 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 break;
520 }
521 case controller_un_ata6:
522 case controller_k2_ata6: {
523 /* 100Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200524 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200525 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 break;
527 }
528 case controller_kl_ata4:
529 /* 66Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200530 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 - ide_pio_timings[pio].setup_time;
532 recTime = max(recTime, 150U);
533 accessTime = ide_pio_timings[pio].active_time;
534 accessTime = max(accessTime, 150U);
535 accessTicks = SYSCLK_TICKS_66(accessTime);
536 accessTicks = min(accessTicks, 0x1fU);
537 recTicks = SYSCLK_TICKS_66(recTime);
538 recTicks = min(recTicks, 0x1fU);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200539 t = (t & ~TR_66_PIO_MASK) |
540 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
541 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 break;
543 default: {
544 /* 33Mhz cell */
545 int ebit = 0;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200546 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 - ide_pio_timings[pio].setup_time;
548 recTime = max(recTime, 150U);
549 accessTime = ide_pio_timings[pio].active_time;
550 accessTime = max(accessTime, 150U);
551 accessTicks = SYSCLK_TICKS(accessTime);
552 accessTicks = min(accessTicks, 0x1fU);
553 accessTicks = max(accessTicks, 4U);
554 recTicks = SYSCLK_TICKS(recTime);
555 recTicks = min(recTicks, 0x1fU);
556 recTicks = max(recTicks, 5U) - 4;
557 if (recTicks > 9) {
558 recTicks--; /* guess, but it's only for PIO0, so... */
559 ebit = 1;
560 }
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200561 t = (t & ~TR_33_PIO_MASK) |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
563 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
564 if (ebit)
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200565 t |= TR_33_PIO_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566 break;
567 }
568 }
569
570#ifdef IDE_PMAC_DEBUG
571 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
572 drive->name, pio, *timings);
573#endif
574
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200575 *timings = t;
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200576 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577}
578
579#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
580
581/*
582 * Calculate KeyLargo ATA/66 UDMA timings
583 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500584static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585set_timings_udma_ata4(u32 *timings, u8 speed)
586{
587 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
588
589 if (speed > XFER_UDMA_4)
590 return 1;
591
592 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
593 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
594 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
595
596 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
597 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
598 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
599 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
600 TR_66_UDMA_EN;
601#ifdef IDE_PMAC_DEBUG
602 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
603 speed & 0xf, *timings);
604#endif
605
606 return 0;
607}
608
609/*
610 * Calculate Kauai ATA/100 UDMA timings
611 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500612static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
614{
615 struct ide_timing *t = ide_timing_find_mode(speed);
616 u32 tr;
617
618 if (speed > XFER_UDMA_5 || t == NULL)
619 return 1;
620 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
622 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
623
624 return 0;
625}
626
627/*
628 * Calculate Shasta ATA/133 UDMA timings
629 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500630static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
632{
633 struct ide_timing *t = ide_timing_find_mode(speed);
634 u32 tr;
635
636 if (speed > XFER_UDMA_6 || t == NULL)
637 return 1;
638 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
640 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
641
642 return 0;
643}
644
645/*
646 * Calculate MDMA timings for all cells
647 */
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200648static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200650 u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651{
652 int cycleTime, accessTime = 0, recTime = 0;
653 unsigned accessTicks, recTicks;
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200654 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 struct mdma_timings_t* tm = NULL;
656 int i;
657
658 /* Get default cycle time for mode */
659 switch(speed & 0xf) {
660 case 0: cycleTime = 480; break;
661 case 1: cycleTime = 150; break;
662 case 2: cycleTime = 120; break;
663 default:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200664 BUG();
665 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 }
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200667
668 /* Check if drive provides explicit DMA cycle time */
669 if ((id->field_valid & 2) && id->eide_dma_time)
670 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
671
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 /* OHare limits according to some old Apple sources */
673 if ((intf_type == controller_ohare) && (cycleTime < 150))
674 cycleTime = 150;
675 /* Get the proper timing array for this controller */
676 switch(intf_type) {
677 case controller_sh_ata6:
678 case controller_un_ata6:
679 case controller_k2_ata6:
680 break;
681 case controller_kl_ata4:
682 tm = mdma_timings_66;
683 break;
684 case controller_kl_ata3:
685 tm = mdma_timings_33k;
686 break;
687 default:
688 tm = mdma_timings_33;
689 break;
690 }
691 if (tm != NULL) {
692 /* Lookup matching access & recovery times */
693 i = -1;
694 for (;;) {
695 if (tm[i+1].cycleTime < cycleTime)
696 break;
697 i++;
698 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 cycleTime = tm[i].cycleTime;
700 accessTime = tm[i].accessTime;
701 recTime = tm[i].recoveryTime;
702
703#ifdef IDE_PMAC_DEBUG
704 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
705 drive->name, cycleTime, accessTime, recTime);
706#endif
707 }
708 switch(intf_type) {
709 case controller_sh_ata6: {
710 /* 133Mhz cell */
711 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
713 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
714 }
715 case controller_un_ata6:
716 case controller_k2_ata6: {
717 /* 100Mhz cell */
718 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
720 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
721 }
722 break;
723 case controller_kl_ata4:
724 /* 66Mhz cell */
725 accessTicks = SYSCLK_TICKS_66(accessTime);
726 accessTicks = min(accessTicks, 0x1fU);
727 accessTicks = max(accessTicks, 0x1U);
728 recTicks = SYSCLK_TICKS_66(recTime);
729 recTicks = min(recTicks, 0x1fU);
730 recTicks = max(recTicks, 0x3U);
731 /* Clear out mdma bits and disable udma */
732 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
733 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
734 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
735 break;
736 case controller_kl_ata3:
737 /* 33Mhz cell on KeyLargo */
738 accessTicks = SYSCLK_TICKS(accessTime);
739 accessTicks = max(accessTicks, 1U);
740 accessTicks = min(accessTicks, 0x1fU);
741 accessTime = accessTicks * IDE_SYSCLK_NS;
742 recTicks = SYSCLK_TICKS(recTime);
743 recTicks = max(recTicks, 1U);
744 recTicks = min(recTicks, 0x1fU);
745 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
746 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
747 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
748 break;
749 default: {
750 /* 33Mhz cell on others */
751 int halfTick = 0;
752 int origAccessTime = accessTime;
753 int origRecTime = recTime;
754
755 accessTicks = SYSCLK_TICKS(accessTime);
756 accessTicks = max(accessTicks, 1U);
757 accessTicks = min(accessTicks, 0x1fU);
758 accessTime = accessTicks * IDE_SYSCLK_NS;
759 recTicks = SYSCLK_TICKS(recTime);
760 recTicks = max(recTicks, 2U) - 1;
761 recTicks = min(recTicks, 0x1fU);
762 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
763 if ((accessTicks > 1) &&
764 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
765 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
766 halfTick = 1;
767 accessTicks--;
768 }
769 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
770 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
771 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
772 if (halfTick)
773 *timings |= TR_33_MDMA_HALFTICK;
774 }
775 }
776#ifdef IDE_PMAC_DEBUG
777 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
778 drive->name, speed & 0xf, *timings);
779#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780}
781#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
782
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200783static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784{
785 int unit = (drive->select.b.unit & 0x01);
786 int ret = 0;
787 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200788 u32 *timings, *timings2, tl[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 timings = &pmif->timings[unit];
791 timings2 = &pmif->timings[unit+2];
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200792
793 /* Copy timings to local image */
794 tl[0] = *timings;
795 tl[1] = *timings2;
796
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +0100798 if (speed >= XFER_UDMA_0) {
799 if (pmif->kind == controller_kl_ata4)
800 ret = set_timings_udma_ata4(&tl[0], speed);
801 else if (pmif->kind == controller_un_ata6
802 || pmif->kind == controller_k2_ata6)
803 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
804 else if (pmif->kind == controller_sh_ata6)
805 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
806 else
807 ret = -1;
808 } else
809 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 if (ret)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200812 return;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200813
814 /* Apply timings to controller */
815 *timings = tl[0];
816 *timings2 = tl[1];
817
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819}
820
821/*
822 * Blast some well known "safe" values to the timing registers at init or
823 * wakeup from sleep time, before we do real calculation
824 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500825static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826sanitize_timings(pmac_ide_hwif_t *pmif)
827{
828 unsigned int value, value2 = 0;
829
830 switch(pmif->kind) {
831 case controller_sh_ata6:
832 value = 0x0a820c97;
833 value2 = 0x00033031;
834 break;
835 case controller_un_ata6:
836 case controller_k2_ata6:
837 value = 0x08618a92;
838 value2 = 0x00002921;
839 break;
840 case controller_kl_ata4:
841 value = 0x0008438c;
842 break;
843 case controller_kl_ata3:
844 value = 0x00084526;
845 break;
846 case controller_heathrow:
847 case controller_ohare:
848 default:
849 value = 0x00074526;
850 break;
851 }
852 pmif->timings[0] = pmif->timings[1] = value;
853 pmif->timings[2] = pmif->timings[3] = value2;
854}
855
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856/* Suspend call back, should be called after the child devices
857 * have actually been suspended
858 */
859static int
860pmac_ide_do_suspend(ide_hwif_t *hwif)
861{
862 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
863
864 /* We clear the timings */
865 pmif->timings[0] = 0;
866 pmif->timings[1] = 0;
867
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700868 disable_irq(pmif->irq);
869
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 /* The media bay will handle itself just fine */
871 if (pmif->mediabay)
872 return 0;
873
874 /* Kauai has bus control FCRs directly here */
875 if (pmif->kauai_fcr) {
876 u32 fcr = readl(pmif->kauai_fcr);
877 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
878 writel(fcr, pmif->kauai_fcr);
879 }
880
881 /* Disable the bus on older machines and the cell on kauai */
882 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
883 0);
884
885 return 0;
886}
887
888/* Resume call back, should be called before the child devices
889 * are resumed
890 */
891static int
892pmac_ide_do_resume(ide_hwif_t *hwif)
893{
894 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
895
896 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
897 if (!pmif->mediabay) {
898 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
899 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
900 msleep(10);
901 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902
903 /* Kauai has it different */
904 if (pmif->kauai_fcr) {
905 u32 fcr = readl(pmif->kauai_fcr);
906 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
907 writel(fcr, pmif->kauai_fcr);
908 }
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700909
910 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911 }
912
913 /* Sanitize drive timings */
914 sanitize_timings(pmif);
915
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700916 enable_irq(pmif->irq);
917
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 return 0;
919}
920
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200921static const struct ide_port_ops pmac_ide_ata6_port_ops = {
922 .set_pio_mode = pmac_ide_set_pio_mode,
923 .set_dma_mode = pmac_ide_set_dma_mode,
924 .selectproc = pmac_ide_kauai_selectproc,
925};
926
927static const struct ide_port_ops pmac_ide_port_ops = {
928 .set_pio_mode = pmac_ide_set_pio_mode,
929 .set_dma_mode = pmac_ide_set_dma_mode,
930 .selectproc = pmac_ide_selectproc,
931};
932
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200933static const struct ide_dma_ops pmac_dma_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200934
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100935static const struct ide_port_info pmac_port_info = {
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +0200936 .init_dma = pmac_ide_init_dma,
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100937 .chipset = ide_pmac,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200938#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
939 .dma_ops = &pmac_dma_ops,
940#endif
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200941 .port_ops = &pmac_ide_port_ops,
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100942 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100943 IDE_HFLAG_POST_SET_MODE |
Bartlomiej Zolnierkiewiczc5dd43e2008-04-28 23:44:37 +0200944 IDE_HFLAG_MMIO |
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100945 IDE_HFLAG_UNMASK_IRQS,
946 .pio_mask = ATA_PIO4,
947 .mwdma_mask = ATA_MWDMA2,
948};
949
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950/*
951 * Setup, register & probe an IDE channel driven by this driver, this is
952 * called by one of the 2 probe functions (macio or PCI). Note that a channel
953 * that ends up beeing free of any device is not kept around by this driver
954 * (it is kept in 2.4). This introduce an interface numbering change on some
955 * rare machines unfortunately, but it's better this way.
956 */
Adrian Bunk468e4682008-02-01 23:09:16 +0100957static int __devinit
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +0100958pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959{
960 struct device_node *np = pmif->node;
Jeremy Kerr018a3d12006-07-12 15:40:29 +1000961 const int *bidp;
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +0200962 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100963 struct ide_port_info d = pmac_port_info;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964
965 pmif->cable_80 = 0;
966 pmif->broken_dma = pmif->broken_dma_warn = 0;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100967 if (of_device_is_compatible(np, "shasta-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968 pmif->kind = controller_sh_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200969 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100970 d.udma_mask = ATA_UDMA6;
971 } else if (of_device_is_compatible(np, "kauai-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972 pmif->kind = controller_un_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200973 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100974 d.udma_mask = ATA_UDMA5;
975 } else if (of_device_is_compatible(np, "K2-UATA")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 pmif->kind = controller_k2_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200977 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100978 d.udma_mask = ATA_UDMA5;
979 } else if (of_device_is_compatible(np, "keylargo-ata")) {
980 if (strcmp(np->name, "ata-4") == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 pmif->kind = controller_kl_ata4;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100982 d.udma_mask = ATA_UDMA4;
983 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984 pmif->kind = controller_kl_ata3;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100985 } else if (of_device_is_compatible(np, "heathrow-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 pmif->kind = controller_heathrow;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100987 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 pmif->kind = controller_ohare;
989 pmif->broken_dma = 1;
990 }
991
Stephen Rothwell40cd3a42007-05-01 13:54:02 +1000992 bidp = of_get_property(np, "AAPL,bus-id", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 pmif->aapl_bus_id = bidp ? *bidp : 0;
994
995 /* Get cable type from device-tree */
996 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
997 || pmif->kind == controller_k2_ata6
998 || pmif->kind == controller_sh_ata6) {
Stephen Rothwell40cd3a42007-05-01 13:54:02 +1000999 const char* cable = of_get_property(np, "cable-type", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 if (cable && !strncmp(cable, "80-", 3))
1001 pmif->cable_80 = 1;
1002 }
1003 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1004 * they have a 80 conductor cable, this seem to be always the case unless
1005 * the user mucked around
1006 */
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001007 if (of_device_is_compatible(np, "K2-UATA") ||
1008 of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 pmif->cable_80 = 1;
1010
1011 /* On Kauai-type controllers, we make sure the FCR is correct */
1012 if (pmif->kauai_fcr)
1013 writel(KAUAI_FCR_UATA_MAGIC |
1014 KAUAI_FCR_UATA_RESET_N |
1015 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1016
1017 pmif->mediabay = 0;
1018
1019 /* Make sure we have sane timings */
1020 sanitize_timings(pmif);
1021
1022#ifndef CONFIG_PPC64
1023 /* XXX FIXME: Media bay stuff need re-organizing */
1024 if (np->parent && np->parent->name
1025 && strcasecmp(np->parent->name, "media-bay") == 0) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001026#ifdef CONFIG_PMAC_MEDIABAY
Bartlomiej Zolnierkiewicz2dde7862008-04-18 00:46:23 +02001027 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
1028 hwif);
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001029#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 pmif->mediabay = 1;
1031 if (!bidp)
1032 pmif->aapl_bus_id = 1;
1033 } else if (pmif->kind == controller_ohare) {
1034 /* The code below is having trouble on some ohare machines
1035 * (timing related ?). Until I can put my hand on one of these
1036 * units, I keep the old way
1037 */
1038 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1039 } else
1040#endif
1041 {
1042 /* This is necessary to enable IDE when net-booting */
1043 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1044 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1045 msleep(10);
1046 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1047 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1048 }
1049
1050 /* Setup MMIO ops */
1051 default_hwif_mmiops(hwif);
1052 hwif->OUTBSYNC = pmac_outbsync;
1053
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054 hwif->hwif_data = pmif;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001055 ide_init_port_hw(hwif, hw);
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +02001056 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1059 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1060 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
Bartlomiej Zolnierkiewicze53cd452008-04-26 22:25:16 +02001061
1062 if (pmif->mediabay) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001063#ifdef CONFIG_PMAC_MEDIABAY
Bartlomiej Zolnierkiewicze53cd452008-04-26 22:25:16 +02001064 if (check_media_bay_by_base(pmif->regbase, MB_CD)) {
1065#else
1066 if (1) {
1067#endif
1068 hwif->drives[0].noprobe = 1;
1069 hwif->drives[1].noprobe = 1;
1070 }
1071 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001074 if (pmif->cable_80 == 0)
1075 d.udma_mask &= ATA_UDMA2;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001076#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001078 idx[0] = hwif->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001080 ide_device_add(idx, &d);
Bartlomiej Zolnierkiewicz5cbf79c2007-05-10 00:01:11 +02001081
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 return 0;
1083}
1084
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001085static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1086{
1087 int i;
1088
1089 for (i = 0; i < 8; ++i)
Bartlomiej Zolnierkiewicz4c3032d2008-04-27 15:38:32 +02001090 hw->io_ports_array[i] = base + i * 0x10;
1091
1092 hw->io_ports.ctl_addr = base + 0x160;
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001093}
1094
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095/*
1096 * Attach to a macio probed interface
1097 */
1098static int __devinit
Jeff Mahoney5e655772005-07-06 15:44:41 -04001099pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100{
1101 void __iomem *base;
1102 unsigned long regbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 ide_hwif_t *hwif;
1104 pmac_ide_hwif_t *pmif;
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001105 int irq, rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001106 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001108 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1109 if (pmif == NULL)
1110 return -ENOMEM;
1111
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001112 hwif = ide_find_port();
1113 if (hwif == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1115 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001116 rc = -ENODEV;
1117 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 }
1119
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +11001120 if (macio_resource_count(mdev) == 0) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001121 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1122 mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001123 rc = -ENXIO;
1124 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125 }
1126
1127 /* Request memory resource for IO ports */
1128 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001129 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1130 "%s!\n", mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001131 rc = -EBUSY;
1132 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133 }
1134
1135 /* XXX This is bogus. Should be fixed in the registry by checking
1136 * the kind of host interrupt controller, a bit like gatwick
1137 * fixes in irq.c. That works well enough for the single case
1138 * where that happens though...
1139 */
1140 if (macio_irq_count(mdev) == 0) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001141 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1142 "13\n", mdev->ofdev.node->full_name);
Benjamin Herrenschmidt69917c22006-09-22 12:56:30 +10001143 irq = irq_create_mapping(NULL, 13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144 } else
1145 irq = macio_irq(mdev, 0);
1146
1147 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1148 regbase = (unsigned long) base;
1149
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001150 hwif->dev = &mdev->bus->pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151
1152 pmif->mdev = mdev;
1153 pmif->node = mdev->ofdev.node;
1154 pmif->regbase = regbase;
1155 pmif->irq = irq;
1156 pmif->kauai_fcr = NULL;
1157#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1158 if (macio_resource_count(mdev) >= 2) {
1159 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001160 printk(KERN_WARNING "ide-pmac: can't request DMA "
1161 "resource for %s!\n",
1162 mdev->ofdev.node->full_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 else
1164 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1165 } else
1166 pmif->dma_regs = NULL;
1167#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1168 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1169
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001170 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001171 pmac_ide_init_ports(&hw, pmif->regbase);
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001172 hw.irq = irq;
1173 hw.dev = &mdev->ofdev.dev;
1174
1175 rc = pmac_ide_setup_device(pmif, hwif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 if (rc != 0) {
1177 /* The inteface is released to the common IDE layer */
1178 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1179 iounmap(base);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001180 if (pmif->dma_regs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 iounmap(pmif->dma_regs);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001182 macio_release_resource(mdev, 1);
1183 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184 macio_release_resource(mdev, 0);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001185 kfree(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186 }
1187
1188 return rc;
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001189
1190out_free_pmif:
1191 kfree(pmif);
1192 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193}
1194
1195static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001196pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197{
1198 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1199 int rc = 0;
1200
David Brownell8b4b8a22006-08-14 23:11:03 -07001201 if (mesg.event != mdev->ofdev.dev.power.power_state.event
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001202 && (mesg.event & PM_EVENT_SLEEP)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203 rc = pmac_ide_do_suspend(hwif);
1204 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001205 mdev->ofdev.dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206 }
1207
1208 return rc;
1209}
1210
1211static int
1212pmac_ide_macio_resume(struct macio_dev *mdev)
1213{
1214 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1215 int rc = 0;
1216
Pavel Machekca078ba2005-09-03 15:56:57 -07001217 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 rc = pmac_ide_do_resume(hwif);
1219 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001220 mdev->ofdev.dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 }
1222
1223 return rc;
1224}
1225
1226/*
1227 * Attach to a PCI probed interface
1228 */
1229static int __devinit
1230pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1231{
1232 ide_hwif_t *hwif;
1233 struct device_node *np;
1234 pmac_ide_hwif_t *pmif;
1235 void __iomem *base;
1236 unsigned long rbase, rlen;
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001237 int rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001238 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239
1240 np = pci_device_to_OF_node(pdev);
1241 if (np == NULL) {
1242 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1243 return -ENODEV;
1244 }
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001245
1246 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1247 if (pmif == NULL)
1248 return -ENOMEM;
1249
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001250 hwif = ide_find_port();
1251 if (hwif == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1253 printk(KERN_ERR " %s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001254 rc = -ENODEV;
1255 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256 }
1257
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 if (pci_enable_device(pdev)) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001259 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1260 "%s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001261 rc = -ENXIO;
1262 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001263 }
1264 pci_set_master(pdev);
1265
1266 if (pci_request_regions(pdev, "Kauai ATA")) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001267 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1268 "%s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001269 rc = -ENXIO;
1270 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271 }
1272
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001273 hwif->dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001274 pmif->mdev = NULL;
1275 pmif->node = np;
1276
1277 rbase = pci_resource_start(pdev, 0);
1278 rlen = pci_resource_len(pdev, 0);
1279
1280 base = ioremap(rbase, rlen);
1281 pmif->regbase = (unsigned long) base + 0x2000;
1282#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1283 pmif->dma_regs = base + 0x1000;
1284#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1285 pmif->kauai_fcr = base;
1286 pmif->irq = pdev->irq;
1287
1288 pci_set_drvdata(pdev, hwif);
1289
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001290 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001291 pmac_ide_init_ports(&hw, pmif->regbase);
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001292 hw.irq = pdev->irq;
1293 hw.dev = &pdev->dev;
1294
1295 rc = pmac_ide_setup_device(pmif, hwif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296 if (rc != 0) {
1297 /* The inteface is released to the common IDE layer */
1298 pci_set_drvdata(pdev, NULL);
1299 iounmap(base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 pci_release_regions(pdev);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001301 kfree(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 }
1303
1304 return rc;
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001305
1306out_free_pmif:
1307 kfree(pmif);
1308 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309}
1310
1311static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001312pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313{
1314 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1315 int rc = 0;
1316
David Brownell8b4b8a22006-08-14 23:11:03 -07001317 if (mesg.event != pdev->dev.power.power_state.event
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001318 && (mesg.event & PM_EVENT_SLEEP)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 rc = pmac_ide_do_suspend(hwif);
1320 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001321 pdev->dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 }
1323
1324 return rc;
1325}
1326
1327static int
1328pmac_ide_pci_resume(struct pci_dev *pdev)
1329{
1330 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1331 int rc = 0;
1332
Pavel Machekca078ba2005-09-03 15:56:57 -07001333 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334 rc = pmac_ide_do_resume(hwif);
1335 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001336 pdev->dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 }
1338
1339 return rc;
1340}
1341
Jeff Mahoney5e655772005-07-06 15:44:41 -04001342static struct of_device_id pmac_ide_macio_match[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343{
1344 {
1345 .name = "IDE",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346 },
1347 {
1348 .name = "ATA",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349 },
1350 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 .type = "ide",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 },
1353 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354 .type = "ata",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 },
1356 {},
1357};
1358
1359static struct macio_driver pmac_ide_macio_driver =
1360{
1361 .name = "ide-pmac",
1362 .match_table = pmac_ide_macio_match,
1363 .probe = pmac_ide_macio_attach,
1364 .suspend = pmac_ide_macio_suspend,
1365 .resume = pmac_ide_macio_resume,
1366};
1367
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001368static const struct pci_device_id pmac_ide_pci_match[] = {
1369 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1370 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1371 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1372 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1373 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
Benjamin Herrenschmidt71e4eda2007-10-06 18:52:27 +10001374 {},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001375};
1376
1377static struct pci_driver pmac_ide_pci_driver = {
1378 .name = "ide-pmac",
1379 .id_table = pmac_ide_pci_match,
1380 .probe = pmac_ide_pci_attach,
1381 .suspend = pmac_ide_pci_suspend,
1382 .resume = pmac_ide_pci_resume,
1383};
1384MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1385
Andrew Morton9e5755b2007-03-03 17:48:54 +01001386int __init pmac_ide_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001387{
Andrew Morton9e5755b2007-03-03 17:48:54 +01001388 int error;
1389
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001390 if (!machine_is(powermac))
Andrew Morton9e5755b2007-03-03 17:48:54 +01001391 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392
1393#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
Andrew Morton9e5755b2007-03-03 17:48:54 +01001394 error = pci_register_driver(&pmac_ide_pci_driver);
1395 if (error)
1396 goto out;
1397 error = macio_register_driver(&pmac_ide_macio_driver);
1398 if (error) {
1399 pci_unregister_driver(&pmac_ide_pci_driver);
1400 goto out;
1401 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402#else
Andrew Morton9e5755b2007-03-03 17:48:54 +01001403 error = macio_register_driver(&pmac_ide_macio_driver);
1404 if (error)
1405 goto out;
1406 error = pci_register_driver(&pmac_ide_pci_driver);
1407 if (error) {
1408 macio_unregister_driver(&pmac_ide_macio_driver);
1409 goto out;
1410 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001411#endif
Andrew Morton9e5755b2007-03-03 17:48:54 +01001412out:
1413 return error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414}
1415
1416#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1417
1418/*
1419 * pmac_ide_build_dmatable builds the DBDMA command list
1420 * for a transfer and sets the DBDMA channel to point to it.
1421 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001422static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1424{
1425 struct dbdma_cmd *table;
1426 int i, count = 0;
1427 ide_hwif_t *hwif = HWIF(drive);
1428 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1429 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1430 struct scatterlist *sg;
1431 int wr = (rq_data_dir(rq) == WRITE);
1432
1433 /* DMA table is already aligned */
1434 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1435
1436 /* Make sure DMA controller is stopped (necessary ?) */
1437 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1438 while (readl(&dma->status) & RUN)
1439 udelay(1);
1440
1441 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1442
1443 if (!i)
1444 return 0;
1445
1446 /* Build DBDMA commands list */
1447 sg = hwif->sg_table;
1448 while (i && sg_dma_len(sg)) {
1449 u32 cur_addr;
1450 u32 cur_len;
1451
1452 cur_addr = sg_dma_address(sg);
1453 cur_len = sg_dma_len(sg);
1454
1455 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1456 if (pmif->broken_dma_warn == 0) {
Joe Perchesaca38a52007-11-27 21:35:55 +01001457 printk(KERN_WARNING "%s: DMA on non aligned address, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458 "switching to PIO on Ohare chipset\n", drive->name);
1459 pmif->broken_dma_warn = 1;
1460 }
1461 goto use_pio_instead;
1462 }
1463 while (cur_len) {
1464 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1465
1466 if (count++ >= MAX_DCMDS) {
1467 printk(KERN_WARNING "%s: DMA table too small\n",
1468 drive->name);
1469 goto use_pio_instead;
1470 }
1471 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1472 st_le16(&table->req_count, tc);
1473 st_le32(&table->phy_addr, cur_addr);
1474 table->cmd_dep = 0;
1475 table->xfer_status = 0;
1476 table->res_count = 0;
1477 cur_addr += tc;
1478 cur_len -= tc;
1479 ++table;
1480 }
Jens Axboe55c16a72007-07-25 08:13:56 +02001481 sg = sg_next(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 i--;
1483 }
1484
1485 /* convert the last command to an input/output last command */
1486 if (count) {
1487 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1488 /* add the stop command to the end of the list */
1489 memset(table, 0, sizeof(struct dbdma_cmd));
1490 st_le16(&table->command, DBDMA_STOP);
1491 mb();
1492 writel(hwif->dmatable_dma, &dma->cmdptr);
1493 return 1;
1494 }
1495
1496 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001497
1498use_pio_instead:
1499 ide_destroy_dmatable(drive);
1500
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501 return 0; /* revert to PIO for this request */
1502}
1503
1504/* Teardown mappings after DMA has completed. */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001505static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506pmac_ide_destroy_dmatable (ide_drive_t *drive)
1507{
1508 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001510 if (hwif->sg_nents) {
1511 ide_destroy_dmatable(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512 hwif->sg_nents = 0;
1513 }
1514}
1515
1516/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1518 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1519 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001520static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521pmac_ide_dma_setup(ide_drive_t *drive)
1522{
1523 ide_hwif_t *hwif = HWIF(drive);
1524 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1525 struct request *rq = HWGROUP(drive)->rq;
1526 u8 unit = (drive->select.b.unit & 0x01);
1527 u8 ata4;
1528
1529 if (pmif == NULL)
1530 return 1;
1531 ata4 = (pmif->kind == controller_kl_ata4);
1532
1533 if (!pmac_ide_build_dmatable(drive, rq)) {
1534 ide_map_sg(drive, rq);
1535 return 1;
1536 }
1537
1538 /* Apple adds 60ns to wrDataSetup on reads */
1539 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1540 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1541 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1542 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1543 }
1544
1545 drive->waiting_for_dma = 1;
1546
1547 return 0;
1548}
1549
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001550static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1552{
1553 /* issue cmd to drive */
1554 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1555}
1556
1557/*
1558 * Kick the DMA controller into life after the DMA command has been issued
1559 * to the drive.
1560 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001561static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562pmac_ide_dma_start(ide_drive_t *drive)
1563{
1564 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1565 volatile struct dbdma_regs __iomem *dma;
1566
1567 dma = pmif->dma_regs;
1568
1569 writel((RUN << 16) | RUN, &dma->control);
1570 /* Make sure it gets to the controller right now */
1571 (void)readl(&dma->control);
1572}
1573
1574/*
1575 * After a DMA transfer, make sure the controller is stopped
1576 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001577static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578pmac_ide_dma_end (ide_drive_t *drive)
1579{
1580 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1581 volatile struct dbdma_regs __iomem *dma;
1582 u32 dstat;
1583
1584 if (pmif == NULL)
1585 return 0;
1586 dma = pmif->dma_regs;
1587
1588 drive->waiting_for_dma = 0;
1589 dstat = readl(&dma->status);
1590 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1591 pmac_ide_destroy_dmatable(drive);
1592 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1593 * in theory, but with ATAPI decices doing buffer underruns, that would
1594 * cause us to disable DMA, which isn't what we want
1595 */
1596 return (dstat & (RUN|DEAD)) != RUN;
1597}
1598
1599/*
1600 * Check out that the interrupt we got was for us. We can't always know this
1601 * for sure with those Apple interfaces (well, we could on the recent ones but
1602 * that's not implemented yet), on the other hand, we don't have shared interrupts
1603 * so it's not really a problem
1604 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001605static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606pmac_ide_dma_test_irq (ide_drive_t *drive)
1607{
1608 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1609 volatile struct dbdma_regs __iomem *dma;
1610 unsigned long status, timeout;
1611
1612 if (pmif == NULL)
1613 return 0;
1614 dma = pmif->dma_regs;
1615
1616 /* We have to things to deal with here:
1617 *
1618 * - The dbdma won't stop if the command was started
1619 * but completed with an error without transferring all
1620 * datas. This happens when bad blocks are met during
1621 * a multi-block transfer.
1622 *
1623 * - The dbdma fifo hasn't yet finished flushing to
1624 * to system memory when the disk interrupt occurs.
1625 *
1626 */
1627
1628 /* If ACTIVE is cleared, the STOP command have passed and
1629 * transfer is complete.
1630 */
1631 status = readl(&dma->status);
1632 if (!(status & ACTIVE))
1633 return 1;
1634 if (!drive->waiting_for_dma)
1635 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1636 called while not waiting\n", HWIF(drive)->index);
1637
1638 /* If dbdma didn't execute the STOP command yet, the
1639 * active bit is still set. We consider that we aren't
1640 * sharing interrupts (which is hopefully the case with
1641 * those controllers) and so we just try to flush the
1642 * channel for pending data in the fifo
1643 */
1644 udelay(1);
1645 writel((FLUSH << 16) | FLUSH, &dma->control);
1646 timeout = 0;
1647 for (;;) {
1648 udelay(1);
1649 status = readl(&dma->status);
1650 if ((status & FLUSH) == 0)
1651 break;
1652 if (++timeout > 100) {
1653 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1654 timeout flushing channel\n", HWIF(drive)->index);
1655 break;
1656 }
1657 }
1658 return 1;
1659}
1660
Bartlomiej Zolnierkiewicz15ce9262008-01-26 20:13:03 +01001661static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001662{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001663}
1664
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001665static void
1666pmac_ide_dma_lost_irq (ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667{
1668 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1669 volatile struct dbdma_regs __iomem *dma;
1670 unsigned long status;
1671
1672 if (pmif == NULL)
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001673 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674 dma = pmif->dma_regs;
1675
1676 status = readl(&dma->status);
1677 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678}
1679
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001680static const struct ide_dma_ops pmac_dma_ops = {
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001681 .dma_host_set = pmac_ide_dma_host_set,
1682 .dma_setup = pmac_ide_dma_setup,
1683 .dma_exec_cmd = pmac_ide_dma_exec_cmd,
1684 .dma_start = pmac_ide_dma_start,
1685 .dma_end = pmac_ide_dma_end,
1686 .dma_test_irq = pmac_ide_dma_test_irq,
1687 .dma_timeout = ide_dma_timeout,
1688 .dma_lost_irq = pmac_ide_dma_lost_irq,
1689};
1690
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691/*
1692 * Allocate the data structures needed for using DMA with an interface
1693 * and fill the proper list of functions pointers
1694 */
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001695static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1696 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697{
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001698 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001699 struct pci_dev *dev = to_pci_dev(hwif->dev);
1700
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701 /* We won't need pci_dev if we switch to generic consistent
1702 * DMA routines ...
1703 */
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001704 if (dev == NULL || pmif->dma_regs == 0)
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001705 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706 /*
1707 * Allocate space for the DBDMA commands.
1708 * The +2 is +1 for the stop command and +1 to allow for
1709 * aligning the start address to a multiple of 16 bytes.
1710 */
1711 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001712 dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1714 &hwif->dmatable_dma);
1715 if (pmif->dma_table_cpu == NULL) {
1716 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1717 hwif->name);
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001718 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001719 }
1720
Bartlomiej Zolnierkiewicz4f52a322008-01-26 20:13:08 +01001721 hwif->sg_max_nents = MAX_DCMDS;
1722
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001723 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724}
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001725#else
1726static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1727 const struct ide_port_info *d)
1728{
1729 return -EOPNOTSUPP;
1730}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Bartlomiej Zolnierkiewiczade2daf2008-01-26 20:13:07 +01001732
1733module_init(pmac_ide_probe);
Adrian Bunkde9facb2008-04-02 21:22:03 +02001734
1735MODULE_LICENSE("GPL");