blob: 21eff6f841d510b2906048187f73b4a2d5f1a73d [file] [log] [blame]
CK Hu119f5172016-01-04 18:36:34 +01001/*
2 * Copyright (c) 2015 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <drm/drmP.h>
15#include <linux/clk.h>
16#include <linux/component.h>
17#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/platform_device.h>
20
21#include "mtk_drm_crtc.h"
22#include "mtk_drm_ddp_comp.h"
23
24#define DISP_REG_RDMA_INT_ENABLE 0x0000
25#define DISP_REG_RDMA_INT_STATUS 0x0004
26#define RDMA_TARGET_LINE_INT BIT(5)
27#define RDMA_FIFO_UNDERFLOW_INT BIT(4)
28#define RDMA_EOF_ABNORMAL_INT BIT(3)
29#define RDMA_FRAME_END_INT BIT(2)
30#define RDMA_FRAME_START_INT BIT(1)
31#define RDMA_REG_UPDATE_INT BIT(0)
32#define DISP_REG_RDMA_GLOBAL_CON 0x0010
33#define RDMA_ENGINE_EN BIT(0)
34#define DISP_REG_RDMA_SIZE_CON_0 0x0014
35#define DISP_REG_RDMA_SIZE_CON_1 0x0018
36#define DISP_REG_RDMA_TARGET_LINE 0x001c
37#define DISP_REG_RDMA_FIFO_CON 0x0040
38#define RDMA_FIFO_UNDERFLOW_EN BIT(31)
39#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
40#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
41
42/**
43 * struct mtk_disp_rdma - DISP_RDMA driver structure
44 * @ddp_comp - structure containing type enum and hardware resources
45 * @crtc - associated crtc to report irq events to
46 */
47struct mtk_disp_rdma {
48 struct mtk_ddp_comp ddp_comp;
49 struct drm_crtc *crtc;
50};
51
yt.shen@mediatek.com55dc0652017-03-31 19:30:29 +080052static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
53{
54 return container_of(comp, struct mtk_disp_rdma, ddp_comp);
55}
56
CK Hu119f5172016-01-04 18:36:34 +010057static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
58{
59 struct mtk_disp_rdma *priv = dev_id;
60 struct mtk_ddp_comp *rdma = &priv->ddp_comp;
61
62 /* Clear frame completion interrupt */
63 writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS);
64
65 if (!priv->crtc)
66 return IRQ_NONE;
67
68 mtk_crtc_ddp_irq(priv->crtc, rdma);
69
70 return IRQ_HANDLED;
71}
72
73static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg,
74 unsigned int mask, unsigned int val)
75{
76 unsigned int tmp = readl(comp->regs + reg);
77
78 tmp = (tmp & ~mask) | (val & mask);
79 writel(tmp, comp->regs + reg);
80}
81
82static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
83 struct drm_crtc *crtc)
84{
yt.shen@mediatek.com55dc0652017-03-31 19:30:29 +080085 struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
CK Hu119f5172016-01-04 18:36:34 +010086
yt.shen@mediatek.com55dc0652017-03-31 19:30:29 +080087 rdma->crtc = crtc;
CK Hu119f5172016-01-04 18:36:34 +010088 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
89 RDMA_FRAME_END_INT);
90}
91
92static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
93{
yt.shen@mediatek.com55dc0652017-03-31 19:30:29 +080094 struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
CK Hu119f5172016-01-04 18:36:34 +010095
yt.shen@mediatek.com55dc0652017-03-31 19:30:29 +080096 rdma->crtc = NULL;
CK Hu119f5172016-01-04 18:36:34 +010097 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
98}
99
100static void mtk_rdma_start(struct mtk_ddp_comp *comp)
101{
102 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
103 RDMA_ENGINE_EN);
104}
105
106static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
107{
108 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
109}
110
111static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
Bibby Hsieh72164362016-07-28 10:22:55 +0800112 unsigned int height, unsigned int vrefresh,
113 unsigned int bpc)
CK Hu119f5172016-01-04 18:36:34 +0100114{
115 unsigned int threshold;
116 unsigned int reg;
117
118 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
119 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
120
121 /*
122 * Enable FIFO underflow since DSI and DPI can't be blocked.
123 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
124 * output threshold to 6 microseconds with 7/6 overhead to
125 * account for blanking, and with a pixel depth of 4 bytes:
126 */
127 threshold = width * height * vrefresh * 4 * 7 / 1000000;
128 reg = RDMA_FIFO_UNDERFLOW_EN |
129 RDMA_FIFO_PSEUDO_SIZE(SZ_8K) |
130 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
131 writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
132}
133
134static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
135 .config = mtk_rdma_config,
136 .start = mtk_rdma_start,
137 .stop = mtk_rdma_stop,
138 .enable_vblank = mtk_rdma_enable_vblank,
139 .disable_vblank = mtk_rdma_disable_vblank,
140};
141
142static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
143 void *data)
144{
145 struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
146 struct drm_device *drm_dev = data;
147 int ret;
148
149 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
150 if (ret < 0) {
151 dev_err(dev, "Failed to register component %s: %d\n",
152 dev->of_node->full_name, ret);
153 return ret;
154 }
155
156 return 0;
157
158}
159
160static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
161 void *data)
162{
163 struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
164 struct drm_device *drm_dev = data;
165
166 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
167}
168
169static const struct component_ops mtk_disp_rdma_component_ops = {
170 .bind = mtk_disp_rdma_bind,
171 .unbind = mtk_disp_rdma_unbind,
172};
173
174static int mtk_disp_rdma_probe(struct platform_device *pdev)
175{
176 struct device *dev = &pdev->dev;
177 struct mtk_disp_rdma *priv;
178 int comp_id;
179 int irq;
180 int ret;
181
182 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
183 if (!priv)
184 return -ENOMEM;
185
186 irq = platform_get_irq(pdev, 0);
187 if (irq < 0)
188 return irq;
189
190 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA);
191 if (comp_id < 0) {
192 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
193 return comp_id;
194 }
195
196 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
197 &mtk_disp_rdma_funcs);
198 if (ret) {
199 dev_err(dev, "Failed to initialize component: %d\n", ret);
200 return ret;
201 }
202
203 /* Disable and clear pending interrupts */
204 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE);
205 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS);
206
207 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
208 IRQF_TRIGGER_NONE, dev_name(dev), priv);
209 if (ret < 0) {
210 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
211 return ret;
212 }
213
214 platform_set_drvdata(pdev, priv);
215
216 ret = component_add(dev, &mtk_disp_rdma_component_ops);
217 if (ret)
218 dev_err(dev, "Failed to add component: %d\n", ret);
219
220 return ret;
221}
222
223static int mtk_disp_rdma_remove(struct platform_device *pdev)
224{
225 component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
226
227 return 0;
228}
229
230static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
231 { .compatible = "mediatek,mt8173-disp-rdma", },
232 {},
233};
234MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
235
236struct platform_driver mtk_disp_rdma_driver = {
237 .probe = mtk_disp_rdma_probe,
238 .remove = mtk_disp_rdma_remove,
239 .driver = {
240 .name = "mediatek-disp-rdma",
241 .owner = THIS_MODULE,
242 .of_match_table = mtk_disp_rdma_driver_dt_match,
243 },
244};