Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / c6f5e017df9dfa9f6cbe70da008e7d716d726f1b / . / drivers / gpu / drm / amd / include / atomfirmware.h
blob: 092d800b703a7627a2b98fdda7be54b5b6f7ff11 [file] [log] [blame]
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type{
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM = 0x60,
183};
184
185enum atom_dp_vs_preemph_def{
186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
196};
197
198
199/*
200enum atom_string_def{
201asic_bus_type_pcie_string = "PCI_EXPRESS",
202atom_fire_gl_string = "FGL",
203atom_bios_string = "ATOM"
204};
205*/
206
207#pragma pack(1) /* BIOS data must use byte aligment*/
208
209enum atombios_image_offset{
210OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
211OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
212OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
213MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
214OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
215OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
216};
217
218/****************************************************************************
219* Common header for all tables (Data table, Command function).
220* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
221* And the pointer actually points to this header.
222****************************************************************************/
223
224struct atom_common_table_header
225{
226 uint16_t structuresize;
227 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
228 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
229};
230
231/****************************************************************************
232* Structure stores the ROM header.
233****************************************************************************/
234struct atom_rom_header_v2_2
235{
236 struct atom_common_table_header table_header;
237 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
238 uint16_t bios_segment_address;
239 uint16_t protectedmodeoffset;
240 uint16_t configfilenameoffset;
241 uint16_t crc_block_offset;
242 uint16_t vbios_bootupmessageoffset;
243 uint16_t int10_offset;
244 uint16_t pcibusdevinitcode;
245 uint16_t iobaseaddress;
246 uint16_t subsystem_vendor_id;
247 uint16_t subsystem_id;
248 uint16_t pci_info_offset;
249 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
250 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
251 uint16_t reserved;
252 uint32_t pspdirtableoffset;
253};
254
255/*==============================hw function portion======================================================================*/
256
257
258/****************************************************************************
259* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
260* The real functionality of each function is associated with the parameter structure version when defined
261* For all internal cmd function definitions, please reference to atomstruct.h
262****************************************************************************/
263struct atom_master_list_of_command_functions_v2_1{
264 uint16_t asic_init; //Function
265 uint16_t cmd_function1; //used as an internal one
266 uint16_t cmd_function2; //used as an internal one
267 uint16_t cmd_function3; //used as an internal one
268 uint16_t digxencodercontrol; //Function
269 uint16_t cmd_function5; //used as an internal one
270 uint16_t cmd_function6; //used as an internal one
271 uint16_t cmd_function7; //used as an internal one
272 uint16_t cmd_function8; //used as an internal one
273 uint16_t cmd_function9; //used as an internal one
274 uint16_t setengineclock; //Function
275 uint16_t setmemoryclock; //Function
276 uint16_t setpixelclock; //Function
277 uint16_t enabledisppowergating; //Function
278 uint16_t cmd_function14; //used as an internal one
279 uint16_t cmd_function15; //used as an internal one
280 uint16_t cmd_function16; //used as an internal one
281 uint16_t cmd_function17; //used as an internal one
282 uint16_t cmd_function18; //used as an internal one
283 uint16_t cmd_function19; //used as an internal one
284 uint16_t cmd_function20; //used as an internal one
285 uint16_t cmd_function21; //used as an internal one
286 uint16_t cmd_function22; //used as an internal one
287 uint16_t cmd_function23; //used as an internal one
288 uint16_t cmd_function24; //used as an internal one
289 uint16_t cmd_function25; //used as an internal one
290 uint16_t cmd_function26; //used as an internal one
291 uint16_t cmd_function27; //used as an internal one
292 uint16_t cmd_function28; //used as an internal one
293 uint16_t cmd_function29; //used as an internal one
294 uint16_t cmd_function30; //used as an internal one
295 uint16_t cmd_function31; //used as an internal one
296 uint16_t cmd_function32; //used as an internal one
297 uint16_t cmd_function33; //used as an internal one
298 uint16_t blankcrtc; //Function
299 uint16_t enablecrtc; //Function
300 uint16_t cmd_function36; //used as an internal one
301 uint16_t cmd_function37; //used as an internal one
302 uint16_t cmd_function38; //used as an internal one
303 uint16_t cmd_function39; //used as an internal one
304 uint16_t cmd_function40; //used as an internal one
305 uint16_t getsmuclockinfo; //Function
306 uint16_t selectcrtc_source; //Function
307 uint16_t cmd_function43; //used as an internal one
308 uint16_t cmd_function44; //used as an internal one
309 uint16_t cmd_function45; //used as an internal one
310 uint16_t setdceclock; //Function
311 uint16_t getmemoryclock; //Function
312 uint16_t getengineclock; //Function
313 uint16_t setcrtc_usingdtdtiming; //Function
314 uint16_t externalencodercontrol; //Function
315 uint16_t cmd_function51; //used as an internal one
316 uint16_t cmd_function52; //used as an internal one
317 uint16_t cmd_function53; //used as an internal one
318 uint16_t processi2cchanneltransaction;//Function
319 uint16_t cmd_function55; //used as an internal one
320 uint16_t cmd_function56; //used as an internal one
321 uint16_t cmd_function57; //used as an internal one
322 uint16_t cmd_function58; //used as an internal one
323 uint16_t cmd_function59; //used as an internal one
324 uint16_t computegpuclockparam; //Function
325 uint16_t cmd_function61; //used as an internal one
326 uint16_t cmd_function62; //used as an internal one
327 uint16_t dynamicmemorysettings; //Function function
328 uint16_t memorytraining; //Function function
329 uint16_t cmd_function65; //used as an internal one
330 uint16_t cmd_function66; //used as an internal one
331 uint16_t setvoltage; //Function
332 uint16_t cmd_function68; //used as an internal one
333 uint16_t readefusevalue; //Function
334 uint16_t cmd_function70; //used as an internal one
335 uint16_t cmd_function71; //used as an internal one
336 uint16_t cmd_function72; //used as an internal one
337 uint16_t cmd_function73; //used as an internal one
338 uint16_t cmd_function74; //used as an internal one
339 uint16_t cmd_function75; //used as an internal one
340 uint16_t dig1transmittercontrol; //Function
341 uint16_t cmd_function77; //used as an internal one
342 uint16_t processauxchanneltransaction;//Function
343 uint16_t cmd_function79; //used as an internal one
344 uint16_t getvoltageinfo; //Function
345};
346
347struct atom_master_command_function_v2_1
348{
349 struct atom_common_table_header table_header;
350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
351};
352
353/****************************************************************************
354* Structures used in every command function
355****************************************************************************/
356struct atom_function_attribute
357{
358 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
359 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
360 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
361};
362
363
364/****************************************************************************
365* Common header for all hw functions.
366* Every function pointed by _master_list_of_hw_function has this common header.
367* And the pointer actually points to this header.
368****************************************************************************/
369struct atom_rom_hw_function_header
370{
371 struct atom_common_table_header func_header;
372 struct atom_function_attribute func_attrib;
373};
374
375
376/*==============================sw data table portion======================================================================*/
377/****************************************************************************
378* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
379* The real name of each table is given when its data structure version is defined
380****************************************************************************/
381struct atom_master_list_of_data_tables_v2_1{
382 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
383 uint16_t multimedia_info;
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]384 uint16_t smc_dpm_info;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]385 uint16_t sw_datatable3;
386 uint16_t firmwareinfo; /* Shared by various SW components */
387 uint16_t sw_datatable5;
388 uint16_t lcd_info; /* Shared by various SW components */
389 uint16_t sw_datatable7;
390 uint16_t smu_info;
391 uint16_t sw_datatable9;
392 uint16_t sw_datatable10;
393 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
394 uint16_t gpio_pin_lut; /* Shared by various SW components */
395 uint16_t sw_datatable13;
396 uint16_t gfx_info;
397 uint16_t powerplayinfo; /* Shared by various SW components */
398 uint16_t sw_datatable16;
399 uint16_t sw_datatable17;
400 uint16_t sw_datatable18;
401 uint16_t sw_datatable19;
402 uint16_t sw_datatable20;
403 uint16_t sw_datatable21;
404 uint16_t displayobjectinfo; /* Shared by various SW components */
405 uint16_t indirectioaccess; /* used as an internal one */
406 uint16_t umc_info; /* Shared by various SW components */
407 uint16_t sw_datatable25;
408 uint16_t sw_datatable26;
409 uint16_t dce_info; /* Shared by various SW components */
410 uint16_t vram_info; /* Shared by various SW components */
411 uint16_t sw_datatable29;
412 uint16_t integratedsysteminfo; /* Shared by various SW components */
413 uint16_t asic_profiling_info; /* Shared by various SW components */
414 uint16_t voltageobject_info; /* shared by various SW components */
415 uint16_t sw_datatable33;
416 uint16_t sw_datatable34;
417};
418
419
420struct atom_master_data_table_v2_1
421{
422 struct atom_common_table_header table_header;
423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
424};
425
426
427struct atom_dtd_format
428{
429 uint16_t pixclk;
430 uint16_t h_active;
431 uint16_t h_blanking_time;
432 uint16_t v_active;
433 uint16_t v_blanking_time;
434 uint16_t h_sync_offset;
435 uint16_t h_sync_width;
436 uint16_t v_sync_offset;
437 uint16_t v_syncwidth;
438 uint16_t reserved;
439 uint16_t reserved0;
440 uint8_t h_border;
441 uint8_t v_border;
442 uint16_t miscinfo;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
445};
446
447/* atom_dtd_format.modemiscinfo defintion */
448enum atom_dtd_format_modemiscinfo{
449 ATOM_HSYNC_POLARITY = 0x0002,
450 ATOM_VSYNC_POLARITY = 0x0004,
451 ATOM_H_REPLICATIONBY2 = 0x0010,
452 ATOM_V_REPLICATIONBY2 = 0x0020,
453 ATOM_INTERLACE = 0x0080,
454 ATOM_COMPOSITESYNC = 0x0040,
455};
456
457
458/* utilitypipeline
459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
460 * the location of it can't change
461*/
462
463
464/*
465 ***************************************************************************
466 Data Table firmwareinfo structure
467 ***************************************************************************
468*/
469
470struct atom_firmware_info_v3_1
471{
472 struct atom_common_table_header table_header;
473 uint32_t firmware_revision;
474 uint32_t bootup_sclk_in10khz;
475 uint32_t bootup_mclk_in10khz;
476 uint32_t firmware_capability; // enum atombios_firmware_capability
477 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
478 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
479 uint16_t bootup_vddc_mv;
480 uint16_t bootup_vddci_mv;
481 uint16_t bootup_mvddc_mv;
482 uint16_t bootup_vddgfx_mv;
483 uint8_t mem_module_id;
484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
485 uint8_t reserved1[2];
486 uint32_t mc_baseaddr_high;
487 uint32_t mc_baseaddr_low;
488 uint32_t reserved2[6];
489};
490
491/* Total 32bit cap indication */
492enum atombios_firmware_capability
493{
494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
497};
498
499enum atom_cooling_solution_id{
500 AIR_COOLING = 0x00,
501 LIQUID_COOLING = 0x01
502};
503
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability; // enum atombios_firmware_capability
510 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]530
531/*
532 ***************************************************************************
533 Data Table lcd_info structure
534 ***************************************************************************
535*/
536
537struct lcd_info_v2_1
538{
539 struct atom_common_table_header table_header;
540 struct atom_dtd_format lcd_timing;
541 uint16_t backlight_pwm;
542 uint16_t special_handle_cap;
543 uint16_t panel_misc;
544 uint16_t lvds_max_slink_pclk;
545 uint16_t lvds_ss_percentage;
546 uint16_t lvds_ss_rate_10hz;
547 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
548 uint8_t pwr_on_de_to_vary_bl;
549 uint8_t pwr_down_vary_bloff_to_de;
550 uint8_t pwr_down_de_to_digoff;
551 uint8_t pwr_off_delay;
552 uint8_t pwr_on_vary_bl_to_blon;
553 uint8_t pwr_down_bloff_to_vary_bloff;
554 uint8_t panel_bpc;
555 uint8_t dpcd_edp_config_cap;
556 uint8_t dpcd_max_link_rate;
557 uint8_t dpcd_max_lane_count;
558 uint8_t dpcd_max_downspread;
559 uint8_t min_allowed_bl_level;
560 uint8_t max_allowed_bl_level;
561 uint8_t bootup_bl_level;
562 uint8_t dplvdsrxid;
563 uint32_t reserved1[8];
564};
565
566/* lcd_info_v2_1.panel_misc defintion */
567enum atom_lcd_info_panel_misc{
568 ATOM_PANEL_MISC_FPDI =0x0002,
569};
570
571//uceDPToLVDSRxId
572enum atom_lcd_info_dptolvds_rx_id
573{
574 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
575 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
576 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
577};
578
579
580/*
581 ***************************************************************************
582 Data Table gpio_pin_lut structure
583 ***************************************************************************
584*/
585
586struct atom_gpio_pin_assignment
587{
588 uint32_t data_a_reg_index;
589 uint8_t gpio_bitshift;
590 uint8_t gpio_mask_bitshift;
591 uint8_t gpio_id;
592 uint8_t reserved;
593};
594
595/* atom_gpio_pin_assignment.gpio_id definition */
596enum atom_gpio_pin_assignment_gpio_id {
597 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
598 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
599 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
600
601 /* gpio_id pre-define id for multiple usage */
602 /* GPIO use to control PCIE_VDDC in certain SLT board */
603 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
604 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
605 PP_AC_DC_SWITCH_GPIO_PINID = 60,
606 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
607 VDDC_VRHOT_GPIO_PINID = 61,
608 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
609 VDDC_PCC_GPIO_PINID = 62,
610 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
611 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
612 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
613 DRAM_SELF_REFRESH_GPIO_PINID = 64,
614 /* Thermal interrupt output->system thermal chip GPIO pin */
615 THERMAL_INT_OUTPUT_GPIO_PINID =65,
616};
617
618
619struct atom_gpio_pin_lut_v2_1
620{
621 struct atom_common_table_header table_header;
622 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
623 struct atom_gpio_pin_assignment gpio_pin[8];
624};
625
626
627/*
628 ***************************************************************************
629 Data Table vram_usagebyfirmware structure
630 ***************************************************************************
631*/
632
633struct vram_usagebyfirmware_v2_1
634{
635 struct atom_common_table_header table_header;
636 uint32_t start_address_in_kb;
637 uint16_t used_by_firmware_in_kb;
638 uint16_t used_by_driver_in_kb;
639};
640
641
642/*
643 ***************************************************************************
644 Data Table displayobjectinfo structure
645 ***************************************************************************
646*/
647
648enum atom_object_record_type_id
649{
650 ATOM_I2C_RECORD_TYPE =1,
651 ATOM_HPD_INT_RECORD_TYPE =2,
652 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
653 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
654 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
655 ATOM_ENCODER_CAP_RECORD_TYPE=20,
656 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
657 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
658 ATOM_RECORD_END_TYPE =0xFF,
659};
660
661struct atom_common_record_header
662{
663 uint8_t record_type; //An emun to indicate the record type
664 uint8_t record_size; //The size of the whole record in byte
665};
666
667struct atom_i2c_record
668{
669 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
670 uint8_t i2c_id;
671 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
672};
673
674struct atom_hpd_int_record
675{
676 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
677 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
678 uint8_t plugin_pin_state;
679};
680
681// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
682enum atom_encoder_caps_def
683{
684 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
685 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
686 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
687 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
688 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
689};
690
691struct atom_encoder_caps_record
692{
693 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
694 uint32_t encodercaps;
695};
696
697enum atom_connector_caps_def
698{
699 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
700 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
701};
702
703struct atom_disp_connector_caps_record
704{
705 struct atom_common_record_header record_header;
706 uint32_t connectcaps;
707};
708
709//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
710struct atom_gpio_pin_control_pair
711{
712 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
713 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
714};
715
716struct atom_object_gpio_cntl_record
717{
718 struct atom_common_record_header record_header;
719 uint8_t flag; // Future expnadibility
720 uint8_t number_of_pins; // Number of GPIO pins used to control the object
721 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
722};
723
724//Definitions for GPIO pin state
725enum atom_gpio_pin_control_pinstate_def
726{
727 GPIO_PIN_TYPE_INPUT = 0x00,
728 GPIO_PIN_TYPE_OUTPUT = 0x10,
729 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
730
731//For GPIO_PIN_TYPE_OUTPUT the following is defined
732 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
733 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
734 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
735 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
736};
737
738// Indexes to GPIO array in GLSync record
739// GLSync record is for Frame Lock/Gen Lock feature.
740enum atom_glsync_record_gpio_index_def
741{
742 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
743 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
744 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
745 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
746 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
747 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
748 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
749 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
750 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
751 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
752};
753
754
755struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
756{
757 struct atom_common_record_header record_header;
758 uint8_t hpd_pin_map[8];
759};
760
761struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
762{
763 struct atom_common_record_header record_header;
764 uint8_t aux_ddc_map[8];
765};
766
767struct atom_connector_forced_tmds_cap_record
768{
769 struct atom_common_record_header record_header;
770 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
771 uint8_t maxtmdsclkrate_in2_5mhz;
772 uint8_t reserved;
773};
774
775struct atom_connector_layout_info
776{
777 uint16_t connectorobjid;
778 uint8_t connector_type;
779 uint8_t position;
780};
781
782// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
783enum atom_connector_layout_info_connector_type_def
784{
785 CONNECTOR_TYPE_DVI_D = 1,
786
787 CONNECTOR_TYPE_HDMI = 4,
788 CONNECTOR_TYPE_DISPLAY_PORT = 5,
789 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
790};
791
792struct atom_bracket_layout_record
793{
794 struct atom_common_record_header record_header;
795 uint8_t bracketlen;
796 uint8_t bracketwidth;
797 uint8_t conn_num;
798 uint8_t reserved;
799 struct atom_connector_layout_info conn_info[1];
800};
801
802enum atom_display_device_tag_def{
803 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
804 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
805 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
806 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
807 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
808 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
809 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
810 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
811};
812
813struct atom_display_object_path_v2
814{
815 uint16_t display_objid; //Connector Object ID or Misc Object ID
816 uint16_t disp_recordoffset;
817 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
818 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
819 uint16_t encoder_recordoffset;
820 uint16_t extencoder_recordoffset;
821 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
822 uint8_t priority_id;
823 uint8_t reserved;
824};
825
826struct display_object_info_table_v1_4
827{
828 struct atom_common_table_header table_header;
829 uint16_t supporteddevices;
830 uint8_t number_of_path;
831 uint8_t reserved;
832 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
833};
834
835
836/*
837 ***************************************************************************
838 Data Table dce_info structure
839 ***************************************************************************
840*/
841struct atom_display_controller_info_v4_1
842{
843 struct atom_common_table_header table_header;
844 uint32_t display_caps;
845 uint32_t bootup_dispclk_10khz;
846 uint16_t dce_refclk_10khz;
847 uint16_t i2c_engine_refclk_10khz;
848 uint16_t dvi_ss_percentage; // in unit of 0.001%
849 uint16_t dvi_ss_rate_10hz;
850 uint16_t hdmi_ss_percentage; // in unit of 0.001%
851 uint16_t hdmi_ss_rate_10hz;
852 uint16_t dp_ss_percentage; // in unit of 0.001%
853 uint16_t dp_ss_rate_10hz;
854 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
855 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
856 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
857 uint8_t ss_reserved;
858 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
859 uint8_t reserved1[3];
860 uint16_t dpphy_refclk_10khz;
861 uint16_t reserved2;
862 uint8_t dceip_min_ver;
863 uint8_t dceip_max_ver;
864 uint8_t max_disp_pipe_num;
865 uint8_t max_vbios_active_disp_pipe_num;
866 uint8_t max_ppll_num;
867 uint8_t max_disp_phy_num;
868 uint8_t max_aux_pairs;
869 uint8_t remotedisplayconfig;
870 uint8_t reserved3[8];
871};
872
873
874struct atom_display_controller_info_v4_2
875{
876 struct atom_common_table_header table_header;
877 uint32_t display_caps;
878 uint32_t bootup_dispclk_10khz;
879 uint16_t dce_refclk_10khz;
880 uint16_t i2c_engine_refclk_10khz;
881 uint16_t dvi_ss_percentage; // in unit of 0.001%
882 uint16_t dvi_ss_rate_10hz;
883 uint16_t hdmi_ss_percentage; // in unit of 0.001%
884 uint16_t hdmi_ss_rate_10hz;
885 uint16_t dp_ss_percentage; // in unit of 0.001%
886 uint16_t dp_ss_rate_10hz;
887 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
888 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
889 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
890 uint8_t ss_reserved;
891 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
892 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
893 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
894 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
895 uint16_t dpphy_refclk_10khz;
896 uint16_t reserved2;
897 uint8_t dcnip_min_ver;
898 uint8_t dcnip_max_ver;
899 uint8_t max_disp_pipe_num;
900 uint8_t max_vbios_active_disp_pipe_num;
901 uint8_t max_ppll_num;
902 uint8_t max_disp_phy_num;
903 uint8_t max_aux_pairs;
904 uint8_t remotedisplayconfig;
905 uint8_t reserved3[8];
906};
907
908
909enum dce_info_caps_def
910{
911 // only for VBIOS
912 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
913 // only for VBIOS
914 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
915 // only for VBIOS
916 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
917
918};
919
920/*
921 ***************************************************************************
922 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
923 ***************************************************************************
924*/
925struct atom_ext_display_path
926{
927 uint16_t device_tag; //A bit vector to show what devices are supported
928 uint16_t device_acpi_enum; //16bit device ACPI id.
929 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
930 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
931 uint8_t hpdlut_index; //An index into external HPD pin LUT
932 uint16_t ext_encoder_objid; //external encoder object id
933 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
934 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
935 uint16_t caps;
936 uint16_t reserved;
937};
938
939//usCaps
940enum ext_display_path_cap_def
941{
942 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
943 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
944 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
945};
946
947struct atom_external_display_connection_info
948{
949 struct atom_common_table_header table_header;
950 uint8_t guid[16]; // a GUID is a 16 byte long string
951 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
952 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
953 uint8_t stereopinid; // use for eDP panel
954 uint8_t remotedisplayconfig;
955 uint8_t edptolvdsrxid;
956 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
957 uint8_t reserved[3]; // for potential expansion
958};
959
960/*
961 ***************************************************************************
962 Data Table integratedsysteminfo structure
963 ***************************************************************************
964*/
965
966struct atom_camera_dphy_timing_param
967{
968 uint8_t profile_id; // SENSOR_PROFILES
969 uint32_t param;
970};
971
972struct atom_camera_dphy_elec_param
973{
974 uint16_t param[3];
975};
976
977struct atom_camera_module_info
978{
979 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
980 uint8_t module_name[8];
981 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
982};
983
984struct atom_camera_flashlight_info
985{
986 uint8_t flashlight_id; // 0: Rear, 1: Front
987 uint8_t name[8];
988};
989
990struct atom_camera_data
991{
992 uint32_t versionCode;
993 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
994 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
995 struct atom_camera_dphy_elec_param dphy_param;
996 uint32_t crc_val; // CRC
997};
998
999
1000struct atom_14nm_dpphy_dvihdmi_tuningset
1001{
1002 uint32_t max_symclk_in10khz;
1003 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1004 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1005 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1006 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1007 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1008 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1009 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1010};
1011
1012struct atom_14nm_dpphy_dp_setting{
1013 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1014 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1015 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1016 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1017};
1018
1019struct atom_14nm_dpphy_dp_tuningset{
1020 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1021 uint8_t version;
1022 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1023 uint16_t reserved;
1024 struct atom_14nm_dpphy_dp_setting dptuning[10];
1025};
1026
1027struct atom_14nm_dig_transmitter_info_header_v4_0{
1028 struct atom_common_table_header table_header;
1029 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1030 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1031 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1032};
1033
1034struct atom_14nm_combphy_tmds_vs_set
1035{
1036 uint8_t sym_clk;
1037 uint8_t dig_mode;
1038 uint8_t phy_sel;
1039 uint16_t common_mar_deemph_nom__margin_deemph_val;
1040 uint8_t common_seldeemph60__deemph_6db_4_val;
1041 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1042 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1043 uint8_t margin_deemph_lane0__deemph_sel_val;
1044};
1045
Harry Wentlande719d512017-08-21 15:43:32 -0400[diff] [blame]1046struct atom_i2c_reg_info {
1047 uint8_t ucI2cRegIndex;
1048 uint8_t ucI2cRegVal;
1049};
1050
1051struct atom_hdmi_retimer_redriver_set {
1052 uint8_t HdmiSlvAddr;
1053 uint8_t HdmiRegNum;
1054 uint8_t Hdmi6GRegNum;
1055 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1056 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1057};
1058
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1059struct atom_integrated_system_info_v1_11
1060{
1061 struct atom_common_table_header table_header;
1062 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1063 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1064 uint32_t system_config;
1065 uint32_t cpucapinfo;
1066 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1067 uint16_t gpuclk_ss_type;
1068 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1069 uint16_t lvds_ss_rate_10hz;
1070 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1071 uint16_t hdmi_ss_rate_10hz;
1072 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1073 uint16_t dvi_ss_rate_10hz;
1074 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1075 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1076 uint16_t backlight_pwm_hz; // pwm frequency in hz
1077 uint8_t memorytype; // enum of atom_sys_mem_type
1078 uint8_t umachannelnumber; // number of memory channels
1079 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1080 uint8_t pwr_on_de_to_vary_bl;
1081 uint8_t pwr_down_vary_bloff_to_de;
1082 uint8_t pwr_down_de_to_digoff;
1083 uint8_t pwr_off_delay;
1084 uint8_t pwr_on_vary_bl_to_blon;
1085 uint8_t pwr_down_bloff_to_vary_bloff;
1086 uint8_t min_allowed_bl_level;
1087 struct atom_external_display_connection_info extdispconninfo;
1088 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1089 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1090 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1091 struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
1092 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
1093 struct atom_camera_data camera_info;
Harry Wentlande719d512017-08-21 15:43:32 -0400[diff] [blame]1094 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1095 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1096 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1097 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1098 uint32_t reserved[108];
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1099};
1100
1101
1102// system_config
1103enum atom_system_vbiosmisc_def{
1104 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1105};
1106
1107
1108// gpucapinfo
1109enum atom_system_gpucapinf_def{
1110 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1111};
1112
1113//dpphy_override
1114enum atom_sysinfo_dpphy_override_def{
1115 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1116 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1117 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1118 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1119 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1120};
1121
1122//lvds_misc
1123enum atom_sys_info_lvds_misc_def
1124{
1125 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1126 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1127 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1128};
1129
1130
1131//memorytype DMI Type 17 offset 12h - Memory Type
1132enum atom_dmi_t17_mem_type_def{
1133 OtherMemType = 0x01, ///< Assign 01 to Other
1134 UnknownMemType, ///< Assign 02 to Unknown
1135 DramMemType, ///< Assign 03 to DRAM
1136 EdramMemType, ///< Assign 04 to EDRAM
1137 VramMemType, ///< Assign 05 to VRAM
1138 SramMemType, ///< Assign 06 to SRAM
1139 RamMemType, ///< Assign 07 to RAM
1140 RomMemType, ///< Assign 08 to ROM
1141 FlashMemType, ///< Assign 09 to Flash
1142 EepromMemType, ///< Assign 10 to EEPROM
1143 FepromMemType, ///< Assign 11 to FEPROM
1144 EpromMemType, ///< Assign 12 to EPROM
1145 CdramMemType, ///< Assign 13 to CDRAM
1146 ThreeDramMemType, ///< Assign 14 to 3DRAM
1147 SdramMemType, ///< Assign 15 to SDRAM
1148 SgramMemType, ///< Assign 16 to SGRAM
1149 RdramMemType, ///< Assign 17 to RDRAM
1150 DdrMemType, ///< Assign 18 to DDR
1151 Ddr2MemType, ///< Assign 19 to DDR2
1152 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1153 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1154 Fbd2MemType, ///< Assign 25 to FBD2
1155 Ddr4MemType, ///< Assign 26 to DDR4
1156 LpDdrMemType, ///< Assign 27 to LPDDR
1157 LpDdr2MemType, ///< Assign 28 to LPDDR2
1158 LpDdr3MemType, ///< Assign 29 to LPDDR3
1159 LpDdr4MemType, ///< Assign 30 to LPDDR4
1160};
1161
1162
1163// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1164struct atom_fusion_system_info_v4
1165{
1166 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1167 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1168};
1169
1170
1171/*
1172 ***************************************************************************
1173 Data Table gfx_info structure
1174 ***************************************************************************
1175*/
1176
1177struct atom_gfx_info_v2_2
1178{
1179 struct atom_common_table_header table_header;
1180 uint8_t gfxip_min_ver;
1181 uint8_t gfxip_max_ver;
1182 uint8_t max_shader_engines;
1183 uint8_t max_tile_pipes;
1184 uint8_t max_cu_per_sh;
1185 uint8_t max_sh_per_se;
1186 uint8_t max_backends_per_se;
1187 uint8_t max_texture_channel_caches;
1188 uint32_t regaddr_cp_dma_src_addr;
1189 uint32_t regaddr_cp_dma_src_addr_hi;
1190 uint32_t regaddr_cp_dma_dst_addr;
1191 uint32_t regaddr_cp_dma_dst_addr_hi;
1192 uint32_t regaddr_cp_dma_command;
1193 uint32_t regaddr_cp_status;
1194 uint32_t regaddr_rlc_gpu_clock_32;
1195 uint32_t rlc_gpu_timer_refclk;
1196};
1197
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]1198struct atom_gfx_info_v2_3 {
1199 struct atom_common_table_header table_header;
1200 uint8_t gfxip_min_ver;
1201 uint8_t gfxip_max_ver;
1202 uint8_t max_shader_engines;
1203 uint8_t max_tile_pipes;
1204 uint8_t max_cu_per_sh;
1205 uint8_t max_sh_per_se;
1206 uint8_t max_backends_per_se;
1207 uint8_t max_texture_channel_caches;
1208 uint32_t regaddr_cp_dma_src_addr;
1209 uint32_t regaddr_cp_dma_src_addr_hi;
1210 uint32_t regaddr_cp_dma_dst_addr;
1211 uint32_t regaddr_cp_dma_dst_addr_hi;
1212 uint32_t regaddr_cp_dma_command;
1213 uint32_t regaddr_cp_status;
1214 uint32_t regaddr_rlc_gpu_clock_32;
1215 uint32_t rlc_gpu_timer_refclk;
1216 uint8_t active_cu_per_sh;
1217 uint8_t active_rb_per_se;
1218 uint16_t gcgoldenoffset;
1219 uint32_t rm21_sram_vmin_value;
1220};
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1221
Alex Deucher6f687112018-03-15 21:32:27 -0500[diff] [blame]1222struct atom_gfx_info_v2_4 {
1223 struct atom_common_table_header table_header;
1224 uint8_t gfxip_min_ver;
1225 uint8_t gfxip_max_ver;
1226 uint8_t gc_num_se;
1227 uint8_t max_tile_pipes;
1228 uint8_t gc_num_cu_per_sh;
1229 uint8_t gc_num_sh_per_se;
1230 uint8_t gc_num_rb_per_se;
1231 uint8_t gc_num_tccs;
1232 uint32_t regaddr_cp_dma_src_addr;
1233 uint32_t regaddr_cp_dma_src_addr_hi;
1234 uint32_t regaddr_cp_dma_dst_addr;
1235 uint32_t regaddr_cp_dma_dst_addr_hi;
1236 uint32_t regaddr_cp_dma_command;
1237 uint32_t regaddr_cp_status;
1238 uint32_t regaddr_rlc_gpu_clock_32;
1239 uint32_t rlc_gpu_timer_refclk;
1240 uint8_t active_cu_per_sh;
1241 uint8_t active_rb_per_se;
1242 uint16_t gcgoldenoffset;
Alex Deucher6f687112018-03-15 21:32:27 -0500[diff] [blame]1243 uint16_t gc_num_gprs;
1244 uint16_t gc_gsprim_buff_depth;
1245 uint16_t gc_parameter_cache_depth;
1246 uint16_t gc_wave_size;
1247 uint16_t gc_max_waves_per_simd;
1248 uint16_t gc_lds_size;
1249 uint8_t gc_num_max_gs_thds;
1250 uint8_t gc_gs_table_depth;
1251 uint8_t gc_double_offchip_lds_buffer;
1252 uint8_t gc_max_scratch_slots_per_cu;
Shaoyun Liuf9fb22a2018-05-22 11:45:41 -0400[diff] [blame]1253 uint32_t sram_rm_fuses_val;
1254 uint32_t sram_custom_rm_fuses_val;
Alex Deucher6f687112018-03-15 21:32:27 -0500[diff] [blame]1255};
1256
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1257/*
1258 ***************************************************************************
1259 Data Table smu_info structure
1260 ***************************************************************************
1261*/
1262struct atom_smu_info_v3_1
1263{
1264 struct atom_common_table_header table_header;
1265 uint8_t smuip_min_ver;
1266 uint8_t smuip_max_ver;
1267 uint8_t smu_rsd1;
1268 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1269 uint16_t sclk_ss_percentage;
1270 uint16_t sclk_ss_rate_10hz;
1271 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1272 uint16_t gpuclk_ss_rate_10hz;
1273 uint32_t core_refclk_10khz;
1274 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1275 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1276 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1277 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1278 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1279 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1280 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1281 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1282};
1283
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]1284struct atom_smu_info_v3_2 {
1285 struct atom_common_table_header table_header;
1286 uint8_t smuip_min_ver;
1287 uint8_t smuip_max_ver;
1288 uint8_t smu_rsd1;
1289 uint8_t gpuclk_ss_mode;
1290 uint16_t sclk_ss_percentage;
1291 uint16_t sclk_ss_rate_10hz;
1292 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1293 uint16_t gpuclk_ss_rate_10hz;
1294 uint32_t core_refclk_10khz;
1295 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1296 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1297 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1298 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1299 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1300 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1301 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1302 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1303 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1304 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1305 uint16_t smugoldenoffset;
1306 uint32_t gpupll_vco_freq_10khz;
1307 uint32_t bootup_smnclk_10khz;
1308 uint32_t bootup_socclk_10khz;
1309 uint32_t bootup_mp0clk_10khz;
1310 uint32_t bootup_mp1clk_10khz;
1311 uint32_t bootup_lclk_10khz;
1312 uint32_t bootup_dcefclk_10khz;
1313 uint32_t ctf_threshold_override_value;
1314 uint32_t reserved[5];
1315};
1316
1317struct atom_smu_info_v3_3 {
1318 struct atom_common_table_header table_header;
1319 uint8_t smuip_min_ver;
1320 uint8_t smuip_max_ver;
1321 uint8_t smu_rsd1;
1322 uint8_t gpuclk_ss_mode;
1323 uint16_t sclk_ss_percentage;
1324 uint16_t sclk_ss_rate_10hz;
1325 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1326 uint16_t gpuclk_ss_rate_10hz;
1327 uint32_t core_refclk_10khz;
1328 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1329 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1330 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1331 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1332 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1333 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1334 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1335 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1336 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1337 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1338 uint16_t smugoldenoffset;
1339 uint32_t gpupll_vco_freq_10khz;
1340 uint32_t bootup_smnclk_10khz;
1341 uint32_t bootup_socclk_10khz;
1342 uint32_t bootup_mp0clk_10khz;
1343 uint32_t bootup_mp1clk_10khz;
1344 uint32_t bootup_lclk_10khz;
1345 uint32_t bootup_dcefclk_10khz;
1346 uint32_t ctf_threshold_override_value;
1347 uint32_t syspll3_0_vco_freq_10khz;
1348 uint32_t syspll3_1_vco_freq_10khz;
1349 uint32_t bootup_fclk_10khz;
1350 uint32_t bootup_waflclk_10khz;
1351 uint32_t reserved[3];
1352};
1353
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]1354/*
1355 ***************************************************************************
1356 Data Table smc_dpm_info structure
1357 ***************************************************************************
1358 */
1359struct atom_smc_dpm_info_v4_1
1360{
1361 struct atom_common_table_header table_header;
1362 uint8_t liquid1_i2c_address;
1363 uint8_t liquid2_i2c_address;
1364 uint8_t vr_i2c_address;
1365 uint8_t plx_i2c_address;
1366
1367 uint8_t liquid_i2c_linescl;
1368 uint8_t liquid_i2c_linesda;
1369 uint8_t vr_i2c_linescl;
1370 uint8_t vr_i2c_linesda;
1371
1372 uint8_t plx_i2c_linescl;
1373 uint8_t plx_i2c_linesda;
1374 uint8_t vrsensorpresent;
1375 uint8_t liquidsensorpresent;
1376
1377 uint16_t maxvoltagestepgfx;
1378 uint16_t maxvoltagestepsoc;
1379
1380 uint8_t vddgfxvrmapping;
1381 uint8_t vddsocvrmapping;
1382 uint8_t vddmem0vrmapping;
1383 uint8_t vddmem1vrmapping;
1384
1385 uint8_t gfxulvphasesheddingmask;
1386 uint8_t soculvphasesheddingmask;
1387 uint8_t padding8_v[2];
1388
1389 uint16_t gfxmaxcurrent;
1390 uint8_t gfxoffset;
1391 uint8_t padding_telemetrygfx;
1392
1393 uint16_t socmaxcurrent;
1394 uint8_t socoffset;
1395 uint8_t padding_telemetrysoc;
1396
1397 uint16_t mem0maxcurrent;
1398 uint8_t mem0offset;
1399 uint8_t padding_telemetrymem0;
1400
1401 uint16_t mem1maxcurrent;
1402 uint8_t mem1offset;
1403 uint8_t padding_telemetrymem1;
1404
1405 uint8_t acdcgpio;
1406 uint8_t acdcpolarity;
1407 uint8_t vr0hotgpio;
1408 uint8_t vr0hotpolarity;
1409
1410 uint8_t vr1hotgpio;
1411 uint8_t vr1hotpolarity;
1412 uint8_t padding1;
1413 uint8_t padding2;
1414
1415 uint8_t ledpin0;
1416 uint8_t ledpin1;
1417 uint8_t ledpin2;
1418 uint8_t padding8_4;
1419
Kenneth Feng5d415352018-03-28 17:58:03 +0800[diff] [blame]1420 uint8_t pllgfxclkspreadenabled;
1421 uint8_t pllgfxclkspreadpercent;
1422 uint16_t pllgfxclkspreadfreq;
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]1423
1424 uint8_t uclkspreadenabled;
1425 uint8_t uclkspreadpercent;
1426 uint16_t uclkspreadfreq;
1427
1428 uint8_t socclkspreadenabled;
1429 uint8_t socclkspreadpercent;
1430 uint16_t socclkspreadfreq;
1431
Kenneth Feng5d415352018-03-28 17:58:03 +0800[diff] [blame]1432 uint8_t acggfxclkspreadenabled;
1433 uint8_t acggfxclkspreadpercent;
1434 uint16_t acggfxclkspreadfreq;
1435
1436 uint32_t boardreserved[10];
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]1437};
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1438
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1439/*
1440 ***************************************************************************
1441 Data Table asic_profiling_info structure
1442 ***************************************************************************
1443*/
1444struct atom_asic_profiling_info_v4_1
1445{
1446 struct atom_common_table_header table_header;
1447 uint32_t maxvddc;
1448 uint32_t minvddc;
1449 uint32_t avfs_meannsigma_acontant0;
1450 uint32_t avfs_meannsigma_acontant1;
1451 uint32_t avfs_meannsigma_acontant2;
1452 uint16_t avfs_meannsigma_dc_tol_sigma;
1453 uint16_t avfs_meannsigma_platform_mean;
1454 uint16_t avfs_meannsigma_platform_sigma;
1455 uint32_t gb_vdroop_table_cksoff_a0;
1456 uint32_t gb_vdroop_table_cksoff_a1;
1457 uint32_t gb_vdroop_table_cksoff_a2;
1458 uint32_t gb_vdroop_table_ckson_a0;
1459 uint32_t gb_vdroop_table_ckson_a1;
1460 uint32_t gb_vdroop_table_ckson_a2;
1461 uint32_t avfsgb_fuse_table_cksoff_m1;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1462 uint32_t avfsgb_fuse_table_cksoff_m2;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1463 uint32_t avfsgb_fuse_table_cksoff_b;
1464 uint32_t avfsgb_fuse_table_ckson_m1;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1465 uint32_t avfsgb_fuse_table_ckson_m2;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1466 uint32_t avfsgb_fuse_table_ckson_b;
1467 uint16_t max_voltage_0_25mv;
1468 uint8_t enable_gb_vdroop_table_cksoff;
1469 uint8_t enable_gb_vdroop_table_ckson;
1470 uint8_t enable_gb_fuse_table_cksoff;
1471 uint8_t enable_gb_fuse_table_ckson;
1472 uint16_t psm_age_comfactor;
1473 uint8_t enable_apply_avfs_cksoff_voltage;
1474 uint8_t reserved;
1475 uint32_t dispclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1476 uint32_t dispclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1477 uint32_t dispclk2gfxclk_c;
1478 uint32_t pixclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1479 uint32_t pixclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1480 uint32_t pixclk2gfxclk_c;
1481 uint32_t dcefclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1482 uint32_t dcefclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1483 uint32_t dcefclk2gfxclk_c;
1484 uint32_t phyclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1485 uint32_t phyclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1486 uint32_t phyclk2gfxclk_c;
1487};
1488
Rex Zhub7437502017-06-24 16:45:58 +0800[diff] [blame]1489struct atom_asic_profiling_info_v4_2 {
1490 struct atom_common_table_header table_header;
1491 uint32_t maxvddc;
1492 uint32_t minvddc;
1493 uint32_t avfs_meannsigma_acontant0;
1494 uint32_t avfs_meannsigma_acontant1;
1495 uint32_t avfs_meannsigma_acontant2;
1496 uint16_t avfs_meannsigma_dc_tol_sigma;
1497 uint16_t avfs_meannsigma_platform_mean;
1498 uint16_t avfs_meannsigma_platform_sigma;
1499 uint32_t gb_vdroop_table_cksoff_a0;
1500 uint32_t gb_vdroop_table_cksoff_a1;
1501 uint32_t gb_vdroop_table_cksoff_a2;
1502 uint32_t gb_vdroop_table_ckson_a0;
1503 uint32_t gb_vdroop_table_ckson_a1;
1504 uint32_t gb_vdroop_table_ckson_a2;
1505 uint32_t avfsgb_fuse_table_cksoff_m1;
1506 uint32_t avfsgb_fuse_table_cksoff_m2;
1507 uint32_t avfsgb_fuse_table_cksoff_b;
1508 uint32_t avfsgb_fuse_table_ckson_m1;
1509 uint32_t avfsgb_fuse_table_ckson_m2;
1510 uint32_t avfsgb_fuse_table_ckson_b;
1511 uint16_t max_voltage_0_25mv;
1512 uint8_t enable_gb_vdroop_table_cksoff;
1513 uint8_t enable_gb_vdroop_table_ckson;
1514 uint8_t enable_gb_fuse_table_cksoff;
1515 uint8_t enable_gb_fuse_table_ckson;
1516 uint16_t psm_age_comfactor;
1517 uint8_t enable_apply_avfs_cksoff_voltage;
1518 uint8_t reserved;
1519 uint32_t dispclk2gfxclk_a;
1520 uint32_t dispclk2gfxclk_b;
1521 uint32_t dispclk2gfxclk_c;
1522 uint32_t pixclk2gfxclk_a;
1523 uint32_t pixclk2gfxclk_b;
1524 uint32_t pixclk2gfxclk_c;
1525 uint32_t dcefclk2gfxclk_a;
1526 uint32_t dcefclk2gfxclk_b;
1527 uint32_t dcefclk2gfxclk_c;
1528 uint32_t phyclk2gfxclk_a;
1529 uint32_t phyclk2gfxclk_b;
1530 uint32_t phyclk2gfxclk_c;
1531 uint32_t acg_gb_vdroop_table_a0;
1532 uint32_t acg_gb_vdroop_table_a1;
1533 uint32_t acg_gb_vdroop_table_a2;
1534 uint32_t acg_avfsgb_fuse_table_m1;
1535 uint32_t acg_avfsgb_fuse_table_m2;
1536 uint32_t acg_avfsgb_fuse_table_b;
1537 uint8_t enable_acg_gb_vdroop_table;
1538 uint8_t enable_acg_gb_fuse_table;
1539 uint32_t acg_dispclk2gfxclk_a;
1540 uint32_t acg_dispclk2gfxclk_b;
1541 uint32_t acg_dispclk2gfxclk_c;
1542 uint32_t acg_pixclk2gfxclk_a;
1543 uint32_t acg_pixclk2gfxclk_b;
1544 uint32_t acg_pixclk2gfxclk_c;
1545 uint32_t acg_dcefclk2gfxclk_a;
1546 uint32_t acg_dcefclk2gfxclk_b;
1547 uint32_t acg_dcefclk2gfxclk_c;
1548 uint32_t acg_phyclk2gfxclk_a;
1549 uint32_t acg_phyclk2gfxclk_b;
1550 uint32_t acg_phyclk2gfxclk_c;
1551};
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1552
1553/*
1554 ***************************************************************************
1555 Data Table multimedia_info structure
1556 ***************************************************************************
1557*/
1558struct atom_multimedia_info_v2_1
1559{
1560 struct atom_common_table_header table_header;
1561 uint8_t uvdip_min_ver;
1562 uint8_t uvdip_max_ver;
1563 uint8_t vceip_min_ver;
1564 uint8_t vceip_max_ver;
1565 uint16_t uvd_enc_max_input_width_pixels;
1566 uint16_t uvd_enc_max_input_height_pixels;
1567 uint16_t vce_enc_max_input_width_pixels;
1568 uint16_t vce_enc_max_input_height_pixels;
1569 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1570 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1571};
1572
1573
1574/*
1575 ***************************************************************************
1576 Data Table umc_info structure
1577 ***************************************************************************
1578*/
1579struct atom_umc_info_v3_1
1580{
1581 struct atom_common_table_header table_header;
1582 uint32_t ucode_version;
1583 uint32_t ucode_rom_startaddr;
1584 uint32_t ucode_length;
1585 uint16_t umc_reg_init_offset;
1586 uint16_t customer_ucode_name_offset;
1587 uint16_t mclk_ss_percentage;
1588 uint16_t mclk_ss_rate_10hz;
1589 uint8_t umcip_min_ver;
1590 uint8_t umcip_max_ver;
1591 uint8_t vram_type; //enum of atom_dgpu_vram_type
1592 uint8_t umc_config;
1593 uint32_t mem_refclk_10khz;
1594};
1595
1596
1597/*
1598 ***************************************************************************
1599 Data Table vram_info structure
1600 ***************************************************************************
1601*/
1602struct atom_vram_module_v9
1603{
1604 // Design Specific Values
1605 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1606 uint32_t channel_enable; // for 32 channel ASIC usage
1607 uint32_t umcch_addrcfg;
1608 uint32_t umcch_addrsel;
1609 uint32_t umcch_colsel;
1610 uint16_t vram_module_size; // Size of atom_vram_module_v9
1611 uint8_t ext_memory_id; // Current memory module ID
1612 uint8_t memory_type; // enum of atom_dgpu_vram_type
1613 uint8_t channel_num; // Number of mem. channels supported in this module
1614 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1615 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1616 uint8_t tunningset_id; // MC phy registers set per.
1617 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
1618 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1619 uint16_t vram_rsd2; // reserved
1620 char dram_pnstring[20]; // part number end with '0'.
1621};
1622
1623
1624struct atom_vram_info_header_v2_3
1625{
1626 struct atom_common_table_header table_header;
1627 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
1628 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
1629 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
1630 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
1631 uint16_t dram_data_remap_tbloffset; // reserved for now
1632 uint16_t vram_rsd2[3];
1633 uint8_t vram_module_num; // indicate number of VRAM module
1634 uint8_t vram_rsd1[2];
1635 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
1636 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
1637};
1638
1639struct atom_umc_register_addr_info{
1640 uint32_t umc_register_addr:24;
1641 uint32_t umc_reg_type_ind:1;
1642 uint32_t umc_reg_rsvd:7;
1643};
1644
1645//atom_umc_register_addr_info.
1646enum atom_umc_register_addr_info_flag{
1647 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
1648};
1649
1650union atom_umc_register_addr_info_access
1651{
1652 struct atom_umc_register_addr_info umc_reg_addr;
1653 uint32_t u32umc_reg_addr;
1654};
1655
1656struct atom_umc_reg_setting_id_config{
1657 uint32_t memclockrange:24;
1658 uint32_t mem_blk_id:8;
1659};
1660
1661union atom_umc_reg_setting_id_config_access
1662{
1663 struct atom_umc_reg_setting_id_config umc_id_access;
1664 uint32_t u32umc_id_access;
1665};
1666
1667struct atom_umc_reg_setting_data_block{
1668 union atom_umc_reg_setting_id_config_access block_id;
1669 uint32_t u32umc_reg_data[1];
1670};
1671
1672struct atom_umc_init_reg_block{
1673 uint16_t umc_reg_num;
1674 uint16_t reserved;
1675 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
1676 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
1677};
1678
1679
1680/*
1681 ***************************************************************************
1682 Data Table voltageobject_info structure
1683 ***************************************************************************
1684*/
1685struct atom_i2c_data_entry
1686{
1687 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
1688 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
1689};
1690
1691struct atom_voltage_object_header_v4{
1692 uint8_t voltage_type; //enum atom_voltage_type
1693 uint8_t voltage_mode; //enum atom_voltage_object_mode
1694 uint16_t object_size; //Size of Object
1695};
1696
1697// atom_voltage_object_header_v4.voltage_mode
1698enum atom_voltage_object_mode
1699{
1700 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
1701 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
1702 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
1703 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
1704 VOLTAGE_OBJ_EVV = 8,
1705 VOLTAGE_OBJ_MERGED_POWER = 9,
1706};
1707
1708struct atom_i2c_voltage_object_v4
1709{
1710 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
1711 uint8_t regulator_id; //Indicate Voltage Regulator Id
1712 uint8_t i2c_id;
1713 uint8_t i2c_slave_addr;
1714 uint8_t i2c_control_offset;
1715 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
1716 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
1717 uint8_t reserved[2];
1718 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
1719};
1720
1721// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
1722enum atom_i2c_voltage_control_flag
1723{
1724 VOLTAGE_DATA_ONE_BYTE = 0,
1725 VOLTAGE_DATA_TWO_BYTE = 1,
1726};
1727
1728
1729struct atom_voltage_gpio_map_lut
1730{
1731 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
1732 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
1733};
1734
1735struct atom_gpio_voltage_object_v4
1736{
1737 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
1738 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
1739 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
1740 uint8_t phase_delay_us; // phase delay in unit of micro second
1741 uint8_t reserved;
1742 uint32_t gpio_mask_val; // GPIO Mask value
1743 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
1744};
1745
1746struct atom_svid2_voltage_object_v4
1747{
1748 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
1749 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
1750 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
1751 uint8_t psi0_enable; //
1752 uint8_t maxvstep;
1753 uint8_t telemetry_offset;
1754 uint8_t telemetry_gain;
1755 uint16_t reserved1;
1756};
1757
1758struct atom_merged_voltage_object_v4
1759{
1760 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
1761 uint8_t merged_powerrail_type; //enum atom_voltage_type
1762 uint8_t reserved[3];
1763};
1764
1765union atom_voltage_object_v4{
1766 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
1767 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
1768 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
1769 struct atom_merged_voltage_object_v4 merged_voltage_obj;
1770};
1771
1772struct atom_voltage_objects_info_v4_1
1773{
1774 struct atom_common_table_header table_header;
1775 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
1776};
1777
1778
1779/*
1780 ***************************************************************************
1781 All Command Function structure definition
1782 ***************************************************************************
1783*/
1784
1785/*
1786 ***************************************************************************
1787 Structures used by asic_init
1788 ***************************************************************************
1789*/
1790
1791struct asic_init_engine_parameters
1792{
1793 uint32_t sclkfreqin10khz:24;
1794 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
1795};
1796
1797struct asic_init_mem_parameters
1798{
1799 uint32_t mclkfreqin10khz:24;
1800 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
1801};
1802
1803struct asic_init_parameters_v2_1
1804{
1805 struct asic_init_engine_parameters engineparam;
1806 struct asic_init_mem_parameters memparam;
1807};
1808
1809struct asic_init_ps_allocation_v2_1
1810{
1811 struct asic_init_parameters_v2_1 param;
1812 uint32_t reserved[16];
1813};
1814
1815
1816enum atom_asic_init_engine_flag
1817{
1818 b3NORMAL_ENGINE_INIT = 0,
1819 b3SRIOV_SKIP_ASIC_INIT = 0x02,
1820 b3SRIOV_LOAD_UCODE = 0x40,
1821};
1822
1823enum atom_asic_init_mem_flag
1824{
1825 b3NORMAL_MEM_INIT = 0,
1826 b3DRAM_SELF_REFRESH_EXIT =0x20,
1827};
1828
1829/*
1830 ***************************************************************************
1831 Structures used by setengineclock
1832 ***************************************************************************
1833*/
1834
1835struct set_engine_clock_parameters_v2_1
1836{
1837 uint32_t sclkfreqin10khz:24;
1838 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
1839 uint32_t reserved[10];
1840};
1841
1842struct set_engine_clock_ps_allocation_v2_1
1843{
1844 struct set_engine_clock_parameters_v2_1 clockinfo;
1845 uint32_t reserved[10];
1846};
1847
1848
1849enum atom_set_engine_mem_clock_flag
1850{
1851 b3NORMAL_CHANGE_CLOCK = 0,
1852 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
1853 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
1854};
1855
1856/*
1857 ***************************************************************************
1858 Structures used by getengineclock
1859 ***************************************************************************
1860*/
1861struct get_engine_clock_parameter
1862{
1863 uint32_t sclk_10khz; // current engine speed in 10KHz unit
1864 uint32_t reserved;
1865};
1866
1867/*
1868 ***************************************************************************
1869 Structures used by setmemoryclock
1870 ***************************************************************************
1871*/
1872struct set_memory_clock_parameters_v2_1
1873{
1874 uint32_t mclkfreqin10khz:24;
1875 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
1876 uint32_t reserved[10];
1877};
1878
1879struct set_memory_clock_ps_allocation_v2_1
1880{
1881 struct set_memory_clock_parameters_v2_1 clockinfo;
1882 uint32_t reserved[10];
1883};
1884
1885
1886/*
1887 ***************************************************************************
1888 Structures used by getmemoryclock
1889 ***************************************************************************
1890*/
1891struct get_memory_clock_parameter
1892{
1893 uint32_t mclk_10khz; // current engine speed in 10KHz unit
1894 uint32_t reserved;
1895};
1896
1897
1898
1899/*
1900 ***************************************************************************
1901 Structures used by setvoltage
1902 ***************************************************************************
1903*/
1904
1905struct set_voltage_parameters_v1_4
1906{
1907 uint8_t voltagetype; /* enum atom_voltage_type */
1908 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
1909 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
1910};
1911
1912//set_voltage_parameters_v2_1.voltagemode
1913enum atom_set_voltage_command{
1914 ATOM_SET_VOLTAGE = 0,
1915 ATOM_INIT_VOLTAGE_REGULATOR = 3,
1916 ATOM_SET_VOLTAGE_PHASE = 4,
1917 ATOM_GET_LEAKAGE_ID = 8,
1918};
1919
1920struct set_voltage_ps_allocation_v1_4
1921{
1922 struct set_voltage_parameters_v1_4 setvoltageparam;
1923 uint32_t reserved[10];
1924};
1925
1926
1927/*
1928 ***************************************************************************
1929 Structures used by computegpuclockparam
1930 ***************************************************************************
1931*/
1932
1933//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
1934enum atom_gpu_clock_type
1935{
1936 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
1937 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
1938 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
1939};
1940
1941struct compute_gpu_clock_input_parameter_v1_8
1942{
1943 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
1944 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
1945 uint32_t reserved[5];
1946};
1947
1948
1949struct compute_gpu_clock_output_parameter_v1_8
1950{
1951 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
1952 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
1953 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
1954 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
1955 uint16_t pll_ss_slew_frac;
1956 uint8_t pll_ss_enable;
1957 uint8_t reserved;
1958 uint32_t reserved1[2];
1959};
1960
1961
1962
1963/*
1964 ***************************************************************************
1965 Structures used by ReadEfuseValue
1966 ***************************************************************************
1967*/
1968
1969struct read_efuse_input_parameters_v3_1
1970{
1971 uint16_t efuse_start_index;
1972 uint8_t reserved;
1973 uint8_t bitslen;
1974};
1975
1976// ReadEfuseValue input/output parameter
1977union read_efuse_value_parameters_v3_1
1978{
1979 struct read_efuse_input_parameters_v3_1 efuse_info;
1980 uint32_t efusevalue;
1981};
1982
1983
1984/*
1985 ***************************************************************************
1986 Structures used by getsmuclockinfo
1987 ***************************************************************************
1988*/
1989struct atom_get_smu_clock_info_parameters_v3_1
1990{
1991 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
1992 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1993 uint8_t command; // enum of atom_get_smu_clock_info_command
1994 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1995};
1996
1997enum atom_get_smu_clock_info_command
1998{
1999 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
2000 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
2001 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
2002};
2003
2004enum atom_smu9_syspll0_clock_id
2005{
2006 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
2007 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
2008 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2009 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
2010 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
2011 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
2012 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
2013 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
2014 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
2015 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
2016 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
2017};
2018
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]2019enum atom_smu11_syspll_id {
2020 SMU11_SYSPLL0_ID = 0,
2021 SMU11_SYSPLL1_0_ID = 1,
2022 SMU11_SYSPLL1_1_ID = 2,
2023 SMU11_SYSPLL1_2_ID = 3,
2024 SMU11_SYSPLL2_ID = 4,
2025 SMU11_SYSPLL3_0_ID = 5,
2026 SMU11_SYSPLL3_1_ID = 6,
2027};
2028
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]2029enum atom_smu11_syspll0_clock_id {
Evan Quanee7a99c2018-05-28 08:53:03 +0800[diff] [blame]2030 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
2031 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
2032 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2033 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
2034 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]2035 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2036};
2037
Jerry (Fangzhi) Zuo3aabfcd2018-03-05 14:59:57 -0500[diff] [blame]2038enum atom_smu11_syspll1_0_clock_id {
2039 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2040};
2041
2042enum atom_smu11_syspll1_1_clock_id {
2043 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2044};
2045
2046enum atom_smu11_syspll1_2_clock_id {
2047 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2048};
2049
2050enum atom_smu11_syspll2_clock_id {
2051 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2052};
2053
2054enum atom_smu11_syspll3_0_clock_id {
2055 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2056 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2057 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2058};
2059
2060enum atom_smu11_syspll3_1_clock_id {
2061 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2062 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2063 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2064};
2065
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]2066struct atom_get_smu_clock_info_output_parameters_v3_1
2067{
2068 union {
2069 uint32_t smu_clock_freq_hz;
2070 uint32_t syspllvcofreq_10khz;
2071 uint32_t sysspllrefclk_10khz;
2072 }atom_smu_outputclkfreq;
2073};
2074
2075
2076
2077/*
2078 ***************************************************************************
2079 Structures used by dynamicmemorysettings
2080 ***************************************************************************
2081*/
2082
2083enum atom_dynamic_memory_setting_command
2084{
2085 COMPUTE_MEMORY_PLL_PARAM = 1,
2086 COMPUTE_ENGINE_PLL_PARAM = 2,
2087 ADJUST_MC_SETTING_PARAM = 3,
2088};
2089
2090/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
2091struct dynamic_mclk_settings_parameters_v2_1
2092{
2093 uint32_t mclk_10khz:24; //Input= target mclk
2094 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2095 uint32_t reserved;
2096};
2097
2098/* when command = COMPUTE_ENGINE_PLL_PARAM */
2099struct dynamic_sclk_settings_parameters_v2_1
2100{
2101 uint32_t sclk_10khz:24; //Input= target mclk
2102 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2103 uint32_t mclk_10khz;
2104 uint32_t reserved;
2105};
2106
2107union dynamic_memory_settings_parameters_v2_1
2108{
2109 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
2110 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
2111};
2112
2113
2114
2115/*
2116 ***************************************************************************
2117 Structures used by memorytraining
2118 ***************************************************************************
2119*/
2120
2121enum atom_umc6_0_ucode_function_call_enum_id
2122{
2123 UMC60_UCODE_FUNC_ID_REINIT = 0,
2124 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
2125 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
2126};
2127
2128
2129struct memory_training_parameters_v2_1
2130{
2131 uint8_t ucode_func_id;
2132 uint8_t ucode_reserved[3];
2133 uint32_t reserved[5];
2134};
2135
2136
2137/*
2138 ***************************************************************************
2139 Structures used by setpixelclock
2140 ***************************************************************************
2141*/
2142
2143struct set_pixel_clock_parameter_v1_7
2144{
2145 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2146
2147 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2148 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2149 // indicate which graphic encoder will be used.
2150 uint8_t encoder_mode; // Encoder mode:
2151 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2152 uint8_t crtc_id; // enum of atom_crtc_def
2153 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2154 uint8_t reserved1[2];
2155 uint32_t reserved2;
2156};
2157
2158//ucMiscInfo
2159enum atom_set_pixel_clock_v1_7_misc_info
2160{
2161 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
2162 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
2163 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
2164 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
2165 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
2166 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
2167 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
2168 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
2169 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
2170 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
2171 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
2172};
2173
2174/* deep_color_ratio */
2175enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2176{
2177 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2178 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2179 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2180 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2181};
2182
2183/*
2184 ***************************************************************************
2185 Structures used by setdceclock
2186 ***************************************************************************
2187*/
2188
2189// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
2190struct set_dce_clock_parameters_v2_1
2191{
2192 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2193 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2194 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2195 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2196 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2197};
2198
2199//ucDCEClkType
2200enum atom_set_dce_clock_clock_type
2201{
2202 DCE_CLOCK_TYPE_DISPCLK = 0,
2203 DCE_CLOCK_TYPE_DPREFCLK = 1,
2204 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
2205};
2206
2207//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2208enum atom_set_dce_clock_dprefclk_flag
2209{
2210 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2211 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2212 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2213 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2214 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2215};
2216
2217//ucDCEClkFlag when ucDCEClkType == PIXCLK
2218enum atom_set_dce_clock_pixclk_flag
2219{
2220 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2221 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2222 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2223 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2224 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2225 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2226};
2227
2228struct set_dce_clock_ps_allocation_v2_1
2229{
2230 struct set_dce_clock_parameters_v2_1 param;
2231 uint32_t ulReserved[2];
2232};
2233
2234
2235/****************************************************************************/
2236// Structures used by BlankCRTC
2237/****************************************************************************/
2238struct blank_crtc_parameters
2239{
2240 uint8_t crtc_id; // enum atom_crtc_def
2241 uint8_t blanking; // enum atom_blank_crtc_command
2242 uint16_t reserved;
2243 uint32_t reserved1;
2244};
2245
2246enum atom_blank_crtc_command
2247{
2248 ATOM_BLANKING = 1,
2249 ATOM_BLANKING_OFF = 0,
2250};
2251
2252/****************************************************************************/
2253// Structures used by enablecrtc
2254/****************************************************************************/
2255struct enable_crtc_parameters
2256{
2257 uint8_t crtc_id; // enum atom_crtc_def
2258 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2259 uint8_t padding[2];
2260};
2261
2262
2263/****************************************************************************/
2264// Structure used by EnableDispPowerGating
2265/****************************************************************************/
2266struct enable_disp_power_gating_parameters_v2_1
2267{
2268 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2269 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2270 uint8_t padding[2];
2271};
2272
2273struct enable_disp_power_gating_ps_allocation
2274{
2275 struct enable_disp_power_gating_parameters_v2_1 param;
2276 uint32_t ulReserved[4];
2277};
2278
2279/****************************************************************************/
2280// Structure used in setcrtc_usingdtdtiming
2281/****************************************************************************/
2282struct set_crtc_using_dtd_timing_parameters
2283{
2284 uint16_t h_size;
2285 uint16_t h_blanking_time;
2286 uint16_t v_size;
2287 uint16_t v_blanking_time;
2288 uint16_t h_syncoffset;
2289 uint16_t h_syncwidth;
2290 uint16_t v_syncoffset;
2291 uint16_t v_syncwidth;
2292 uint16_t modemiscinfo;
2293 uint8_t h_border;
2294 uint8_t v_border;
2295 uint8_t crtc_id; // enum atom_crtc_def
2296 uint8_t encoder_mode; // atom_encode_mode_def
2297 uint8_t padding[2];
2298};
2299
2300
2301/****************************************************************************/
2302// Structures used by processi2cchanneltransaction
2303/****************************************************************************/
2304struct process_i2c_channel_transaction_parameters
2305{
2306 uint8_t i2cspeed_khz;
2307 union {
2308 uint8_t regindex;
2309 uint8_t status; /* enum atom_process_i2c_flag */
2310 } regind_status;
2311 uint16_t i2c_data_out;
2312 uint8_t flag; /* enum atom_process_i2c_status */
2313 uint8_t trans_bytes;
2314 uint8_t slave_addr;
2315 uint8_t i2c_id;
2316};
2317
2318//ucFlag
2319enum atom_process_i2c_flag
2320{
2321 HW_I2C_WRITE = 1,
2322 HW_I2C_READ = 0,
2323 I2C_2BYTE_ADDR = 0x02,
2324 HW_I2C_SMBUS_BYTE_WR = 0x04,
2325};
2326
2327//status
2328enum atom_process_i2c_status
2329{
2330 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2331 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2332};
2333
2334
2335/****************************************************************************/
2336// Structures used by processauxchanneltransaction
2337/****************************************************************************/
2338
2339struct process_aux_channel_transaction_parameters_v1_2
2340{
2341 uint16_t aux_request;
2342 uint16_t dataout;
2343 uint8_t channelid;
2344 union {
2345 uint8_t reply_status;
2346 uint8_t aux_delay;
2347 } aux_status_delay;
2348 uint8_t dataout_len;
2349 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2350};
2351
2352
2353/****************************************************************************/
2354// Structures used by selectcrtc_source
2355/****************************************************************************/
2356
2357struct select_crtc_source_parameters_v2_3
2358{
2359 uint8_t crtc_id; // enum atom_crtc_def
2360 uint8_t encoder_id; // enum atom_dig_def
2361 uint8_t encode_mode; // enum atom_encode_mode_def
2362 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2363};
2364
2365
2366/****************************************************************************/
2367// Structures used by digxencodercontrol
2368/****************************************************************************/
2369
2370// ucAction:
2371enum atom_dig_encoder_control_action
2372{
2373 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2374 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2375 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2376 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2377 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2378 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2379 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2380 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2381 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2382 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2383 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2384 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2385 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2386 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2387};
2388
2389//define ucPanelMode
2390enum atom_dig_encoder_control_panelmode
2391{
2392 DP_PANEL_MODE_DISABLE = 0x00,
2393 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2394 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2395};
2396
2397//ucDigId
2398enum atom_dig_encoder_control_v5_digid
2399{
2400 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2401 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2402 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2403 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2404 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2405 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2406 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2407 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2408};
2409
2410struct dig_encoder_stream_setup_parameters_v1_5
2411{
2412 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2413 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2414 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2415 uint8_t lanenum; // Lane number
2416 uint32_t pclk_10khz; // Pixel Clock in 10Khz
2417 uint8_t bitpercolor;
2418 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2419 uint8_t reserved[2];
2420};
2421
2422struct dig_encoder_link_setup_parameters_v1_5
2423{
2424 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2425 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2426 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2427 uint8_t lanenum; // Lane number
2428 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2429 uint8_t hpd_sel;
2430 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2431 uint8_t reserved[2];
2432};
2433
2434struct dp_panel_mode_set_parameters_v1_5
2435{
2436 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2437 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2438 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2439 uint8_t reserved1;
2440 uint32_t reserved2[2];
2441};
2442
2443struct dig_encoder_generic_cmd_parameters_v1_5
2444{
2445 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2446 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2447 uint8_t reserved1[2];
2448 uint32_t reserved2[2];
2449};
2450
2451union dig_encoder_control_parameters_v1_5
2452{
2453 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
2454 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2455 struct dig_encoder_link_setup_parameters_v1_5 link_param;
2456 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2457};
2458
2459/*
2460 ***************************************************************************
2461 Structures used by dig1transmittercontrol
2462 ***************************************************************************
2463*/
2464struct dig_transmitter_control_parameters_v1_6
2465{
2466 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2467 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
2468 union {
2469 uint8_t digmode; // enum atom_encode_mode_def
2470 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
2471 } mode_laneset;
2472 uint8_t lanenum; // Lane number 1, 2, 4, 8
2473 uint32_t symclk_10khz; // Symbol Clock in 10Khz
2474 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2475 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2476 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
2477 uint8_t reserved;
2478 uint32_t reserved1;
2479};
2480
2481struct dig_transmitter_control_ps_allocation_v1_6
2482{
2483 struct dig_transmitter_control_parameters_v1_6 param;
2484 uint32_t reserved[4];
2485};
2486
2487//ucAction
2488enum atom_dig_transmitter_control_action
2489{
2490 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
2491 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
2492 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
2493 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
2494 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
2495 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
2496 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
2497 ATOM_TRANSMITTER_ACTION_INIT = 7,
2498 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
2499 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
2500 ATOM_TRANSMITTER_ACTION_SETUP = 10,
2501 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
2502 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
2503 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
2504};
2505
2506// digfe_sel
2507enum atom_dig_transmitter_control_digfe_sel
2508{
2509 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
2510 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
2511 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
2512 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
2513 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
2514 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
2515 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
2516};
2517
2518
2519//ucHPDSel
2520enum atom_dig_transmitter_control_hpd_sel
2521{
2522 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
2523 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
2524 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
2525 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
2526 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
2527 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
2528 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
2529};
2530
2531// ucDPLaneSet
2532enum atom_dig_transmitter_control_dplaneset
2533{
2534 DP_LANE_SET__0DB_0_4V = 0x00,
2535 DP_LANE_SET__0DB_0_6V = 0x01,
2536 DP_LANE_SET__0DB_0_8V = 0x02,
2537 DP_LANE_SET__0DB_1_2V = 0x03,
2538 DP_LANE_SET__3_5DB_0_4V = 0x08,
2539 DP_LANE_SET__3_5DB_0_6V = 0x09,
2540 DP_LANE_SET__3_5DB_0_8V = 0x0a,
2541 DP_LANE_SET__6DB_0_4V = 0x10,
2542 DP_LANE_SET__6DB_0_6V = 0x11,
2543 DP_LANE_SET__9_5DB_0_4V = 0x18,
2544};
2545
2546
2547
2548/****************************************************************************/
2549// Structures used by ExternalEncoderControl V2.4
2550/****************************************************************************/
2551
2552struct external_encoder_control_parameters_v2_4
2553{
2554 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
2555 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
2556 uint8_t action; //
2557 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2558 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2559 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
2560 uint8_t hpd_id;
2561};
2562
2563
2564// ucAction
2565enum external_encoder_control_action_def
2566{
2567 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
2568 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
2569 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
2570 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
2571 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
2572 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
2573 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
2574 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
2575};
2576
2577// ucConfig
2578enum external_encoder_control_v2_4_config_def
2579{
2580 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
2581 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
2582 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
2583 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
2584 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
2585 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
2586 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
2587 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
2588 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
2589};
2590
2591struct external_encoder_control_ps_allocation_v2_4
2592{
2593 struct external_encoder_control_parameters_v2_4 sExtEncoder;
2594 uint32_t reserved[2];
2595};
2596
2597
2598/*
2599 ***************************************************************************
2600 AMD ACPI Table
2601
2602 ***************************************************************************
2603*/
2604
2605struct amd_acpi_description_header{
2606 uint32_t signature;
2607 uint32_t tableLength; //Length
2608 uint8_t revision;
2609 uint8_t checksum;
2610 uint8_t oemId[6];
2611 uint8_t oemTableId[8]; //UINT64 OemTableId;
2612 uint32_t oemRevision;
2613 uint32_t creatorId;
2614 uint32_t creatorRevision;
2615};
2616
2617struct uefi_acpi_vfct{
2618 struct amd_acpi_description_header sheader;
2619 uint8_t tableUUID[16]; //0x24
2620 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
2621 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
2622 uint32_t reserved[4]; //0x3C
2623};
2624
2625struct vfct_image_header{
2626 uint32_t pcibus; //0x4C
2627 uint32_t pcidevice; //0x50
2628 uint32_t pcifunction; //0x54
2629 uint16_t vendorid; //0x58
2630 uint16_t deviceid; //0x5A
2631 uint16_t ssvid; //0x5C
2632 uint16_t ssid; //0x5E
2633 uint32_t revision; //0x60
2634 uint32_t imagelength; //0x64
2635};
2636
2637
2638struct gop_vbios_content {
2639 struct vfct_image_header vbiosheader;
2640 uint8_t vbioscontent[1];
2641};
2642
2643struct gop_lib1_content {
2644 struct vfct_image_header lib1header;
2645 uint8_t lib1content[1];
2646};
2647
2648
2649
2650/*
2651 ***************************************************************************
2652 Scratch Register definitions
2653 Each number below indicates which scratch regiser request, Active and
2654 Connect all share the same definitions as display_device_tag defines
2655 ***************************************************************************
2656*/
2657
2658enum scratch_register_def{
2659 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
2660 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
2661 ATOM_ACTIVE_INFO_DEF = 3,
2662 ATOM_LCD_INFO_DEF = 4,
2663 ATOM_DEVICE_REQ_INFO_DEF = 5,
2664 ATOM_ACC_CHANGE_INFO_DEF = 6,
2665 ATOM_PRE_OS_MODE_INFO_DEF = 7,
2666 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
2667 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
2668};
2669
2670enum scratch_device_connect_info_bit_def{
2671 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
2672 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
2673 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
2674 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
2675 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
2676 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
2677 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
2678 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
2679 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
2680};
2681
2682enum scratch_bl_bri_level_info_bit_def{
2683 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
2684#ifndef _H2INC
2685 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
2686 ATOM_DEVICE_DPMS_STATE =0x00010000,
2687#endif
2688};
2689
2690enum scratch_active_info_bits_def{
2691 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
2692 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
2693 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
2694 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
2695 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
2696 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
2697 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
2698 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
2699};
2700
2701enum scratch_device_req_info_bits_def{
2702 ATOM_DISPLAY_LCD1_REQ =0x0002,
2703 ATOM_DISPLAY_DFP1_REQ =0x0008,
2704 ATOM_DISPLAY_DFP2_REQ =0x0080,
2705 ATOM_DISPLAY_DFP3_REQ =0x0200,
2706 ATOM_DISPLAY_DFP4_REQ =0x0400,
2707 ATOM_DISPLAY_DFP5_REQ =0x0800,
2708 ATOM_DISPLAY_DFP6_REQ =0x0040,
2709 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
2710};
2711
2712enum scratch_acc_change_info_bitshift_def{
2713 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
2714 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
2715};
2716
2717enum scratch_acc_change_info_bits_def{
2718 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
2719 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
2720};
2721
2722enum scratch_pre_os_mode_info_bits_def{
2723 ATOM_PRE_OS_MODE_MASK =0x00000003,
2724 ATOM_PRE_OS_MODE_VGA =0x00000000,
2725 ATOM_PRE_OS_MODE_VESA =0x00000001,
2726 ATOM_PRE_OS_MODE_GOP =0x00000002,
2727 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
2728 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
2729 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
2730 ATOM_ASIC_INIT_COMPLETE =0x00000200,
2731#ifndef _H2INC
2732 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
2733#endif
2734};
2735
2736
2737
2738/*
2739 ***************************************************************************
2740 ATOM firmware ID header file
2741 !! Please keep it at end of the atomfirmware.h !!
2742 ***************************************************************************
2743*/
2744#include "atomfirmwareid.h"
2745#pragma pack()
2746
2747#endif
2748