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gerrit-public.fairphone.software / kernel / msm-5.4 / c72544d85fd6e46cfca6056ba775a17dc272d810 / . / arch / powerpc / kvm / book3s_hv_interrupts.S
blob: 404deb512844424d07bba8ead5bd77e70aee82af [file] [log] [blame]
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
16 *
17 * Derived from book3s_interrupts.S, which is:
18 * Copyright SUSE Linux Products GmbH 2009
19 *
20 * Authors: Alexander Graf <agraf@suse.de>
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/page.h>
27#include <asm/asm-offsets.h>
28#include <asm/exception-64s.h>
29#include <asm/ppc-opcode.h>
30
31/*****************************************************************************
32 * *
33 * Guest entry / exit code that is in kernel module memory (vmalloc) *
34 * *
35 ****************************************************************************/
36
37/* Registers:
Paul Mackerrase0b7ec02014-01-08 21:25:20 +1100[diff] [blame]38 * none
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]39 */
40_GLOBAL(__kvmppc_vcore_entry)
41
42 /* Write correct stack frame */
43 mflr r0
44 std r0,PPC_LR_STKOFF(r1)
45
46 /* Save host state to the stack */
47 stdu r1, -SWITCH_FRAME_SIZE(r1)
48
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]49 /* Save non-volatile registers (r14 - r31) and CR */
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]50 SAVE_NVGPRS(r1)
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]51 mfcr r3
52 std r3, _CCR(r1)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]53
54 /* Save host DSCR */
55 mfspr r3, SPRN_DSCR
56 std r3, HSTATE_DSCR(r13)
57
Michael Neulingeee7ff92014-01-08 21:25:19 +1100[diff] [blame]58BEGIN_FTR_SECTION
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]59 /* Save host DABR */
60 mfspr r3, SPRN_DABR
61 std r3, HSTATE_DABR(r13)
Michael Neulingeee7ff92014-01-08 21:25:19 +1100[diff] [blame]62END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]63
64 /* Hard-disable interrupts */
65 mfmsr r10
66 std r10, HSTATE_HOST_MSR(r13)
67 rldicl r10,r10,48,1
68 rotldi r10,r10,16
69 mtmsrd r10,1
70
Paul Mackerras89436332012-03-02 01:38:23 +0000[diff] [blame]71 /* Save host PMU registers */
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]72BEGIN_FTR_SECTION
73 /* Work around P8 PMAE bug */
74 li r3, -1
75 clrrdi r3, r3, 10
76 mfspr r8, SPRN_MMCR2
77 mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
78 isync
79END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]80 li r3, 1
81 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
82 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
83 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
Paul Mackerras89436332012-03-02 01:38:23 +0000[diff] [blame]84 mfspr r6, SPRN_MMCRA
Paul Mackerrasc17b98c2014-12-03 13:30:38 +1100[diff] [blame]85 /* Clear MMCRA in order to disable SDAR updates */
Paul Mackerras89436332012-03-02 01:38:23 +0000[diff] [blame]86 li r5, 0
87 mtspr SPRN_MMCRA, r5
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]88 isync
89 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
90 lbz r5, LPPACA_PMCINUSE(r3)
91 cmpwi r5, 0
92 beq 31f /* skip if not */
93 mfspr r5, SPRN_MMCR1
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]94 mfspr r9, SPRN_SIAR
95 mfspr r10, SPRN_SDAR
Michael Ellerman9a4fc4e2014-07-10 19:34:31 +1000[diff] [blame]96 std r7, HSTATE_MMCR0(r13)
97 std r5, HSTATE_MMCR1(r13)
98 std r6, HSTATE_MMCRA(r13)
99 std r9, HSTATE_SIAR(r13)
100 std r10, HSTATE_SDAR(r13)
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]101BEGIN_FTR_SECTION
102 mfspr r9, SPRN_SIER
Michael Ellerman9a4fc4e2014-07-10 19:34:31 +1000[diff] [blame]103 std r8, HSTATE_MMCR2(r13)
104 std r9, HSTATE_SIER(r13)
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]105END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]106 mfspr r3, SPRN_PMC1
107 mfspr r5, SPRN_PMC2
108 mfspr r6, SPRN_PMC3
109 mfspr r7, SPRN_PMC4
110 mfspr r8, SPRN_PMC5
111 mfspr r9, SPRN_PMC6
Michael Ellerman9a4fc4e2014-07-10 19:34:31 +1000[diff] [blame]112 stw r3, HSTATE_PMC1(r13)
113 stw r5, HSTATE_PMC2(r13)
114 stw r6, HSTATE_PMC3(r13)
115 stw r7, HSTATE_PMC4(r13)
116 stw r8, HSTATE_PMC5(r13)
117 stw r9, HSTATE_PMC6(r13)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]11831:
119
120 /*
121 * Put whatever is in the decrementer into the
122 * hypervisor decrementer.
123 */
Paul Mackerras2f272462017-05-22 16:25:14 +1000[diff] [blame]124BEGIN_FTR_SECTION
125 ld r5, HSTATE_KVM_VCORE(r13)
126 ld r6, VCORE_KVM(r5)
127 ld r9, KVM_HOST_LPCR(r6)
128 andis. r9, r9, LPCR_LD@h
129END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]130 mfspr r8,SPRN_DEC
131 mftb r7
Paul Mackerras2f272462017-05-22 16:25:14 +1000[diff] [blame]132BEGIN_FTR_SECTION
133 /* On POWER9, don't sign-extend if host LPCR[LD] bit is set */
134 bne 32f
135END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]136 extsw r8,r8
Paul Mackerras2f272462017-05-22 16:25:14 +1000[diff] [blame]13732: mtspr SPRN_HDEC,r8
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]138 add r8,r8,r7
139 std r8,HSTATE_DECEXP(r13)
140
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]141 /* Jump to partition switch code */
Anton Blanchardb1576fe2014-02-04 16:04:35 +1100[diff] [blame]142 bl kvmppc_hv_entry_trampoline
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]143 nop
144
145/*
146 * We return here in virtual mode after the guest exits
147 * with something that we can't handle in real mode.
148 * Interrupts are enabled again at this point.
149 */
150
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]151 /*
152 * Register usage at this point:
153 *
154 * R1 = host R1
155 * R2 = host R2
156 * R12 = exit handler id
157 * R13 = PACA
158 */
159
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]160 /* Restore non-volatile host registers (r14 - r31) and CR */
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]161 REST_NVGPRS(r1)
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]162 ld r4, _CCR(r1)
163 mtcr r4
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]164
165 addi r1, r1, SWITCH_FRAME_SIZE
166 ld r0, PPC_LR_STKOFF(r1)
167 mtlr r0
168 blr