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Chris Wilson05235c52016-07-20 09:21:08 +01001/*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
Chris Wilsonfa545cb2016-08-04 07:52:35 +010025#include <linux/prefetch.h>
Chris Wilsonb52992c2016-10-28 13:58:24 +010026#include <linux/dma-fence-array.h>
Chris Wilsonfa545cb2016-08-04 07:52:35 +010027
Chris Wilson05235c52016-07-20 09:21:08 +010028#include "i915_drv.h"
29
Chris Wilsonf54d1862016-10-25 13:00:45 +010030static const char *i915_fence_get_driver_name(struct dma_fence *fence)
Chris Wilson04769652016-07-20 09:21:11 +010031{
32 return "i915";
33}
34
Chris Wilsonf54d1862016-10-25 13:00:45 +010035static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
Chris Wilson04769652016-07-20 09:21:11 +010036{
Chris Wilson73cb9702016-10-28 13:58:46 +010037 return to_request(fence)->timeline->common->name;
Chris Wilson04769652016-07-20 09:21:11 +010038}
39
Chris Wilsonf54d1862016-10-25 13:00:45 +010040static bool i915_fence_signaled(struct dma_fence *fence)
Chris Wilson04769652016-07-20 09:21:11 +010041{
42 return i915_gem_request_completed(to_request(fence));
43}
44
Chris Wilsonf54d1862016-10-25 13:00:45 +010045static bool i915_fence_enable_signaling(struct dma_fence *fence)
Chris Wilson04769652016-07-20 09:21:11 +010046{
47 if (i915_fence_signaled(fence))
48 return false;
49
50 intel_engine_enable_signaling(to_request(fence));
51 return true;
52}
53
Chris Wilsonf54d1862016-10-25 13:00:45 +010054static signed long i915_fence_wait(struct dma_fence *fence,
Chris Wilson04769652016-07-20 09:21:11 +010055 bool interruptible,
Chris Wilsone95433c2016-10-28 13:58:27 +010056 signed long timeout)
Chris Wilson04769652016-07-20 09:21:11 +010057{
Chris Wilsone95433c2016-10-28 13:58:27 +010058 return i915_wait_request(to_request(fence), interruptible, timeout);
Chris Wilson04769652016-07-20 09:21:11 +010059}
60
Chris Wilsonf54d1862016-10-25 13:00:45 +010061static void i915_fence_release(struct dma_fence *fence)
Chris Wilson04769652016-07-20 09:21:11 +010062{
63 struct drm_i915_gem_request *req = to_request(fence);
64
Chris Wilsonfc158402016-11-25 13:17:18 +000065 /* The request is put onto a RCU freelist (i.e. the address
66 * is immediately reused), mark the fences as being freed now.
67 * Otherwise the debugobjects for the fences are only marked as
68 * freed when the slab cache itself is freed, and so we would get
69 * caught trying to reuse dead objects.
70 */
71 i915_sw_fence_fini(&req->submit);
Chris Wilsonfc158402016-11-25 13:17:18 +000072
Chris Wilson04769652016-07-20 09:21:11 +010073 kmem_cache_free(req->i915->requests, req);
74}
75
Chris Wilsonf54d1862016-10-25 13:00:45 +010076const struct dma_fence_ops i915_fence_ops = {
Chris Wilson04769652016-07-20 09:21:11 +010077 .get_driver_name = i915_fence_get_driver_name,
78 .get_timeline_name = i915_fence_get_timeline_name,
79 .enable_signaling = i915_fence_enable_signaling,
80 .signaled = i915_fence_signaled,
81 .wait = i915_fence_wait,
82 .release = i915_fence_release,
Chris Wilson04769652016-07-20 09:21:11 +010083};
84
Chris Wilson05235c52016-07-20 09:21:08 +010085int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
86 struct drm_file *file)
87{
88 struct drm_i915_private *dev_private;
89 struct drm_i915_file_private *file_priv;
90
91 WARN_ON(!req || !file || req->file_priv);
92
93 if (!req || !file)
94 return -EINVAL;
95
96 if (req->file_priv)
97 return -EINVAL;
98
99 dev_private = req->i915;
100 file_priv = file->driver_priv;
101
102 spin_lock(&file_priv->mm.lock);
103 req->file_priv = file_priv;
104 list_add_tail(&req->client_list, &file_priv->mm.request_list);
105 spin_unlock(&file_priv->mm.lock);
106
Chris Wilson05235c52016-07-20 09:21:08 +0100107 return 0;
108}
109
110static inline void
111i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
112{
113 struct drm_i915_file_private *file_priv = request->file_priv;
114
115 if (!file_priv)
116 return;
117
118 spin_lock(&file_priv->mm.lock);
119 list_del(&request->client_list);
120 request->file_priv = NULL;
121 spin_unlock(&file_priv->mm.lock);
Chris Wilson05235c52016-07-20 09:21:08 +0100122}
123
Chris Wilson52e54202016-11-14 20:41:02 +0000124static struct i915_dependency *
125i915_dependency_alloc(struct drm_i915_private *i915)
126{
127 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
128}
129
130static void
131i915_dependency_free(struct drm_i915_private *i915,
132 struct i915_dependency *dep)
133{
134 kmem_cache_free(i915->dependencies, dep);
135}
136
137static void
138__i915_priotree_add_dependency(struct i915_priotree *pt,
139 struct i915_priotree *signal,
140 struct i915_dependency *dep,
141 unsigned long flags)
142{
Chris Wilson20311bd2016-11-14 20:41:03 +0000143 INIT_LIST_HEAD(&dep->dfs_link);
Chris Wilson52e54202016-11-14 20:41:02 +0000144 list_add(&dep->wait_link, &signal->waiters_list);
145 list_add(&dep->signal_link, &pt->signalers_list);
146 dep->signaler = signal;
147 dep->flags = flags;
148}
149
150static int
151i915_priotree_add_dependency(struct drm_i915_private *i915,
152 struct i915_priotree *pt,
153 struct i915_priotree *signal)
154{
155 struct i915_dependency *dep;
156
157 dep = i915_dependency_alloc(i915);
158 if (!dep)
159 return -ENOMEM;
160
161 __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
162 return 0;
163}
164
165static void
166i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
167{
168 struct i915_dependency *dep, *next;
169
Chris Wilson20311bd2016-11-14 20:41:03 +0000170 GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node));
171
Chris Wilson52e54202016-11-14 20:41:02 +0000172 /* Everyone we depended upon (the fences we wait to be signaled)
173 * should retire before us and remove themselves from our list.
174 * However, retirement is run independently on each timeline and
175 * so we may be called out-of-order.
176 */
177 list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
178 list_del(&dep->wait_link);
179 if (dep->flags & I915_DEPENDENCY_ALLOC)
180 i915_dependency_free(i915, dep);
181 }
182
183 /* Remove ourselves from everyone who depends upon us */
184 list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
185 list_del(&dep->signal_link);
186 if (dep->flags & I915_DEPENDENCY_ALLOC)
187 i915_dependency_free(i915, dep);
188 }
189}
190
191static void
192i915_priotree_init(struct i915_priotree *pt)
193{
194 INIT_LIST_HEAD(&pt->signalers_list);
195 INIT_LIST_HEAD(&pt->waiters_list);
Chris Wilson20311bd2016-11-14 20:41:03 +0000196 RB_CLEAR_NODE(&pt->node);
197 pt->priority = INT_MIN;
Chris Wilson52e54202016-11-14 20:41:02 +0000198}
199
Chris Wilson12d31732017-02-23 07:44:09 +0000200static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
201{
202 struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
203 struct intel_engine_cs *engine;
204 enum intel_engine_id id;
205 int ret;
206
207 /* Carefully retire all requests without writing to the rings */
208 ret = i915_gem_wait_for_idle(i915,
209 I915_WAIT_INTERRUPTIBLE |
210 I915_WAIT_LOCKED);
211 if (ret)
212 return ret;
213
214 i915_gem_retire_requests(i915);
215 GEM_BUG_ON(i915->gt.active_requests > 1);
216
217 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
218 for_each_engine(engine, i915, id) {
219 struct intel_timeline *tl = &timeline->engine[id];
220
221 if (!i915_seqno_passed(seqno, tl->seqno)) {
222 /* spin until threads are complete */
223 while (intel_breadcrumbs_busy(engine))
224 cond_resched();
225 }
226
227 /* Finally reset hw state */
228 tl->seqno = seqno;
229 intel_engine_init_global_seqno(engine, seqno);
230 }
231
232 list_for_each_entry(timeline, &i915->gt.timelines, link) {
233 for_each_engine(engine, i915, id) {
234 struct intel_timeline *tl = &timeline->engine[id];
235
236 memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
237 }
238 }
239
240 return 0;
241}
242
243int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
244{
245 struct drm_i915_private *dev_priv = to_i915(dev);
246
247 lockdep_assert_held(&dev_priv->drm.struct_mutex);
248
249 if (seqno == 0)
250 return -EINVAL;
251
252 /* HWS page needs to be set less than what we
253 * will inject to ring
254 */
255 return reset_all_global_seqno(dev_priv, seqno - 1);
256}
257
258static int reserve_seqno(struct intel_engine_cs *engine)
259{
260 u32 active = ++engine->timeline->inflight_seqnos;
261 u32 seqno = engine->timeline->seqno;
262 int ret;
263
264 /* Reservation is fine until we need to wrap around */
265 if (likely(!add_overflows(seqno, active)))
266 return 0;
267
268 ret = reset_all_global_seqno(engine->i915, 0);
269 if (ret) {
270 engine->timeline->inflight_seqnos--;
271 return ret;
272 }
273
274 return 0;
275}
276
Chris Wilson9b6586a2017-02-23 07:44:08 +0000277static void unreserve_seqno(struct intel_engine_cs *engine)
278{
279 GEM_BUG_ON(!engine->timeline->inflight_seqnos);
280 engine->timeline->inflight_seqnos--;
281}
282
Chris Wilsonfa545cb2016-08-04 07:52:35 +0100283void i915_gem_retire_noop(struct i915_gem_active *active,
284 struct drm_i915_gem_request *request)
285{
286 /* Space left intentionally blank */
287}
288
Chris Wilson05235c52016-07-20 09:21:08 +0100289static void i915_gem_request_retire(struct drm_i915_gem_request *request)
290{
Chris Wilsone8a9c582016-12-18 15:37:20 +0000291 struct intel_engine_cs *engine = request->engine;
Chris Wilsonfa545cb2016-08-04 07:52:35 +0100292 struct i915_gem_active *active, *next;
293
Chris Wilson4c7d62c2016-10-28 13:58:32 +0100294 lockdep_assert_held(&request->i915->drm.struct_mutex);
Chris Wilson48bc2a42016-11-25 13:17:17 +0000295 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
Chris Wilson4c7d62c2016-10-28 13:58:32 +0100296 GEM_BUG_ON(!i915_gem_request_completed(request));
Chris Wilson43020552016-11-15 16:46:20 +0000297 GEM_BUG_ON(!request->i915->gt.active_requests);
Chris Wilson4c7d62c2016-10-28 13:58:32 +0100298
Chris Wilson05235c52016-07-20 09:21:08 +0100299 trace_i915_gem_request_retire(request);
Chris Wilson80b204b2016-10-28 13:58:58 +0100300
Chris Wilsone8a9c582016-12-18 15:37:20 +0000301 spin_lock_irq(&engine->timeline->lock);
Chris Wilsone95433c2016-10-28 13:58:27 +0100302 list_del_init(&request->link);
Chris Wilsone8a9c582016-12-18 15:37:20 +0000303 spin_unlock_irq(&engine->timeline->lock);
Chris Wilson05235c52016-07-20 09:21:08 +0100304
305 /* We know the GPU must have read the request to have
306 * sent us the seqno + interrupt, so use the position
307 * of tail of the request to update the last known position
308 * of the GPU head.
309 *
310 * Note this requires that we are always called in request
311 * completion order.
312 */
Chris Wilson675d9ad2016-08-04 07:52:36 +0100313 list_del(&request->ring_link);
Chris Wilson1dae2df2016-08-02 22:50:19 +0100314 request->ring->last_retired_head = request->postfix;
Chris Wilson43020552016-11-15 16:46:20 +0000315 if (!--request->i915->gt.active_requests) {
316 GEM_BUG_ON(!request->i915->gt.awake);
317 mod_delayed_work(request->i915->wq,
318 &request->i915->gt.idle_work,
319 msecs_to_jiffies(100));
320 }
Chris Wilson9b6586a2017-02-23 07:44:08 +0000321 unreserve_seqno(request->engine);
Chris Wilson05235c52016-07-20 09:21:08 +0100322
Chris Wilsonfa545cb2016-08-04 07:52:35 +0100323 /* Walk through the active list, calling retire on each. This allows
324 * objects to track their GPU activity and mark themselves as idle
325 * when their *last* active request is completed (updating state
326 * tracking lists for eviction, active references for GEM, etc).
327 *
328 * As the ->retire() may free the node, we decouple it first and
329 * pass along the auxiliary information (to avoid dereferencing
330 * the node after the callback).
331 */
332 list_for_each_entry_safe(active, next, &request->active_list, link) {
333 /* In microbenchmarks or focusing upon time inside the kernel,
334 * we may spend an inordinate amount of time simply handling
335 * the retirement of requests and processing their callbacks.
336 * Of which, this loop itself is particularly hot due to the
337 * cache misses when jumping around the list of i915_gem_active.
338 * So we try to keep this loop as streamlined as possible and
339 * also prefetch the next i915_gem_active to try and hide
340 * the likely cache miss.
341 */
342 prefetchw(next);
343
344 INIT_LIST_HEAD(&active->link);
Chris Wilson0eafec62016-08-04 16:32:41 +0100345 RCU_INIT_POINTER(active->request, NULL);
Chris Wilsonfa545cb2016-08-04 07:52:35 +0100346
347 active->retire(active, request);
348 }
349
Chris Wilson05235c52016-07-20 09:21:08 +0100350 i915_gem_request_remove_from_client(request);
351
Mika Kuoppalae5e1fc42016-11-16 17:20:31 +0200352 /* Retirement decays the ban score as it is a sign of ctx progress */
Mika Kuoppalabc1d53c2016-11-16 17:20:34 +0200353 if (request->ctx->ban_score > 0)
354 request->ctx->ban_score--;
Mika Kuoppalae5e1fc42016-11-16 17:20:31 +0200355
Chris Wilsone8a9c582016-12-18 15:37:20 +0000356 /* The backing object for the context is done after switching to the
357 * *next* context. Therefore we cannot retire the previous context until
358 * the next context has already started running. However, since we
359 * cannot take the required locks at i915_gem_request_submit() we
360 * defer the unpinning of the active context to now, retirement of
361 * the subsequent request.
362 */
363 if (engine->last_retired_context)
364 engine->context_unpin(engine, engine->last_retired_context);
365 engine->last_retired_context = request->ctx;
Chris Wilsond07f0e52016-10-28 13:58:44 +0100366
367 dma_fence_signal(&request->fence);
Chris Wilson52e54202016-11-14 20:41:02 +0000368
369 i915_priotree_fini(request->i915, &request->priotree);
Chris Wilsone8a261e2016-07-20 13:31:49 +0100370 i915_gem_request_put(request);
Chris Wilson05235c52016-07-20 09:21:08 +0100371}
372
373void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
374{
375 struct intel_engine_cs *engine = req->engine;
376 struct drm_i915_gem_request *tmp;
377
378 lockdep_assert_held(&req->i915->drm.struct_mutex);
Chris Wilson4ffd6e02016-11-25 13:17:15 +0000379 GEM_BUG_ON(!i915_gem_request_completed(req));
380
Chris Wilsone95433c2016-10-28 13:58:27 +0100381 if (list_empty(&req->link))
382 return;
Chris Wilson05235c52016-07-20 09:21:08 +0100383
384 do {
Chris Wilson73cb9702016-10-28 13:58:46 +0100385 tmp = list_first_entry(&engine->timeline->requests,
Chris Wilsonefdf7c02016-08-04 07:52:33 +0100386 typeof(*tmp), link);
Chris Wilson05235c52016-07-20 09:21:08 +0100387
388 i915_gem_request_retire(tmp);
389 } while (tmp != req);
Chris Wilson05235c52016-07-20 09:21:08 +0100390}
391
Chris Wilson9b6586a2017-02-23 07:44:08 +0000392static u32 timeline_get_seqno(struct intel_timeline *tl)
Chris Wilson80b204b2016-10-28 13:58:58 +0100393{
Chris Wilson9b6586a2017-02-23 07:44:08 +0000394 return ++tl->seqno;
Chris Wilson05235c52016-07-20 09:21:08 +0100395}
396
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000397void __i915_gem_request_submit(struct drm_i915_gem_request *request)
Chris Wilson5590af32016-09-09 14:11:54 +0100398{
Chris Wilson73cb9702016-10-28 13:58:46 +0100399 struct intel_engine_cs *engine = request->engine;
Chris Wilsonf2d13292016-10-28 13:58:57 +0100400 struct intel_timeline *timeline;
401 u32 seqno;
Chris Wilson5590af32016-09-09 14:11:54 +0100402
Chris Wilsone60a8702017-03-02 11:51:30 +0000403 GEM_BUG_ON(!irqs_disabled());
Chris Wilson67520412017-03-02 13:28:01 +0000404 lockdep_assert_held(&engine->timeline->lock);
Chris Wilsone60a8702017-03-02 11:51:30 +0000405
Chris Wilsonfe497892017-02-23 07:44:13 +0000406 trace_i915_gem_request_execute(request);
407
Chris Wilson80b204b2016-10-28 13:58:58 +0100408 /* Transfer from per-context onto the global per-engine timeline */
409 timeline = engine->timeline;
410 GEM_BUG_ON(timeline == request->timeline);
Chris Wilson5590af32016-09-09 14:11:54 +0100411
Chris Wilson9b6586a2017-02-23 07:44:08 +0000412 seqno = timeline_get_seqno(timeline);
Chris Wilsonf2d13292016-10-28 13:58:57 +0100413 GEM_BUG_ON(!seqno);
414 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
415
Chris Wilsonf2d13292016-10-28 13:58:57 +0100416 /* We may be recursing from the signal callback of another i915 fence */
417 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
418 request->global_seqno = seqno;
419 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
420 intel_engine_enable_signaling(request);
421 spin_unlock(&request->lock);
422
Chris Wilsoncaddfe72016-10-28 13:58:52 +0100423 engine->emit_breadcrumb(request,
424 request->ring->vaddr + request->postfix);
Chris Wilson5590af32016-09-09 14:11:54 +0100425
Chris Wilsonbb894852016-11-14 20:40:57 +0000426 spin_lock(&request->timeline->lock);
Chris Wilson80b204b2016-10-28 13:58:58 +0100427 list_move_tail(&request->link, &timeline->requests);
428 spin_unlock(&request->timeline->lock);
429
Chris Wilsonfe497892017-02-23 07:44:13 +0000430 wake_up_all(&request->execute);
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000431}
Chris Wilson23902e42016-11-14 20:40:58 +0000432
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000433void i915_gem_request_submit(struct drm_i915_gem_request *request)
434{
435 struct intel_engine_cs *engine = request->engine;
436 unsigned long flags;
437
438 /* Will be called from irq-context when using foreign fences. */
439 spin_lock_irqsave(&engine->timeline->lock, flags);
440
441 __i915_gem_request_submit(request);
442
443 spin_unlock_irqrestore(&engine->timeline->lock, flags);
444}
445
Chris Wilsond6a22892017-02-23 07:44:17 +0000446void __i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
447{
448 struct intel_engine_cs *engine = request->engine;
449 struct intel_timeline *timeline;
450
Chris Wilsone60a8702017-03-02 11:51:30 +0000451 GEM_BUG_ON(!irqs_disabled());
Chris Wilson67520412017-03-02 13:28:01 +0000452 lockdep_assert_held(&engine->timeline->lock);
Chris Wilsond6a22892017-02-23 07:44:17 +0000453
454 /* Only unwind in reverse order, required so that the per-context list
455 * is kept in seqno/ring order.
456 */
457 GEM_BUG_ON(request->global_seqno != engine->timeline->seqno);
458 engine->timeline->seqno--;
459
460 /* We may be recursing from the signal callback of another i915 fence */
461 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
462 request->global_seqno = 0;
463 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
464 intel_engine_cancel_signaling(request);
465 spin_unlock(&request->lock);
466
467 /* Transfer back from the global per-engine timeline to per-context */
468 timeline = request->timeline;
469 GEM_BUG_ON(timeline == engine->timeline);
470
471 spin_lock(&timeline->lock);
472 list_move(&request->link, &timeline->requests);
473 spin_unlock(&timeline->lock);
474
475 /* We don't need to wake_up any waiters on request->execute, they
476 * will get woken by any other event or us re-adding this request
477 * to the engine timeline (__i915_gem_request_submit()). The waiters
478 * should be quite adapt at finding that the request now has a new
479 * global_seqno to the one they went to sleep on.
480 */
481}
482
483void i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
484{
485 struct intel_engine_cs *engine = request->engine;
486 unsigned long flags;
487
488 /* Will be called from irq-context when using foreign fences. */
489 spin_lock_irqsave(&engine->timeline->lock, flags);
490
491 __i915_gem_request_unsubmit(request);
492
493 spin_unlock_irqrestore(&engine->timeline->lock, flags);
494}
495
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000496static int __i915_sw_fence_call
497submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
498{
Chris Wilson48bc2a42016-11-25 13:17:17 +0000499 struct drm_i915_gem_request *request =
500 container_of(fence, typeof(*request), submit);
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000501
Chris Wilson48bc2a42016-11-25 13:17:17 +0000502 switch (state) {
503 case FENCE_COMPLETE:
Tvrtko Ursulin354d0362017-02-21 11:01:42 +0000504 trace_i915_gem_request_submit(request);
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000505 request->engine->submit_request(request);
Chris Wilson48bc2a42016-11-25 13:17:17 +0000506 break;
507
508 case FENCE_FREE:
509 i915_gem_request_put(request);
510 break;
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000511 }
Chris Wilson80b204b2016-10-28 13:58:58 +0100512
Chris Wilson5590af32016-09-09 14:11:54 +0100513 return NOTIFY_DONE;
514}
515
Chris Wilson8e637172016-08-02 22:50:26 +0100516/**
517 * i915_gem_request_alloc - allocate a request structure
518 *
519 * @engine: engine that we wish to issue the request on.
520 * @ctx: context that the request will be associated with.
521 * This can be NULL if the request is not directly related to
522 * any specific user context, in which case this function will
523 * choose an appropriate context to use.
524 *
525 * Returns a pointer to the allocated request if successful,
526 * or an error code if not.
527 */
528struct drm_i915_gem_request *
529i915_gem_request_alloc(struct intel_engine_cs *engine,
530 struct i915_gem_context *ctx)
Chris Wilson05235c52016-07-20 09:21:08 +0100531{
532 struct drm_i915_private *dev_priv = engine->i915;
Chris Wilson05235c52016-07-20 09:21:08 +0100533 struct drm_i915_gem_request *req;
534 int ret;
535
Chris Wilson28176ef2016-10-28 13:58:56 +0100536 lockdep_assert_held(&dev_priv->drm.struct_mutex);
537
Chris Wilson05235c52016-07-20 09:21:08 +0100538 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
Chris Wilson6ffb7d02017-01-14 16:23:33 +0000539 * EIO if the GPU is already wedged.
Chris Wilson05235c52016-07-20 09:21:08 +0100540 */
Chris Wilson6ffb7d02017-01-14 16:23:33 +0000541 if (i915_terminally_wedged(&dev_priv->gpu_error))
542 return ERR_PTR(-EIO);
Chris Wilson05235c52016-07-20 09:21:08 +0100543
Chris Wilsone8a9c582016-12-18 15:37:20 +0000544 /* Pinning the contexts may generate requests in order to acquire
545 * GGTT space, so do this first before we reserve a seqno for
546 * ourselves.
547 */
548 ret = engine->context_pin(engine, ctx);
Chris Wilson28176ef2016-10-28 13:58:56 +0100549 if (ret)
550 return ERR_PTR(ret);
551
Chris Wilson9b6586a2017-02-23 07:44:08 +0000552 ret = reserve_seqno(engine);
Chris Wilsone8a9c582016-12-18 15:37:20 +0000553 if (ret)
554 goto err_unpin;
555
Chris Wilson9b5f4e52016-07-20 09:21:09 +0100556 /* Move the oldest request to the slab-cache (if not in use!) */
Chris Wilson73cb9702016-10-28 13:58:46 +0100557 req = list_first_entry_or_null(&engine->timeline->requests,
Chris Wilsonefdf7c02016-08-04 07:52:33 +0100558 typeof(*req), link);
Chris Wilson754c9fd2017-02-23 07:44:14 +0000559 if (req && i915_gem_request_completed(req))
Chris Wilson2a1d7752016-07-26 12:01:51 +0100560 i915_gem_request_retire(req);
Chris Wilson9b5f4e52016-07-20 09:21:09 +0100561
Chris Wilson5a198b82016-08-09 09:23:34 +0100562 /* Beware: Dragons be flying overhead.
563 *
564 * We use RCU to look up requests in flight. The lookups may
565 * race with the request being allocated from the slab freelist.
566 * That is the request we are writing to here, may be in the process
Chris Wilson1426f712016-08-09 17:03:22 +0100567 * of being read by __i915_gem_active_get_rcu(). As such,
Chris Wilson5a198b82016-08-09 09:23:34 +0100568 * we have to be very careful when overwriting the contents. During
569 * the RCU lookup, we change chase the request->engine pointer,
Chris Wilson65e47602016-10-28 13:58:49 +0100570 * read the request->global_seqno and increment the reference count.
Chris Wilson5a198b82016-08-09 09:23:34 +0100571 *
572 * The reference count is incremented atomically. If it is zero,
573 * the lookup knows the request is unallocated and complete. Otherwise,
574 * it is either still in use, or has been reallocated and reset
Chris Wilsonf54d1862016-10-25 13:00:45 +0100575 * with dma_fence_init(). This increment is safe for release as we
576 * check that the request we have a reference to and matches the active
Chris Wilson5a198b82016-08-09 09:23:34 +0100577 * request.
578 *
579 * Before we increment the refcount, we chase the request->engine
580 * pointer. We must not call kmem_cache_zalloc() or else we set
581 * that pointer to NULL and cause a crash during the lookup. If
582 * we see the request is completed (based on the value of the
583 * old engine and seqno), the lookup is complete and reports NULL.
584 * If we decide the request is not completed (new engine or seqno),
585 * then we grab a reference and double check that it is still the
586 * active request - which it won't be and restart the lookup.
587 *
588 * Do not use kmem_cache_zalloc() here!
589 */
590 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
Chris Wilson28176ef2016-10-28 13:58:56 +0100591 if (!req) {
592 ret = -ENOMEM;
593 goto err_unreserve;
594 }
Chris Wilson05235c52016-07-20 09:21:08 +0100595
Chris Wilson80b204b2016-10-28 13:58:58 +0100596 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
597 GEM_BUG_ON(req->timeline == engine->timeline);
Chris Wilson73cb9702016-10-28 13:58:46 +0100598
Chris Wilson04769652016-07-20 09:21:11 +0100599 spin_lock_init(&req->lock);
Chris Wilsonf54d1862016-10-25 13:00:45 +0100600 dma_fence_init(&req->fence,
601 &i915_fence_ops,
602 &req->lock,
Chris Wilson73cb9702016-10-28 13:58:46 +0100603 req->timeline->fence_context,
Chris Wilson9b6586a2017-02-23 07:44:08 +0000604 timeline_get_seqno(req->timeline));
Chris Wilson04769652016-07-20 09:21:11 +0100605
Chris Wilson48bc2a42016-11-25 13:17:17 +0000606 /* We bump the ref for the fence chain */
607 i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
Chris Wilsonfe497892017-02-23 07:44:13 +0000608 init_waitqueue_head(&req->execute);
Chris Wilson5590af32016-09-09 14:11:54 +0100609
Chris Wilson52e54202016-11-14 20:41:02 +0000610 i915_priotree_init(&req->priotree);
611
Chris Wilsonfa545cb2016-08-04 07:52:35 +0100612 INIT_LIST_HEAD(&req->active_list);
Chris Wilson05235c52016-07-20 09:21:08 +0100613 req->i915 = dev_priv;
614 req->engine = engine;
Chris Wilsone8a9c582016-12-18 15:37:20 +0000615 req->ctx = ctx;
Chris Wilson05235c52016-07-20 09:21:08 +0100616
Chris Wilson5a198b82016-08-09 09:23:34 +0100617 /* No zalloc, must clear what we need by hand */
Chris Wilsonf2d13292016-10-28 13:58:57 +0100618 req->global_seqno = 0;
Chris Wilson5a198b82016-08-09 09:23:34 +0100619 req->file_priv = NULL;
Chris Wilson058d88c2016-08-15 10:49:06 +0100620 req->batch = NULL;
Chris Wilson5a198b82016-08-09 09:23:34 +0100621
Chris Wilson05235c52016-07-20 09:21:08 +0100622 /*
623 * Reserve space in the ring buffer for all the commands required to
624 * eventually emit this request. This is to guarantee that the
625 * i915_add_request() call can't fail. Note that the reserve may need
626 * to be redone if the request is not actually submitted straight
627 * away, e.g. because a GPU scheduler has deferred it.
628 */
629 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
Chris Wilson98f29e82016-10-28 13:58:51 +0100630 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
Chris Wilson05235c52016-07-20 09:21:08 +0100631
Chris Wilsonf73e7392016-12-18 15:37:24 +0000632 ret = engine->request_alloc(req);
Chris Wilson05235c52016-07-20 09:21:08 +0100633 if (ret)
634 goto err_ctx;
635
Chris Wilsond0454462016-08-15 10:48:40 +0100636 /* Record the position of the start of the request so that
637 * should we detect the updated seqno part-way through the
638 * GPU processing the request, we never over-estimate the
639 * position of the head.
640 */
641 req->head = req->ring->tail;
642
Chris Wilson9b6586a2017-02-23 07:44:08 +0000643 /* Check that we didn't interrupt ourselves with a new request */
644 GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
Chris Wilson8e637172016-08-02 22:50:26 +0100645 return req;
Chris Wilson05235c52016-07-20 09:21:08 +0100646
647err_ctx:
Chris Wilson1618bdb2016-11-25 13:17:16 +0000648 /* Make sure we didn't add ourselves to external state before freeing */
649 GEM_BUG_ON(!list_empty(&req->active_list));
650 GEM_BUG_ON(!list_empty(&req->priotree.signalers_list));
651 GEM_BUG_ON(!list_empty(&req->priotree.waiters_list));
652
Chris Wilson05235c52016-07-20 09:21:08 +0100653 kmem_cache_free(dev_priv->requests, req);
Chris Wilson28176ef2016-10-28 13:58:56 +0100654err_unreserve:
Chris Wilson9b6586a2017-02-23 07:44:08 +0000655 unreserve_seqno(engine);
Chris Wilsone8a9c582016-12-18 15:37:20 +0000656err_unpin:
657 engine->context_unpin(engine, ctx);
Chris Wilson8e637172016-08-02 22:50:26 +0100658 return ERR_PTR(ret);
Chris Wilson05235c52016-07-20 09:21:08 +0100659}
660
Chris Wilsona2bc4692016-09-09 14:11:56 +0100661static int
662i915_gem_request_await_request(struct drm_i915_gem_request *to,
663 struct drm_i915_gem_request *from)
664{
Chris Wilson754c9fd2017-02-23 07:44:14 +0000665 u32 seqno;
Chris Wilson85e17f52016-10-28 13:58:53 +0100666 int ret;
Chris Wilsona2bc4692016-09-09 14:11:56 +0100667
668 GEM_BUG_ON(to == from);
669
Chris Wilson52e54202016-11-14 20:41:02 +0000670 if (to->engine->schedule) {
671 ret = i915_priotree_add_dependency(to->i915,
672 &to->priotree,
673 &from->priotree);
674 if (ret < 0)
675 return ret;
676 }
677
Chris Wilson73cb9702016-10-28 13:58:46 +0100678 if (to->timeline == from->timeline)
Chris Wilsona2bc4692016-09-09 14:11:56 +0100679 return 0;
680
Chris Wilson73cb9702016-10-28 13:58:46 +0100681 if (to->engine == from->engine) {
682 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
683 &from->submit,
684 GFP_KERNEL);
685 return ret < 0 ? ret : 0;
686 }
687
Chris Wilson754c9fd2017-02-23 07:44:14 +0000688 seqno = i915_gem_request_global_seqno(from);
689 if (!seqno) {
Chris Wilson65e47602016-10-28 13:58:49 +0100690 ret = i915_sw_fence_await_dma_fence(&to->submit,
691 &from->fence, 0,
692 GFP_KERNEL);
693 return ret < 0 ? ret : 0;
694 }
695
Chris Wilson754c9fd2017-02-23 07:44:14 +0000696 if (seqno <= to->timeline->sync_seqno[from->engine->id])
Chris Wilsona2bc4692016-09-09 14:11:56 +0100697 return 0;
698
699 trace_i915_gem_ring_sync_to(to, from);
700 if (!i915.semaphores) {
Chris Wilson0a046a02016-09-09 14:12:00 +0100701 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
702 ret = i915_sw_fence_await_dma_fence(&to->submit,
703 &from->fence, 0,
704 GFP_KERNEL);
705 if (ret < 0)
706 return ret;
707 }
Chris Wilsona2bc4692016-09-09 14:11:56 +0100708 } else {
709 ret = to->engine->semaphore.sync_to(to, from);
710 if (ret)
711 return ret;
712 }
713
Chris Wilson754c9fd2017-02-23 07:44:14 +0000714 to->timeline->sync_seqno[from->engine->id] = seqno;
Chris Wilsona2bc4692016-09-09 14:11:56 +0100715 return 0;
716}
717
Chris Wilsonb52992c2016-10-28 13:58:24 +0100718int
719i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
720 struct dma_fence *fence)
721{
722 struct dma_fence_array *array;
723 int ret;
724 int i;
725
726 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
727 return 0;
728
729 if (dma_fence_is_i915(fence))
730 return i915_gem_request_await_request(req, to_request(fence));
731
732 if (!dma_fence_is_array(fence)) {
733 ret = i915_sw_fence_await_dma_fence(&req->submit,
734 fence, I915_FENCE_TIMEOUT,
735 GFP_KERNEL);
736 return ret < 0 ? ret : 0;
737 }
738
739 /* Note that if the fence-array was created in signal-on-any mode,
740 * we should *not* decompose it into its individual fences. However,
741 * we don't currently store which mode the fence-array is operating
742 * in. Fortunately, the only user of signal-on-any is private to
743 * amdgpu and we should not see any incoming fence-array from
744 * sync-file being in signal-on-any mode.
745 */
746
747 array = to_dma_fence_array(fence);
748 for (i = 0; i < array->num_fences; i++) {
749 struct dma_fence *child = array->fences[i];
750
751 if (dma_fence_is_i915(child))
752 ret = i915_gem_request_await_request(req,
753 to_request(child));
754 else
755 ret = i915_sw_fence_await_dma_fence(&req->submit,
756 child, I915_FENCE_TIMEOUT,
757 GFP_KERNEL);
758 if (ret < 0)
759 return ret;
760 }
761
762 return 0;
763}
764
Chris Wilsona2bc4692016-09-09 14:11:56 +0100765/**
766 * i915_gem_request_await_object - set this request to (async) wait upon a bo
767 *
768 * @to: request we are wishing to use
769 * @obj: object which may be in use on another ring.
770 *
771 * This code is meant to abstract object synchronization with the GPU.
772 * Conceptually we serialise writes between engines inside the GPU.
773 * We only allow one engine to write into a buffer at any time, but
774 * multiple readers. To ensure each has a coherent view of memory, we must:
775 *
776 * - If there is an outstanding write request to the object, the new
777 * request must wait for it to complete (either CPU or in hw, requests
778 * on the same ring will be naturally ordered).
779 *
780 * - If we are a write request (pending_write_domain is set), the new
781 * request must wait for outstanding read requests to complete.
782 *
783 * Returns 0 if successful, else propagates up the lower layer error.
784 */
785int
786i915_gem_request_await_object(struct drm_i915_gem_request *to,
787 struct drm_i915_gem_object *obj,
788 bool write)
789{
Chris Wilsond07f0e52016-10-28 13:58:44 +0100790 struct dma_fence *excl;
791 int ret = 0;
Chris Wilsona2bc4692016-09-09 14:11:56 +0100792
793 if (write) {
Chris Wilsond07f0e52016-10-28 13:58:44 +0100794 struct dma_fence **shared;
795 unsigned int count, i;
Chris Wilsona2bc4692016-09-09 14:11:56 +0100796
Chris Wilsond07f0e52016-10-28 13:58:44 +0100797 ret = reservation_object_get_fences_rcu(obj->resv,
798 &excl, &count, &shared);
Chris Wilsona2bc4692016-09-09 14:11:56 +0100799 if (ret)
800 return ret;
Chris Wilsond07f0e52016-10-28 13:58:44 +0100801
802 for (i = 0; i < count; i++) {
803 ret = i915_gem_request_await_dma_fence(to, shared[i]);
804 if (ret)
805 break;
806
807 dma_fence_put(shared[i]);
808 }
809
810 for (; i < count; i++)
811 dma_fence_put(shared[i]);
812 kfree(shared);
813 } else {
814 excl = reservation_object_get_excl_rcu(obj->resv);
Chris Wilsona2bc4692016-09-09 14:11:56 +0100815 }
816
Chris Wilsond07f0e52016-10-28 13:58:44 +0100817 if (excl) {
818 if (ret == 0)
819 ret = i915_gem_request_await_dma_fence(to, excl);
820
821 dma_fence_put(excl);
822 }
823
824 return ret;
Chris Wilsona2bc4692016-09-09 14:11:56 +0100825}
826
Chris Wilson05235c52016-07-20 09:21:08 +0100827static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
828{
829 struct drm_i915_private *dev_priv = engine->i915;
830
Chris Wilson05235c52016-07-20 09:21:08 +0100831 if (dev_priv->gt.awake)
832 return;
833
Chris Wilson43020552016-11-15 16:46:20 +0000834 GEM_BUG_ON(!dev_priv->gt.active_requests);
835
Chris Wilson05235c52016-07-20 09:21:08 +0100836 intel_runtime_pm_get_noresume(dev_priv);
837 dev_priv->gt.awake = true;
838
Chris Wilson54b4f682016-07-21 21:16:19 +0100839 intel_enable_gt_powersave(dev_priv);
Chris Wilson05235c52016-07-20 09:21:08 +0100840 i915_update_gfx_val(dev_priv);
841 if (INTEL_GEN(dev_priv) >= 6)
842 gen6_rps_busy(dev_priv);
843
844 queue_delayed_work(dev_priv->wq,
845 &dev_priv->gt.retire_work,
846 round_jiffies_up_relative(HZ));
847}
848
849/*
850 * NB: This function is not allowed to fail. Doing so would mean the the
851 * request is not being tracked for completion but the work itself is
852 * going to happen on the hardware. This would be a Bad Thing(tm).
853 */
Chris Wilson17f298cf2016-08-10 13:41:46 +0100854void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
Chris Wilson05235c52016-07-20 09:21:08 +0100855{
Chris Wilson95b2ab52016-08-15 10:48:46 +0100856 struct intel_engine_cs *engine = request->engine;
857 struct intel_ring *ring = request->ring;
Chris Wilson73cb9702016-10-28 13:58:46 +0100858 struct intel_timeline *timeline = request->timeline;
Chris Wilson0a046a02016-09-09 14:12:00 +0100859 struct drm_i915_gem_request *prev;
Tvrtko Ursulin73dec952017-02-14 11:32:42 +0000860 u32 *cs;
Chris Wilsoncaddfe72016-10-28 13:58:52 +0100861 int err;
Chris Wilson05235c52016-07-20 09:21:08 +0100862
Chris Wilson4c7d62c2016-10-28 13:58:32 +0100863 lockdep_assert_held(&request->i915->drm.struct_mutex);
Chris Wilson0f25dff2016-09-09 14:11:55 +0100864 trace_i915_gem_request_add(request);
865
Chris Wilsonc781c972017-01-11 14:08:58 +0000866 /* Make sure that no request gazumped us - if it was allocated after
867 * our i915_gem_request_alloc() and called __i915_add_request() before
868 * us, the timeline will hold its seqno which is later than ours.
869 */
Chris Wilson9b6586a2017-02-23 07:44:08 +0000870 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
Chris Wilsonc781c972017-01-11 14:08:58 +0000871
Chris Wilson05235c52016-07-20 09:21:08 +0100872 /*
873 * To ensure that this call will not fail, space for its emissions
874 * should already have been reserved in the ring buffer. Let the ring
875 * know that it is time to use that space up.
876 */
Chris Wilson05235c52016-07-20 09:21:08 +0100877 request->reserved_space = 0;
878
879 /*
880 * Emit any outstanding flushes - execbuf can fail to emit the flush
881 * after having emitted the batchbuffer command. Hence we need to fix
882 * things up similar to emitting the lazy request. The difference here
883 * is that the flush _must_ happen before the next request, no matter
884 * what.
885 */
886 if (flush_caches) {
Chris Wilsoncaddfe72016-10-28 13:58:52 +0100887 err = engine->emit_flush(request, EMIT_FLUSH);
Chris Wilsonc7fe7d22016-08-02 22:50:24 +0100888
Chris Wilson05235c52016-07-20 09:21:08 +0100889 /* Not allowed to fail! */
Chris Wilsoncaddfe72016-10-28 13:58:52 +0100890 WARN(err, "engine->emit_flush() failed: %d!\n", err);
Chris Wilson05235c52016-07-20 09:21:08 +0100891 }
892
Chris Wilsond0454462016-08-15 10:48:40 +0100893 /* Record the position of the start of the breadcrumb so that
Chris Wilson05235c52016-07-20 09:21:08 +0100894 * should we detect the updated seqno part-way through the
895 * GPU processing the request, we never over-estimate the
Chris Wilsond0454462016-08-15 10:48:40 +0100896 * position of the ring's HEAD.
Chris Wilson05235c52016-07-20 09:21:08 +0100897 */
Tvrtko Ursulin73dec952017-02-14 11:32:42 +0000898 cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
899 GEM_BUG_ON(IS_ERR(cs));
900 request->postfix = intel_ring_offset(request, cs);
Chris Wilson05235c52016-07-20 09:21:08 +0100901
Chris Wilson0f25dff2016-09-09 14:11:55 +0100902 /* Seal the request and mark it as pending execution. Note that
903 * we may inspect this state, without holding any locks, during
904 * hangcheck. Hence we apply the barrier to ensure that we do not
905 * see a more recent value in the hws than we are tracking.
906 */
Chris Wilson0a046a02016-09-09 14:12:00 +0100907
Chris Wilson73cb9702016-10-28 13:58:46 +0100908 prev = i915_gem_active_raw(&timeline->last_request,
Chris Wilson0a046a02016-09-09 14:12:00 +0100909 &request->i915->drm.struct_mutex);
Chris Wilson52e54202016-11-14 20:41:02 +0000910 if (prev) {
Chris Wilson0a046a02016-09-09 14:12:00 +0100911 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
912 &request->submitq);
Chris Wilson52e54202016-11-14 20:41:02 +0000913 if (engine->schedule)
914 __i915_priotree_add_dependency(&request->priotree,
915 &prev->priotree,
916 &request->dep,
917 0);
918 }
Chris Wilson0a046a02016-09-09 14:12:00 +0100919
Chris Wilson80b204b2016-10-28 13:58:58 +0100920 spin_lock_irq(&timeline->lock);
Chris Wilsonf2d13292016-10-28 13:58:57 +0100921 list_add_tail(&request->link, &timeline->requests);
Chris Wilson80b204b2016-10-28 13:58:58 +0100922 spin_unlock_irq(&timeline->lock);
Chris Wilson28176ef2016-10-28 13:58:56 +0100923
Chris Wilson9b6586a2017-02-23 07:44:08 +0000924 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
Chris Wilson73cb9702016-10-28 13:58:46 +0100925 i915_gem_active_set(&timeline->last_request, request);
Chris Wilsonf2d13292016-10-28 13:58:57 +0100926
Chris Wilson0f25dff2016-09-09 14:11:55 +0100927 list_add_tail(&request->ring_link, &ring->request_list);
Chris Wilsonf2d13292016-10-28 13:58:57 +0100928 request->emitted_jiffies = jiffies;
Chris Wilson0f25dff2016-09-09 14:11:55 +0100929
Chris Wilson9b6586a2017-02-23 07:44:08 +0000930 if (!request->i915->gt.active_requests++)
931 i915_gem_mark_busy(engine);
Chris Wilson5590af32016-09-09 14:11:54 +0100932
Chris Wilson0de91362016-11-14 20:41:01 +0000933 /* Let the backend know a new request has arrived that may need
934 * to adjust the existing execution schedule due to a high priority
935 * request - i.e. we may want to preempt the current request in order
936 * to run a high priority dependency chain *before* we can execute this
937 * request.
938 *
939 * This is called before the request is ready to run so that we can
940 * decide whether to preempt the entire chain so that it is ready to
941 * run at the earliest possible convenience.
942 */
943 if (engine->schedule)
Chris Wilson9f792eb2016-11-14 20:41:04 +0000944 engine->schedule(request, request->ctx->priority);
Chris Wilson0de91362016-11-14 20:41:01 +0000945
Chris Wilson5590af32016-09-09 14:11:54 +0100946 local_bh_disable();
947 i915_sw_fence_commit(&request->submit);
948 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
Chris Wilson05235c52016-07-20 09:21:08 +0100949}
950
951static unsigned long local_clock_us(unsigned int *cpu)
952{
953 unsigned long t;
954
955 /* Cheaply and approximately convert from nanoseconds to microseconds.
956 * The result and subsequent calculations are also defined in the same
957 * approximate microseconds units. The principal source of timing
958 * error here is from the simple truncation.
959 *
960 * Note that local_clock() is only defined wrt to the current CPU;
961 * the comparisons are no longer valid if we switch CPUs. Instead of
962 * blocking preemption for the entire busywait, we can detect the CPU
963 * switch and use that as indicator of system load and a reason to
964 * stop busywaiting, see busywait_stop().
965 */
966 *cpu = get_cpu();
967 t = local_clock() >> 10;
968 put_cpu();
969
970 return t;
971}
972
973static bool busywait_stop(unsigned long timeout, unsigned int cpu)
974{
975 unsigned int this_cpu;
976
977 if (time_after(local_clock_us(&this_cpu), timeout))
978 return true;
979
980 return this_cpu != cpu;
981}
982
983bool __i915_spin_request(const struct drm_i915_gem_request *req,
Chris Wilson754c9fd2017-02-23 07:44:14 +0000984 u32 seqno, int state, unsigned long timeout_us)
Chris Wilson05235c52016-07-20 09:21:08 +0100985{
Chris Wilsonc33ed062017-02-17 15:13:01 +0000986 struct intel_engine_cs *engine = req->engine;
987 unsigned int irq, cpu;
Chris Wilson05235c52016-07-20 09:21:08 +0100988
989 /* When waiting for high frequency requests, e.g. during synchronous
990 * rendering split between the CPU and GPU, the finite amount of time
991 * required to set up the irq and wait upon it limits the response
992 * rate. By busywaiting on the request completion for a short while we
993 * can service the high frequency waits as quick as possible. However,
994 * if it is a slow request, we want to sleep as quickly as possible.
995 * The tradeoff between waiting and sleeping is roughly the time it
996 * takes to sleep on a request, on the order of a microsecond.
997 */
998
Chris Wilsonc33ed062017-02-17 15:13:01 +0000999 irq = atomic_read(&engine->irq_count);
Chris Wilson05235c52016-07-20 09:21:08 +01001000 timeout_us += local_clock_us(&cpu);
1001 do {
Chris Wilson754c9fd2017-02-23 07:44:14 +00001002 if (seqno != i915_gem_request_global_seqno(req))
1003 break;
1004
1005 if (i915_seqno_passed(intel_engine_get_seqno(req->engine),
1006 seqno))
Chris Wilson05235c52016-07-20 09:21:08 +01001007 return true;
1008
Chris Wilsonc33ed062017-02-17 15:13:01 +00001009 /* Seqno are meant to be ordered *before* the interrupt. If
1010 * we see an interrupt without a corresponding seqno advance,
1011 * assume we won't see one in the near future but require
1012 * the engine->seqno_barrier() to fixup coherency.
1013 */
1014 if (atomic_read(&engine->irq_count) != irq)
1015 break;
1016
Chris Wilson05235c52016-07-20 09:21:08 +01001017 if (signal_pending_state(state, current))
1018 break;
1019
1020 if (busywait_stop(timeout_us, cpu))
1021 break;
1022
Christian Borntraegerf2f09a42016-10-25 11:03:14 +02001023 cpu_relax();
Chris Wilson05235c52016-07-20 09:21:08 +01001024 } while (!need_resched());
1025
1026 return false;
1027}
1028
Chris Wilsone0705112017-02-23 07:44:20 +00001029static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *request)
1030{
1031 if (likely(!i915_reset_in_progress(&request->i915->gpu_error)))
1032 return false;
1033
1034 __set_current_state(TASK_RUNNING);
1035 i915_reset(request->i915);
1036 return true;
1037}
1038
Chris Wilson05235c52016-07-20 09:21:08 +01001039/**
Chris Wilson776f3232016-08-04 07:52:40 +01001040 * i915_wait_request - wait until execution of request has finished
Chris Wilsone95433c2016-10-28 13:58:27 +01001041 * @req: the request to wait upon
Chris Wilsonea746f32016-09-09 14:11:49 +01001042 * @flags: how to wait
Chris Wilsone95433c2016-10-28 13:58:27 +01001043 * @timeout: how long to wait in jiffies
Chris Wilson05235c52016-07-20 09:21:08 +01001044 *
Chris Wilsone95433c2016-10-28 13:58:27 +01001045 * i915_wait_request() waits for the request to be completed, for a
1046 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1047 * unbounded wait).
Chris Wilson05235c52016-07-20 09:21:08 +01001048 *
Chris Wilsone95433c2016-10-28 13:58:27 +01001049 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1050 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1051 * must not specify that the wait is locked.
1052 *
1053 * Returns the remaining time (in jiffies) if the request completed, which may
1054 * be zero or -ETIME if the request is unfinished after the timeout expires.
1055 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1056 * pending before the request completes.
Chris Wilson05235c52016-07-20 09:21:08 +01001057 */
Chris Wilsone95433c2016-10-28 13:58:27 +01001058long i915_wait_request(struct drm_i915_gem_request *req,
1059 unsigned int flags,
1060 long timeout)
Chris Wilson05235c52016-07-20 09:21:08 +01001061{
Chris Wilsonea746f32016-09-09 14:11:49 +01001062 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1063 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
Chris Wilson4b36b2e2017-02-23 07:44:10 +00001064 wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue;
Chris Wilsona49625f2017-02-23 07:44:19 +00001065 DEFINE_WAIT_FUNC(reset, default_wake_function);
1066 DEFINE_WAIT_FUNC(exec, default_wake_function);
Chris Wilson05235c52016-07-20 09:21:08 +01001067 struct intel_wait wait;
Chris Wilson05235c52016-07-20 09:21:08 +01001068
1069 might_sleep();
Chris Wilson22dd3bb2016-09-09 14:11:50 +01001070#if IS_ENABLED(CONFIG_LOCKDEP)
Chris Wilsone95433c2016-10-28 13:58:27 +01001071 GEM_BUG_ON(debug_locks &&
1072 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
Chris Wilson22dd3bb2016-09-09 14:11:50 +01001073 !!(flags & I915_WAIT_LOCKED));
1074#endif
Chris Wilsone95433c2016-10-28 13:58:27 +01001075 GEM_BUG_ON(timeout < 0);
Chris Wilson05235c52016-07-20 09:21:08 +01001076
Chris Wilson05235c52016-07-20 09:21:08 +01001077 if (i915_gem_request_completed(req))
Chris Wilsone95433c2016-10-28 13:58:27 +01001078 return timeout;
Chris Wilson05235c52016-07-20 09:21:08 +01001079
Chris Wilsone95433c2016-10-28 13:58:27 +01001080 if (!timeout)
1081 return -ETIME;
Chris Wilson05235c52016-07-20 09:21:08 +01001082
Tvrtko Ursulin936925022017-02-21 11:00:24 +00001083 trace_i915_gem_request_wait_begin(req, flags);
Chris Wilson05235c52016-07-20 09:21:08 +01001084
Chris Wilsona49625f2017-02-23 07:44:19 +00001085 add_wait_queue(&req->execute, &exec);
Chris Wilson7de53bf2017-02-23 07:44:11 +00001086 if (flags & I915_WAIT_LOCKED)
1087 add_wait_queue(errq, &reset);
1088
Chris Wilson56299fb2017-02-27 20:58:48 +00001089 intel_wait_init(&wait, req);
Chris Wilson754c9fd2017-02-23 07:44:14 +00001090
Chris Wilsond6a22892017-02-23 07:44:17 +00001091restart:
Chris Wilson0f2f61d2017-02-23 07:44:22 +00001092 do {
1093 set_current_state(state);
1094 if (intel_wait_update_request(&wait, req))
1095 break;
Chris Wilson754c9fd2017-02-23 07:44:14 +00001096
Chris Wilson0f2f61d2017-02-23 07:44:22 +00001097 if (flags & I915_WAIT_LOCKED &&
1098 __i915_wait_request_check_and_reset(req))
1099 continue;
Chris Wilson541ca6e2017-02-23 07:44:12 +00001100
Chris Wilson0f2f61d2017-02-23 07:44:22 +00001101 if (signal_pending_state(state, current)) {
1102 timeout = -ERESTARTSYS;
1103 goto complete;
1104 }
Chris Wilson541ca6e2017-02-23 07:44:12 +00001105
Chris Wilson0f2f61d2017-02-23 07:44:22 +00001106 if (!timeout) {
1107 timeout = -ETIME;
1108 goto complete;
1109 }
Chris Wilson541ca6e2017-02-23 07:44:12 +00001110
Chris Wilson0f2f61d2017-02-23 07:44:22 +00001111 timeout = io_schedule_timeout(timeout);
1112 } while (1);
Chris Wilson541ca6e2017-02-23 07:44:12 +00001113
Chris Wilson0f2f61d2017-02-23 07:44:22 +00001114 GEM_BUG_ON(!intel_wait_has_seqno(&wait));
Chris Wilsonfe497892017-02-23 07:44:13 +00001115 GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
Chris Wilson4680816b2016-10-28 13:58:48 +01001116
Daniel Vetter437c3082016-08-05 18:11:24 +02001117 /* Optimistic short spin before touching IRQs */
Chris Wilson05235c52016-07-20 09:21:08 +01001118 if (i915_spin_request(req, state, 5))
1119 goto complete;
1120
1121 set_current_state(state);
Chris Wilson05235c52016-07-20 09:21:08 +01001122 if (intel_engine_add_wait(req->engine, &wait))
1123 /* In order to check that we haven't missed the interrupt
1124 * as we enabled it, we need to kick ourselves to do a
1125 * coherent check on the seqno before we sleep.
1126 */
1127 goto wakeup;
1128
Chris Wilson24f417e2017-02-23 07:44:21 +00001129 if (flags & I915_WAIT_LOCKED)
1130 __i915_wait_request_check_and_reset(req);
1131
Chris Wilson05235c52016-07-20 09:21:08 +01001132 for (;;) {
1133 if (signal_pending_state(state, current)) {
Chris Wilsone95433c2016-10-28 13:58:27 +01001134 timeout = -ERESTARTSYS;
Chris Wilson05235c52016-07-20 09:21:08 +01001135 break;
1136 }
1137
Chris Wilsone95433c2016-10-28 13:58:27 +01001138 if (!timeout) {
1139 timeout = -ETIME;
Chris Wilson05235c52016-07-20 09:21:08 +01001140 break;
1141 }
1142
Chris Wilsone95433c2016-10-28 13:58:27 +01001143 timeout = io_schedule_timeout(timeout);
1144
Chris Wilson754c9fd2017-02-23 07:44:14 +00001145 if (intel_wait_complete(&wait) &&
1146 intel_wait_check_request(&wait, req))
Chris Wilson05235c52016-07-20 09:21:08 +01001147 break;
1148
1149 set_current_state(state);
1150
1151wakeup:
1152 /* Carefully check if the request is complete, giving time
1153 * for the seqno to be visible following the interrupt.
1154 * We also have to check in case we are kicked by the GPU
1155 * reset in order to drop the struct_mutex.
1156 */
1157 if (__i915_request_irq_complete(req))
1158 break;
1159
Chris Wilson221fe792016-09-09 14:11:51 +01001160 /* If the GPU is hung, and we hold the lock, reset the GPU
1161 * and then check for completion. On a full reset, the engine's
1162 * HW seqno will be advanced passed us and we are complete.
1163 * If we do a partial reset, we have to wait for the GPU to
1164 * resume and update the breadcrumb.
1165 *
1166 * If we don't hold the mutex, we can just wait for the worker
1167 * to come along and update the breadcrumb (either directly
1168 * itself, or indirectly by recovering the GPU).
1169 */
1170 if (flags & I915_WAIT_LOCKED &&
Chris Wilsone0705112017-02-23 07:44:20 +00001171 __i915_wait_request_check_and_reset(req))
Chris Wilson221fe792016-09-09 14:11:51 +01001172 continue;
Chris Wilson221fe792016-09-09 14:11:51 +01001173
Chris Wilson05235c52016-07-20 09:21:08 +01001174 /* Only spin if we know the GPU is processing this request */
1175 if (i915_spin_request(req, state, 2))
1176 break;
Chris Wilsond6a22892017-02-23 07:44:17 +00001177
1178 if (!intel_wait_check_request(&wait, req)) {
1179 intel_engine_remove_wait(req->engine, &wait);
1180 goto restart;
1181 }
Chris Wilson05235c52016-07-20 09:21:08 +01001182 }
Chris Wilson05235c52016-07-20 09:21:08 +01001183
1184 intel_engine_remove_wait(req->engine, &wait);
Chris Wilson05235c52016-07-20 09:21:08 +01001185complete:
Chris Wilsona49625f2017-02-23 07:44:19 +00001186 __set_current_state(TASK_RUNNING);
Chris Wilson7de53bf2017-02-23 07:44:11 +00001187 if (flags & I915_WAIT_LOCKED)
1188 remove_wait_queue(errq, &reset);
Chris Wilsona49625f2017-02-23 07:44:19 +00001189 remove_wait_queue(&req->execute, &exec);
Chris Wilson05235c52016-07-20 09:21:08 +01001190 trace_i915_gem_request_wait_end(req);
1191
Chris Wilsone95433c2016-10-28 13:58:27 +01001192 return timeout;
Chris Wilson05235c52016-07-20 09:21:08 +01001193}
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001194
Chris Wilson28176ef2016-10-28 13:58:56 +01001195static void engine_retire_requests(struct intel_engine_cs *engine)
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001196{
1197 struct drm_i915_gem_request *request, *next;
Chris Wilson754c9fd2017-02-23 07:44:14 +00001198 u32 seqno = intel_engine_get_seqno(engine);
1199 LIST_HEAD(retire);
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001200
Chris Wilson754c9fd2017-02-23 07:44:14 +00001201 spin_lock_irq(&engine->timeline->lock);
Chris Wilson73cb9702016-10-28 13:58:46 +01001202 list_for_each_entry_safe(request, next,
1203 &engine->timeline->requests, link) {
Chris Wilson754c9fd2017-02-23 07:44:14 +00001204 if (!i915_seqno_passed(seqno, request->global_seqno))
1205 break;
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001206
Chris Wilson754c9fd2017-02-23 07:44:14 +00001207 list_move_tail(&request->link, &retire);
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001208 }
Chris Wilson754c9fd2017-02-23 07:44:14 +00001209 spin_unlock_irq(&engine->timeline->lock);
1210
1211 list_for_each_entry_safe(request, next, &retire, link)
1212 i915_gem_request_retire(request);
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001213}
1214
1215void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1216{
1217 struct intel_engine_cs *engine;
Chris Wilson28176ef2016-10-28 13:58:56 +01001218 enum intel_engine_id id;
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001219
1220 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1221
Chris Wilson28176ef2016-10-28 13:58:56 +01001222 if (!dev_priv->gt.active_requests)
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001223 return;
1224
Chris Wilson28176ef2016-10-28 13:58:56 +01001225 for_each_engine(engine, dev_priv, id)
1226 engine_retire_requests(engine);
Chris Wilson4b8de8e2016-08-04 07:52:42 +01001227}
Chris Wilsonc835c552017-02-13 17:15:21 +00001228
1229#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1230#include "selftests/mock_request.c"
1231#include "selftests/i915_gem_request.c"
1232#endif