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gerrit-public.fairphone.software / kernel / msm-5.4 / caafb95d6952c4c977c1b9ddf32bb56bfcda8059 / . / drivers / net / ethernet / intel / i40e / i40e_common.c
blob: c65f4e8e6cee0800c5568fed1984e3914e3231ac [file] [log] [blame]
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
Greg Rosedc641b72013-12-18 13:45:51 +0000[diff] [blame]4 * Copyright(c) 2013 - 2014 Intel Corporation.
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
Greg Rosedc641b72013-12-18 13:45:51 +0000[diff] [blame]15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]45 case I40E_DEV_ID_SFP_XL710:
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]53 hw->mac.type = I40E_MAC_XL710;
54 break;
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]55 case I40E_DEV_ID_VF:
56 case I40E_DEV_ID_VF_HV:
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]57 hw->mac.type = I40E_MAC_VF;
58 break;
59 default:
60 hw->mac.type = I40E_MAC_GENERIC;
61 break;
62 }
63 } else {
64 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
65 }
66
67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw->mac.type, status);
69 return status;
70}
71
72/**
73 * i40e_debug_aq
74 * @hw: debug mask related to admin queue
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]75 * @mask: debug mask
76 * @desc: pointer to admin queue descriptor
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]77 * @buffer: pointer to command buffer
78 *
79 * Dumps debug log about adminq command with descriptor contents.
80 **/
81void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
82 void *buffer)
83{
84 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
85 u8 *aq_buffer = (u8 *)buffer;
86 u32 data[4];
87 u32 i = 0;
88
89 if ((!(mask & hw->debug_mask)) || (desc == NULL))
90 return;
91
92 i40e_debug(hw, mask,
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
95 aq_desc->retval);
96 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc->cookie_high, aq_desc->cookie_low);
98 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc->params.internal.param0,
100 aq_desc->params.internal.param1);
101 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc->params.external.addr_high,
103 aq_desc->params.external.addr_low);
104
105 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
106 memset(data, 0, sizeof(data));
107 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
108 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
109 data[((i % 16) / 4)] |=
110 ((u32)aq_buffer[i]) << (8 * (i % 4));
111 if ((i % 16) == 15) {
112 i40e_debug(hw, mask,
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i - 15, data[0], data[1], data[2],
115 data[3]);
116 memset(data, 0, sizeof(data));
117 }
118 }
119 if ((i % 16) != 0)
120 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
121 i - (i % 16), data[0], data[1], data[2],
122 data[3]);
123 }
124}
125
126/**
Anjali Singhai Jaine1860d82013-11-28 06:39:45 +0000[diff] [blame]127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
129 *
130 * Returns true if Queue is enabled else false.
131 **/
132bool i40e_check_asq_alive(struct i40e_hw *hw)
133{
Kevin Scott8b833b42014-04-09 05:58:54 +0000[diff] [blame]134 if (hw->aq.asq.len)
135 return !!(rd32(hw, hw->aq.asq.len) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK);
137 else
138 return false;
Anjali Singhai Jaine1860d82013-11-28 06:39:45 +0000[diff] [blame]139}
140
141/**
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
145 *
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
148 **/
149i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
150 bool unloading)
151{
152 struct i40e_aq_desc desc;
153 struct i40e_aqc_queue_shutdown *cmd =
154 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
155 i40e_status status;
156
157 i40e_fill_default_direct_cmd_desc(&desc,
158 i40e_aqc_opc_queue_shutdown);
159
160 if (unloading)
161 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
162 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
163
164 return status;
165}
166
Jesse Brandeburg206812b2014-02-12 01:45:33 +0000[diff] [blame]167/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
169 * packet type.
170 *
171 * Macros are used to shorten the table lines and make this table human
172 * readable.
173 *
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
177 *
178 * Typical work flow:
179 *
180 * IF NOT i40e_ptype_lookup[ptype].known
181 * THEN
182 * Packet is unknown
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
185 * ELSE
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
187 * ENDIF
188 */
189
190/* macro to make the table lines short */
191#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
192 { PTYPE, \
193 1, \
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
202
203#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
205
206/* shorter macros makes the table fit but are terse */
207#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
210
211/* Lookup table mapping the HW PTYPE to the bit field for decoding */
212struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
217 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
225 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
226 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
243 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
244 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
245
246 /* IPv4 --> IPv4 */
247 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
248 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
249 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
252 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
253 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
254
255 /* IPv4 --> IPv6 */
256 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
257 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
258 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
261 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
262 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
263
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
266
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
275
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
284
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
287
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
296
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
305
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
308
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
317
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
326
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
329 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
330 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
333 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
334 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
335
336 /* IPv6 --> IPv4 */
337 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
338 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
339 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
342 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
343 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
344
345 /* IPv6 --> IPv6 */
346 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
347 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
348 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
351 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
352 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
353
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
356
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
365
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
374
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
377
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
386
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
395
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
398
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
407
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
416
417 /* unused entries */
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
424
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
435
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
446
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
457
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
468
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
479
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
490
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
501
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
512
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
523
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
530};
531
532
Anjali Singhai Jaine1860d82013-11-28 06:39:45 +0000[diff] [blame]533/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
536 *
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
544 **/
545i40e_status i40e_init_shared_code(struct i40e_hw *hw)
546{
547 i40e_status status = 0;
548 u32 reg;
549
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]550 i40e_set_mac_type(hw);
551
552 switch (hw->mac.type) {
553 case I40E_MAC_XL710:
554 break;
555 default:
556 return I40E_ERR_DEVICE_NOT_SUPPORTED;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]557 }
558
Shannon Nelsonaf89d26c2013-12-11 08:17:14 +0000[diff] [blame]559 hw->phy.get_link_info = true;
560
561 /* Determine port number */
562 reg = rd32(hw, I40E_PFGEN_PORTNUM);
563 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
564 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
565 hw->port = (u8)reg;
566
Shannon Nelson5f9116a2013-12-11 08:17:13 +0000[diff] [blame]567 /* Determine the PF number based on the PCI fn */
568 reg = rd32(hw, I40E_GLPCI_CAPSUP);
569 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
570 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
571 else
572 hw->pf_id = (u8)hw->bus.func;
573
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]574 status = i40e_init_nvm(hw);
575 return status;
576}
577
578/**
579 * i40e_aq_mac_address_read - Retrieve the MAC addresses
580 * @hw: pointer to the hw struct
581 * @flags: a return indicator of what addresses were added to the addr store
582 * @addrs: the requestor's mac addr store
583 * @cmd_details: pointer to command details structure or NULL
584 **/
585static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
586 u16 *flags,
587 struct i40e_aqc_mac_address_read_data *addrs,
588 struct i40e_asq_cmd_details *cmd_details)
589{
590 struct i40e_aq_desc desc;
591 struct i40e_aqc_mac_address_read *cmd_data =
592 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
593 i40e_status status;
594
595 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
596 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
597
598 status = i40e_asq_send_command(hw, &desc, addrs,
599 sizeof(*addrs), cmd_details);
600 *flags = le16_to_cpu(cmd_data->command_flags);
601
602 return status;
603}
604
605/**
606 * i40e_aq_mac_address_write - Change the MAC addresses
607 * @hw: pointer to the hw struct
608 * @flags: indicates which MAC to be written
609 * @mac_addr: address to write
610 * @cmd_details: pointer to command details structure or NULL
611 **/
612i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
613 u16 flags, u8 *mac_addr,
614 struct i40e_asq_cmd_details *cmd_details)
615{
616 struct i40e_aq_desc desc;
617 struct i40e_aqc_mac_address_write *cmd_data =
618 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
619 i40e_status status;
620
621 i40e_fill_default_direct_cmd_desc(&desc,
622 i40e_aqc_opc_mac_address_write);
623 cmd_data->command_flags = cpu_to_le16(flags);
Kamil Krawczyk55c29c32013-12-18 13:45:52 +0000[diff] [blame]624 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
625 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
626 ((u32)mac_addr[3] << 16) |
627 ((u32)mac_addr[4] << 8) |
628 mac_addr[5]);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]629
630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
631
632 return status;
633}
634
635/**
636 * i40e_get_mac_addr - get MAC address
637 * @hw: pointer to the HW structure
638 * @mac_addr: pointer to MAC address
639 *
640 * Reads the adapter's MAC address from register
641 **/
642i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
643{
644 struct i40e_aqc_mac_address_read_data addrs;
645 i40e_status status;
646 u16 flags = 0;
647
648 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
649
650 if (flags & I40E_AQC_LAN_ADDR_VALID)
651 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
652
653 return status;
654}
655
656/**
Neerav Parikh1f224ad2014-02-12 01:45:31 +0000[diff] [blame]657 * i40e_get_port_mac_addr - get Port MAC address
658 * @hw: pointer to the HW structure
659 * @mac_addr: pointer to Port MAC address
660 *
661 * Reads the adapter's Port MAC address
662 **/
663i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
664{
665 struct i40e_aqc_mac_address_read_data addrs;
666 i40e_status status;
667 u16 flags = 0;
668
669 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
670 if (status)
671 return status;
672
673 if (flags & I40E_AQC_PORT_ADDR_VALID)
674 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
675 else
676 status = I40E_ERR_INVALID_MAC_ADDR;
677
678 return status;
679}
680
681/**
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]682 * i40e_pre_tx_queue_cfg - pre tx queue configure
683 * @hw: pointer to the HW structure
684 * @queue: target pf queue index
685 * @enable: state change request
686 *
687 * Handles hw requirement to indicate intention to enable
688 * or disable target queue.
689 **/
690void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
691{
Shannon Nelsondfb699f2014-05-22 06:32:28 +0000[diff] [blame]692 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]693 u32 reg_block = 0;
Shannon Nelsondfb699f2014-05-22 06:32:28 +0000[diff] [blame]694 u32 reg_val;
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]695
Christopher Pau24a768c2014-06-04 20:41:59 +0000[diff] [blame]696 if (abs_queue_idx >= 128) {
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]697 reg_block = abs_queue_idx / 128;
Christopher Pau24a768c2014-06-04 20:41:59 +0000[diff] [blame]698 abs_queue_idx %= 128;
699 }
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]700
701 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
702 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
703 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
704
705 if (enable)
706 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
707 else
708 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
709
710 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
711}
712
713/**
Jesse Brandeburgbe405eb2013-11-20 10:02:50 +0000[diff] [blame]714 * i40e_get_media_type - Gets media type
715 * @hw: pointer to the hardware structure
716 **/
717static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
718{
719 enum i40e_media_type media;
720
721 switch (hw->phy.link_info.phy_type) {
722 case I40E_PHY_TYPE_10GBASE_SR:
723 case I40E_PHY_TYPE_10GBASE_LR:
724 case I40E_PHY_TYPE_40GBASE_SR4:
725 case I40E_PHY_TYPE_40GBASE_LR4:
726 media = I40E_MEDIA_TYPE_FIBER;
727 break;
728 case I40E_PHY_TYPE_100BASE_TX:
729 case I40E_PHY_TYPE_1000BASE_T:
730 case I40E_PHY_TYPE_10GBASE_T:
731 media = I40E_MEDIA_TYPE_BASET;
732 break;
733 case I40E_PHY_TYPE_10GBASE_CR1_CU:
734 case I40E_PHY_TYPE_40GBASE_CR4_CU:
735 case I40E_PHY_TYPE_10GBASE_CR1:
736 case I40E_PHY_TYPE_40GBASE_CR4:
737 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
738 media = I40E_MEDIA_TYPE_DA;
739 break;
740 case I40E_PHY_TYPE_1000BASE_KX:
741 case I40E_PHY_TYPE_10GBASE_KX4:
742 case I40E_PHY_TYPE_10GBASE_KR:
743 case I40E_PHY_TYPE_40GBASE_KR4:
744 media = I40E_MEDIA_TYPE_BACKPLANE;
745 break;
746 case I40E_PHY_TYPE_SGMII:
747 case I40E_PHY_TYPE_XAUI:
748 case I40E_PHY_TYPE_XFI:
749 case I40E_PHY_TYPE_XLAUI:
750 case I40E_PHY_TYPE_XLPPI:
751 default:
752 media = I40E_MEDIA_TYPE_UNKNOWN;
753 break;
754 }
755
756 return media;
757}
758
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]759#define I40E_PF_RESET_WAIT_COUNT_A0 200
Shannon Nelsond0ff5682014-04-23 04:50:06 +0000[diff] [blame]760#define I40E_PF_RESET_WAIT_COUNT 100
Jesse Brandeburgbe405eb2013-11-20 10:02:50 +0000[diff] [blame]761/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]762 * i40e_pf_reset - Reset the PF
763 * @hw: pointer to the hardware structure
764 *
765 * Assuming someone else has triggered a global reset,
766 * assure the global reset is complete and then reset the PF
767 **/
768i40e_status i40e_pf_reset(struct i40e_hw *hw)
769{
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]770 u32 cnt = 0;
Shannon Nelson42794bd2013-12-11 08:17:10 +0000[diff] [blame]771 u32 cnt1 = 0;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]772 u32 reg = 0;
773 u32 grst_del;
774
775 /* Poll for Global Reset steady state in case of recent GRST.
776 * The grst delay value is in 100ms units, and we'll wait a
777 * couple counts longer to be sure we don't just miss the end.
778 */
779 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
780 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]781 for (cnt = 0; cnt < grst_del + 2; cnt++) {
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]782 reg = rd32(hw, I40E_GLGEN_RSTAT);
783 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
784 break;
785 msleep(100);
786 }
787 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
788 hw_dbg(hw, "Global reset polling failed to complete.\n");
789 return I40E_ERR_RESET_FAILED;
790 }
791
Shannon Nelson42794bd2013-12-11 08:17:10 +0000[diff] [blame]792 /* Now Wait for the FW to be ready */
793 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
794 reg = rd32(hw, I40E_GLNVM_ULD);
795 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
796 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
797 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
798 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
799 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
800 break;
801 }
802 usleep_range(10000, 20000);
803 }
804 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
805 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
806 hw_dbg(hw, "wait for FW Reset complete timedout\n");
807 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
808 return I40E_ERR_RESET_FAILED;
809 }
810
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]811 /* If there was a Global Reset in progress when we got here,
812 * we don't need to do the PF Reset
813 */
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]814 if (!cnt) {
815 if (hw->revision_id == 0)
816 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
817 else
818 cnt = I40E_PF_RESET_WAIT_COUNT;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]819 reg = rd32(hw, I40E_PFGEN_CTRL);
820 wr32(hw, I40E_PFGEN_CTRL,
821 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]822 for (; cnt; cnt--) {
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]823 reg = rd32(hw, I40E_PFGEN_CTRL);
824 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
825 break;
826 usleep_range(1000, 2000);
827 }
828 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
829 hw_dbg(hw, "PF reset polling failed to complete.\n");
830 return I40E_ERR_RESET_FAILED;
831 }
832 }
833
834 i40e_clear_pxe_mode(hw);
Shannon Nelson922680b2013-12-18 05:29:17 +0000[diff] [blame]835
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]836 return 0;
837}
838
839/**
Shannon Nelson838d41d2014-06-04 20:41:27 +0000[diff] [blame]840 * i40e_clear_hw - clear out any left over hw state
841 * @hw: pointer to the hw struct
842 *
843 * Clear queues and interrupts, typically called at init time,
844 * but after the capabilities have been found so we know how many
845 * queues and msix vectors have been allocated.
846 **/
847void i40e_clear_hw(struct i40e_hw *hw)
848{
849 u32 num_queues, base_queue;
850 u32 num_pf_int;
851 u32 num_vf_int;
852 u32 num_vfs;
853 u32 i, j;
854 u32 val;
855 u32 eol = 0x7ff;
856
857 /* get number of interrupts, queues, and vfs */
858 val = rd32(hw, I40E_GLPCI_CNF2);
859 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
860 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
861 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
862 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
863
864 val = rd32(hw, I40E_PFLAN_QALLOC);
865 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
866 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
867 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
868 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
869 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
870 num_queues = (j - base_queue) + 1;
871 else
872 num_queues = 0;
873
874 val = rd32(hw, I40E_PF_VT_PFALLOC);
875 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
876 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
877 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
878 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
879 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
880 num_vfs = (j - i) + 1;
881 else
882 num_vfs = 0;
883
884 /* stop all the interrupts */
885 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
886 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
887 for (i = 0; i < num_pf_int - 2; i++)
888 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
889
890 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
891 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
892 wr32(hw, I40E_PFINT_LNKLST0, val);
893 for (i = 0; i < num_pf_int - 2; i++)
894 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
895 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
896 for (i = 0; i < num_vfs; i++)
897 wr32(hw, I40E_VPINT_LNKLST0(i), val);
898 for (i = 0; i < num_vf_int - 2; i++)
899 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
900
901 /* warn the HW of the coming Tx disables */
902 for (i = 0; i < num_queues; i++) {
903 u32 abs_queue_idx = base_queue + i;
904 u32 reg_block = 0;
905
906 if (abs_queue_idx >= 128) {
907 reg_block = abs_queue_idx / 128;
908 abs_queue_idx %= 128;
909 }
910
911 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
912 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
913 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
914 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
915
916 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
917 }
918 udelay(400);
919
920 /* stop all the queues */
921 for (i = 0; i < num_queues; i++) {
922 wr32(hw, I40E_QINT_TQCTL(i), 0);
923 wr32(hw, I40E_QTX_ENA(i), 0);
924 wr32(hw, I40E_QINT_RQCTL(i), 0);
925 wr32(hw, I40E_QRX_ENA(i), 0);
926 }
927
928 /* short wait for all queue disables to settle */
929 udelay(50);
930}
931
932/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]933 * i40e_clear_pxe_mode - clear pxe operations mode
934 * @hw: pointer to the hw struct
935 *
936 * Make sure all PXE mode settings are cleared, including things
937 * like descriptor fetch/write-back mode.
938 **/
939void i40e_clear_pxe_mode(struct i40e_hw *hw)
940{
941 u32 reg;
942
Shannon Nelsonc9b9b0a2014-04-09 05:59:05 +0000[diff] [blame]943 if (i40e_check_asq_alive(hw))
944 i40e_aq_clear_pxe_mode(hw, NULL);
945
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]946 /* Clear single descriptor fetch/write-back mode */
947 reg = rd32(hw, I40E_GLLAN_RCTL_0);
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]948
949 if (hw->revision_id == 0) {
950 /* As a work around clear PXE_MODE instead of setting it */
951 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
952 } else {
953 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
954 }
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]955}
956
957/**
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]958 * i40e_led_is_mine - helper to find matching led
959 * @hw: pointer to the hw struct
960 * @idx: index into GPIO registers
961 *
962 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
963 */
964static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
965{
966 u32 gpio_val = 0;
967 u32 port;
968
969 if (!hw->func_caps.led[idx])
970 return 0;
971
972 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
973 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
974 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
975
976 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
977 * if it is not our port then ignore
978 */
979 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
980 (port != hw->port))
981 return 0;
982
983 return gpio_val;
984}
985
986#define I40E_LED0 22
987#define I40E_LINK_ACTIVITY 0xC
988
989/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]990 * i40e_led_get - return current on/off mode
991 * @hw: pointer to the hw struct
992 *
993 * The value returned is the 'mode' field as defined in the
994 * GPIO register definitions: 0x0 = off, 0xf = on, and other
995 * values are variations of possible behaviors relating to
996 * blink, link, and wire.
997 **/
998u32 i40e_led_get(struct i40e_hw *hw)
999{
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1000 u32 mode = 0;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1001 int i;
1002
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1003 /* as per the documentation GPIO 22-29 are the LED
1004 * GPIO pins named LED0..LED7
1005 */
1006 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1007 u32 gpio_val = i40e_led_is_mine(hw, i);
1008
1009 if (!gpio_val)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1010 continue;
1011
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1012 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1013 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1014 break;
1015 }
1016
1017 return mode;
1018}
1019
1020/**
1021 * i40e_led_set - set new on/off mode
1022 * @hw: pointer to the hw struct
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1023 * @mode: 0=off, 0xf=on (else see manual for mode details)
1024 * @blink: true if the LED should blink when on, false if steady
1025 *
1026 * if this function is used to turn on the blink it should
1027 * be used to disable the blink when restoring the original state.
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1028 **/
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1029void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1030{
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1031 int i;
1032
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1033 if (mode & 0xfffffff0)
1034 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1035
1036 /* as per the documentation GPIO 22-29 are the LED
1037 * GPIO pins named LED0..LED7
1038 */
1039 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1040 u32 gpio_val = i40e_led_is_mine(hw, i);
1041
1042 if (!gpio_val)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1043 continue;
1044
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1045 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1046 /* this & is a bit of paranoia, but serves as a range check */
1047 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1048 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1049
1050 if (mode == I40E_LINK_ACTIVITY)
1051 blink = false;
1052
1053 gpio_val |= (blink ? 1 : 0) <<
1054 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1055
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1056 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1057 break;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1058 }
1059}
1060
1061/* Admin command wrappers */
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1062
1063/**
Catherine Sullivan8109e122014-06-04 08:45:24 +0000[diff] [blame]1064 * i40e_aq_get_phy_capabilities
1065 * @hw: pointer to the hw struct
1066 * @abilities: structure for PHY capabilities to be filled
1067 * @qualified_modules: report Qualified Modules
1068 * @report_init: report init capabilities (active are default)
1069 * @cmd_details: pointer to command details structure or NULL
1070 *
1071 * Returns the various PHY abilities supported on the Port.
1072 **/
1073i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1074 bool qualified_modules, bool report_init,
1075 struct i40e_aq_get_phy_abilities_resp *abilities,
1076 struct i40e_asq_cmd_details *cmd_details)
1077{
1078 struct i40e_aq_desc desc;
1079 i40e_status status;
1080 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1081
1082 if (!abilities)
1083 return I40E_ERR_PARAM;
1084
1085 i40e_fill_default_direct_cmd_desc(&desc,
1086 i40e_aqc_opc_get_phy_abilities);
1087
1088 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1089 if (abilities_size > I40E_AQ_LARGE_BUF)
1090 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1091
1092 if (qualified_modules)
1093 desc.params.external.param0 |=
1094 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1095
1096 if (report_init)
1097 desc.params.external.param0 |=
1098 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1099
1100 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1101 cmd_details);
1102
1103 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1104 status = I40E_ERR_UNKNOWN_PHY;
1105
1106 return status;
1107}
1108
1109/**
Catherine Sullivanc56999f2014-06-04 08:45:26 +0000[diff] [blame]1110 * i40e_aq_set_phy_config
1111 * @hw: pointer to the hw struct
1112 * @config: structure with PHY configuration to be set
1113 * @cmd_details: pointer to command details structure or NULL
1114 *
1115 * Set the various PHY configuration parameters
1116 * supported on the Port.One or more of the Set PHY config parameters may be
1117 * ignored in an MFP mode as the PF may not have the privilege to set some
1118 * of the PHY Config parameters. This status will be indicated by the
1119 * command response.
1120 **/
1121enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1122 struct i40e_aq_set_phy_config *config,
1123 struct i40e_asq_cmd_details *cmd_details)
1124{
1125 struct i40e_aq_desc desc;
1126 struct i40e_aq_set_phy_config *cmd =
1127 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1128 enum i40e_status_code status;
1129
1130 if (!config)
1131 return I40E_ERR_PARAM;
1132
1133 i40e_fill_default_direct_cmd_desc(&desc,
1134 i40e_aqc_opc_set_phy_config);
1135
1136 *cmd = *config;
1137
1138 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1139
1140 return status;
1141}
1142
1143/**
1144 * i40e_set_fc
1145 * @hw: pointer to the hw struct
1146 *
1147 * Set the requested flow control mode using set_phy_config.
1148 **/
1149enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1150 bool atomic_restart)
1151{
1152 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1153 struct i40e_aq_get_phy_abilities_resp abilities;
1154 struct i40e_aq_set_phy_config config;
1155 enum i40e_status_code status;
1156 u8 pause_mask = 0x0;
1157
1158 *aq_failures = 0x0;
1159
1160 switch (fc_mode) {
1161 case I40E_FC_FULL:
1162 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1163 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1164 break;
1165 case I40E_FC_RX_PAUSE:
1166 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1167 break;
1168 case I40E_FC_TX_PAUSE:
1169 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1170 break;
1171 default:
1172 break;
1173 }
1174
1175 /* Get the current phy config */
1176 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1177 NULL);
1178 if (status) {
1179 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1180 return status;
1181 }
1182
1183 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1184 /* clear the old pause settings */
1185 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1186 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1187 /* set the new abilities */
1188 config.abilities |= pause_mask;
1189 /* If the abilities have changed, then set the new config */
1190 if (config.abilities != abilities.abilities) {
1191 /* Auto restart link so settings take effect */
1192 if (atomic_restart)
1193 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1194 /* Copy over all the old settings */
1195 config.phy_type = abilities.phy_type;
1196 config.link_speed = abilities.link_speed;
1197 config.eee_capability = abilities.eee_capability;
1198 config.eeer = abilities.eeer_val;
1199 config.low_power_ctrl = abilities.d3_lpan;
1200 status = i40e_aq_set_phy_config(hw, &config, NULL);
1201
1202 if (status)
1203 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1204 }
1205 /* Update the link info */
1206 status = i40e_update_link_info(hw, true);
1207 if (status) {
1208 /* Wait a little bit (on 40G cards it sometimes takes a really
1209 * long time for link to come back from the atomic reset)
1210 * and try once more
1211 */
1212 msleep(1000);
1213 status = i40e_update_link_info(hw, true);
1214 }
1215 if (status)
1216 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1217
1218 return status;
1219}
1220
1221/**
Shannon Nelsonc9b9b0a2014-04-09 05:59:05 +0000[diff] [blame]1222 * i40e_aq_clear_pxe_mode
1223 * @hw: pointer to the hw struct
1224 * @cmd_details: pointer to command details structure or NULL
1225 *
1226 * Tell the firmware that the driver is taking over from PXE
1227 **/
1228i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1229 struct i40e_asq_cmd_details *cmd_details)
1230{
1231 i40e_status status;
1232 struct i40e_aq_desc desc;
1233 struct i40e_aqc_clear_pxe *cmd =
1234 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1235
1236 i40e_fill_default_direct_cmd_desc(&desc,
1237 i40e_aqc_opc_clear_pxe_mode);
1238
1239 cmd->rx_cnt = 0x2;
1240
1241 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1242
1243 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1244
1245 return status;
1246}
1247
1248/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1249 * i40e_aq_set_link_restart_an
1250 * @hw: pointer to the hw struct
Catherine Sullivan1ac978a2014-06-04 01:23:20 +0000[diff] [blame]1251 * @enable_link: if true: enable link, if false: disable link
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1252 * @cmd_details: pointer to command details structure or NULL
1253 *
1254 * Sets up the link and restarts the Auto-Negotiation over the link.
1255 **/
1256i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
Catherine Sullivan1ac978a2014-06-04 01:23:20 +0000[diff] [blame]1257 bool enable_link,
1258 struct i40e_asq_cmd_details *cmd_details)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1259{
1260 struct i40e_aq_desc desc;
1261 struct i40e_aqc_set_link_restart_an *cmd =
1262 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1263 i40e_status status;
1264
1265 i40e_fill_default_direct_cmd_desc(&desc,
1266 i40e_aqc_opc_set_link_restart_an);
1267
1268 cmd->command = I40E_AQ_PHY_RESTART_AN;
Catherine Sullivan1ac978a2014-06-04 01:23:20 +0000[diff] [blame]1269 if (enable_link)
1270 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1271 else
1272 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1273
1274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1275
1276 return status;
1277}
1278
1279/**
1280 * i40e_aq_get_link_info
1281 * @hw: pointer to the hw struct
1282 * @enable_lse: enable/disable LinkStatusEvent reporting
1283 * @link: pointer to link status structure - optional
1284 * @cmd_details: pointer to command details structure or NULL
1285 *
1286 * Returns the link status of the adapter.
1287 **/
1288i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1289 bool enable_lse, struct i40e_link_status *link,
1290 struct i40e_asq_cmd_details *cmd_details)
1291{
1292 struct i40e_aq_desc desc;
1293 struct i40e_aqc_get_link_status *resp =
1294 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1295 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1296 i40e_status status;
Catherine Sullivanc56999f2014-06-04 08:45:26 +0000[diff] [blame]1297 bool tx_pause, rx_pause;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1298 u16 command_flags;
1299
1300 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1301
1302 if (enable_lse)
1303 command_flags = I40E_AQ_LSE_ENABLE;
1304 else
1305 command_flags = I40E_AQ_LSE_DISABLE;
1306 resp->command_flags = cpu_to_le16(command_flags);
1307
1308 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1309
1310 if (status)
1311 goto aq_get_link_info_exit;
1312
1313 /* save off old link status information */
Mitch Williamsc36bd4a72013-12-18 13:46:04 +0000[diff] [blame]1314 hw->phy.link_info_old = *hw_link_info;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1315
1316 /* update link status */
1317 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
Jesse Brandeburgbe405eb2013-11-20 10:02:50 +0000[diff] [blame]1318 hw->phy.media_type = i40e_get_media_type(hw);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1319 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1320 hw_link_info->link_info = resp->link_info;
1321 hw_link_info->an_info = resp->an_info;
1322 hw_link_info->ext_info = resp->ext_info;
Kamil Krawczyk639dc372013-11-20 10:03:07 +0000[diff] [blame]1323 hw_link_info->loopback = resp->loopback;
Neerav Parikh6bb3f232014-04-01 07:11:56 +0000[diff] [blame]1324 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1325 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1326
Catherine Sullivanc56999f2014-06-04 08:45:26 +0000[diff] [blame]1327 /* update fc info */
1328 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1329 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1330 if (tx_pause & rx_pause)
1331 hw->fc.current_mode = I40E_FC_FULL;
1332 else if (tx_pause)
1333 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1334 else if (rx_pause)
1335 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1336 else
1337 hw->fc.current_mode = I40E_FC_NONE;
1338
Neerav Parikh6bb3f232014-04-01 07:11:56 +0000[diff] [blame]1339 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1340 hw_link_info->crc_enable = true;
1341 else
1342 hw_link_info->crc_enable = false;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1343
1344 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1345 hw_link_info->lse_enable = true;
1346 else
1347 hw_link_info->lse_enable = false;
1348
1349 /* save link status information */
1350 if (link)
Jesse Brandeburgd7595a22013-09-13 08:23:22 +0000[diff] [blame]1351 *link = *hw_link_info;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1352
1353 /* flag cleared so helper functions don't call AQ again */
1354 hw->phy.get_link_info = false;
1355
1356aq_get_link_info_exit:
1357 return status;
1358}
1359
1360/**
Catherine Sullivan8109e122014-06-04 08:45:24 +0000[diff] [blame]1361 * i40e_update_link_info
1362 * @hw: pointer to the hw struct
1363 * @enable_lse: enable/disable LinkStatusEvent reporting
1364 *
1365 * Returns the link status of the adapter
1366 **/
1367i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1368{
1369 struct i40e_aq_get_phy_abilities_resp abilities;
1370 i40e_status status;
1371
1372 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1373 if (status)
1374 return status;
1375
1376 status = i40e_aq_get_phy_capabilities(hw, false, false,
1377 &abilities, NULL);
1378 if (status)
1379 return status;
1380
1381 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1382 hw->phy.link_info.an_enabled = true;
1383 else
1384 hw->phy.link_info.an_enabled = false;
1385
1386 return status;
1387}
1388
1389/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1390 * i40e_aq_add_vsi
1391 * @hw: pointer to the hw struct
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1392 * @vsi_ctx: pointer to a vsi context struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1393 * @cmd_details: pointer to command details structure or NULL
1394 *
1395 * Add a VSI context to the hardware.
1396**/
1397i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1398 struct i40e_vsi_context *vsi_ctx,
1399 struct i40e_asq_cmd_details *cmd_details)
1400{
1401 struct i40e_aq_desc desc;
1402 struct i40e_aqc_add_get_update_vsi *cmd =
1403 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1404 struct i40e_aqc_add_get_update_vsi_completion *resp =
1405 (struct i40e_aqc_add_get_update_vsi_completion *)
1406 &desc.params.raw;
1407 i40e_status status;
1408
1409 i40e_fill_default_direct_cmd_desc(&desc,
1410 i40e_aqc_opc_add_vsi);
1411
1412 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1413 cmd->connection_type = vsi_ctx->connection_type;
1414 cmd->vf_id = vsi_ctx->vf_num;
1415 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1416
1417 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1418
1419 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1420 sizeof(vsi_ctx->info), cmd_details);
1421
1422 if (status)
1423 goto aq_add_vsi_exit;
1424
1425 vsi_ctx->seid = le16_to_cpu(resp->seid);
1426 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1427 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1428 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1429
1430aq_add_vsi_exit:
1431 return status;
1432}
1433
1434/**
1435 * i40e_aq_set_vsi_unicast_promiscuous
1436 * @hw: pointer to the hw struct
1437 * @seid: vsi number
1438 * @set: set unicast promiscuous enable/disable
1439 * @cmd_details: pointer to command details structure or NULL
1440 **/
1441i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
Mitch Williams885552a2013-12-21 05:44:41 +0000[diff] [blame]1442 u16 seid, bool set,
1443 struct i40e_asq_cmd_details *cmd_details)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1444{
1445 struct i40e_aq_desc desc;
1446 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1447 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1448 i40e_status status;
1449 u16 flags = 0;
1450
1451 i40e_fill_default_direct_cmd_desc(&desc,
1452 i40e_aqc_opc_set_vsi_promiscuous_modes);
1453
1454 if (set)
1455 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1456
1457 cmd->promiscuous_flags = cpu_to_le16(flags);
1458
1459 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1460
1461 cmd->seid = cpu_to_le16(seid);
1462 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1463
1464 return status;
1465}
1466
1467/**
1468 * i40e_aq_set_vsi_multicast_promiscuous
1469 * @hw: pointer to the hw struct
1470 * @seid: vsi number
1471 * @set: set multicast promiscuous enable/disable
1472 * @cmd_details: pointer to command details structure or NULL
1473 **/
1474i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1475 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1476{
1477 struct i40e_aq_desc desc;
1478 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1479 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1480 i40e_status status;
1481 u16 flags = 0;
1482
1483 i40e_fill_default_direct_cmd_desc(&desc,
1484 i40e_aqc_opc_set_vsi_promiscuous_modes);
1485
1486 if (set)
1487 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1488
1489 cmd->promiscuous_flags = cpu_to_le16(flags);
1490
1491 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1492
1493 cmd->seid = cpu_to_le16(seid);
1494 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1495
1496 return status;
1497}
1498
1499/**
1500 * i40e_aq_set_vsi_broadcast
1501 * @hw: pointer to the hw struct
1502 * @seid: vsi number
1503 * @set_filter: true to set filter, false to clear filter
1504 * @cmd_details: pointer to command details structure or NULL
1505 *
1506 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1507 **/
1508i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1509 u16 seid, bool set_filter,
1510 struct i40e_asq_cmd_details *cmd_details)
1511{
1512 struct i40e_aq_desc desc;
1513 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1514 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1515 i40e_status status;
1516
1517 i40e_fill_default_direct_cmd_desc(&desc,
1518 i40e_aqc_opc_set_vsi_promiscuous_modes);
1519
1520 if (set_filter)
1521 cmd->promiscuous_flags
1522 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1523 else
1524 cmd->promiscuous_flags
1525 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1526
1527 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1528 cmd->seid = cpu_to_le16(seid);
1529 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1530
1531 return status;
1532}
1533
1534/**
1535 * i40e_get_vsi_params - get VSI configuration info
1536 * @hw: pointer to the hw struct
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1537 * @vsi_ctx: pointer to a vsi context struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1538 * @cmd_details: pointer to command details structure or NULL
1539 **/
1540i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1541 struct i40e_vsi_context *vsi_ctx,
1542 struct i40e_asq_cmd_details *cmd_details)
1543{
1544 struct i40e_aq_desc desc;
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1545 struct i40e_aqc_add_get_update_vsi *cmd =
1546 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1547 struct i40e_aqc_add_get_update_vsi_completion *resp =
1548 (struct i40e_aqc_add_get_update_vsi_completion *)
1549 &desc.params.raw;
1550 i40e_status status;
1551
1552 i40e_fill_default_direct_cmd_desc(&desc,
1553 i40e_aqc_opc_get_vsi_parameters);
1554
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1555 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1556
1557 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1558
1559 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1560 sizeof(vsi_ctx->info), NULL);
1561
1562 if (status)
1563 goto aq_get_vsi_params_exit;
1564
1565 vsi_ctx->seid = le16_to_cpu(resp->seid);
1566 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1567 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1568 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1569
1570aq_get_vsi_params_exit:
1571 return status;
1572}
1573
1574/**
1575 * i40e_aq_update_vsi_params
1576 * @hw: pointer to the hw struct
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1577 * @vsi_ctx: pointer to a vsi context struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1578 * @cmd_details: pointer to command details structure or NULL
1579 *
1580 * Update a VSI context.
1581 **/
1582i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1583 struct i40e_vsi_context *vsi_ctx,
1584 struct i40e_asq_cmd_details *cmd_details)
1585{
1586 struct i40e_aq_desc desc;
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1587 struct i40e_aqc_add_get_update_vsi *cmd =
1588 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1589 i40e_status status;
1590
1591 i40e_fill_default_direct_cmd_desc(&desc,
1592 i40e_aqc_opc_update_vsi_parameters);
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1593 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1594
1595 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1596
1597 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1598 sizeof(vsi_ctx->info), cmd_details);
1599
1600 return status;
1601}
1602
1603/**
1604 * i40e_aq_get_switch_config
1605 * @hw: pointer to the hardware structure
1606 * @buf: pointer to the result buffer
1607 * @buf_size: length of input buffer
1608 * @start_seid: seid to start for the report, 0 == beginning
1609 * @cmd_details: pointer to command details structure or NULL
1610 *
1611 * Fill the buf with switch configuration returned from AdminQ command
1612 **/
1613i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1614 struct i40e_aqc_get_switch_config_resp *buf,
1615 u16 buf_size, u16 *start_seid,
1616 struct i40e_asq_cmd_details *cmd_details)
1617{
1618 struct i40e_aq_desc desc;
1619 struct i40e_aqc_switch_seid *scfg =
1620 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1621 i40e_status status;
1622
1623 i40e_fill_default_direct_cmd_desc(&desc,
1624 i40e_aqc_opc_get_switch_config);
1625 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1626 if (buf_size > I40E_AQ_LARGE_BUF)
1627 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1628 scfg->seid = cpu_to_le16(*start_seid);
1629
1630 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1631 *start_seid = le16_to_cpu(scfg->seid);
1632
1633 return status;
1634}
1635
1636/**
1637 * i40e_aq_get_firmware_version
1638 * @hw: pointer to the hw struct
1639 * @fw_major_version: firmware major version
1640 * @fw_minor_version: firmware minor version
1641 * @api_major_version: major queue version
1642 * @api_minor_version: minor queue version
1643 * @cmd_details: pointer to command details structure or NULL
1644 *
1645 * Get the firmware version from the admin queue commands
1646 **/
1647i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1648 u16 *fw_major_version, u16 *fw_minor_version,
1649 u16 *api_major_version, u16 *api_minor_version,
1650 struct i40e_asq_cmd_details *cmd_details)
1651{
1652 struct i40e_aq_desc desc;
1653 struct i40e_aqc_get_version *resp =
1654 (struct i40e_aqc_get_version *)&desc.params.raw;
1655 i40e_status status;
1656
1657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1658
1659 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1660
1661 if (!status) {
1662 if (fw_major_version != NULL)
1663 *fw_major_version = le16_to_cpu(resp->fw_major);
1664 if (fw_minor_version != NULL)
1665 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1666 if (api_major_version != NULL)
1667 *api_major_version = le16_to_cpu(resp->api_major);
1668 if (api_minor_version != NULL)
1669 *api_minor_version = le16_to_cpu(resp->api_minor);
1670 }
1671
1672 return status;
1673}
1674
1675/**
1676 * i40e_aq_send_driver_version
1677 * @hw: pointer to the hw struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1678 * @dv: driver's major, minor version
1679 * @cmd_details: pointer to command details structure or NULL
1680 *
1681 * Send the driver version to the firmware
1682 **/
1683i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1684 struct i40e_driver_version *dv,
1685 struct i40e_asq_cmd_details *cmd_details)
1686{
1687 struct i40e_aq_desc desc;
1688 struct i40e_aqc_driver_version *cmd =
1689 (struct i40e_aqc_driver_version *)&desc.params.raw;
1690 i40e_status status;
Kevin Scott9d2f98e2014-04-01 07:11:52 +0000[diff] [blame]1691 u16 len;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1692
1693 if (dv == NULL)
1694 return I40E_ERR_PARAM;
1695
1696 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1697
1698 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1699 cmd->driver_major_ver = dv->major_version;
1700 cmd->driver_minor_ver = dv->minor_version;
1701 cmd->driver_build_ver = dv->build_version;
1702 cmd->driver_subbuild_ver = dv->subbuild_version;
Shannon Nelsond2466012014-04-01 07:11:45 +0000[diff] [blame]1703
1704 len = 0;
1705 while (len < sizeof(dv->driver_string) &&
1706 (dv->driver_string[len] < 0x80) &&
1707 dv->driver_string[len])
1708 len++;
1709 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1710 len, cmd_details);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1711
1712 return status;
1713}
1714
1715/**
1716 * i40e_get_link_status - get status of the HW network link
1717 * @hw: pointer to the hw struct
1718 *
1719 * Returns true if link is up, false if link is down.
1720 *
1721 * Side effect: LinkStatusEvent reporting becomes enabled
1722 **/
1723bool i40e_get_link_status(struct i40e_hw *hw)
1724{
1725 i40e_status status = 0;
1726 bool link_status = false;
1727
1728 if (hw->phy.get_link_info) {
1729 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1730
1731 if (status)
1732 goto i40e_get_link_status_exit;
1733 }
1734
1735 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1736
1737i40e_get_link_status_exit:
1738 return link_status;
1739}
1740
1741/**
1742 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1743 * @hw: pointer to the hw struct
1744 * @uplink_seid: the MAC or other gizmo SEID
1745 * @downlink_seid: the VSI SEID
1746 * @enabled_tc: bitmap of TCs to be enabled
1747 * @default_port: true for default port VSI, false for control port
Kevin Scotte1c51b952013-11-20 10:02:51 +0000[diff] [blame]1748 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1749 * @veb_seid: pointer to where to put the resulting VEB SEID
1750 * @cmd_details: pointer to command details structure or NULL
1751 *
1752 * This asks the FW to add a VEB between the uplink and downlink
1753 * elements. If the uplink SEID is 0, this will be a floating VEB.
1754 **/
1755i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1756 u16 downlink_seid, u8 enabled_tc,
Kevin Scotte1c51b952013-11-20 10:02:51 +0000[diff] [blame]1757 bool default_port, bool enable_l2_filtering,
1758 u16 *veb_seid,
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1759 struct i40e_asq_cmd_details *cmd_details)
1760{
1761 struct i40e_aq_desc desc;
1762 struct i40e_aqc_add_veb *cmd =
1763 (struct i40e_aqc_add_veb *)&desc.params.raw;
1764 struct i40e_aqc_add_veb_completion *resp =
1765 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1766 i40e_status status;
1767 u16 veb_flags = 0;
1768
1769 /* SEIDs need to either both be set or both be 0 for floating VEB */
1770 if (!!uplink_seid != !!downlink_seid)
1771 return I40E_ERR_PARAM;
1772
1773 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1774
1775 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1776 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1777 cmd->enable_tcs = enabled_tc;
1778 if (!uplink_seid)
1779 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1780 if (default_port)
1781 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1782 else
1783 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
Kevin Scotte1c51b952013-11-20 10:02:51 +0000[diff] [blame]1784
1785 if (enable_l2_filtering)
1786 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1787
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1788 cmd->veb_flags = cpu_to_le16(veb_flags);
1789
1790 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1791
1792 if (!status && veb_seid)
1793 *veb_seid = le16_to_cpu(resp->veb_seid);
1794
1795 return status;
1796}
1797
1798/**
1799 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1800 * @hw: pointer to the hw struct
1801 * @veb_seid: the SEID of the VEB to query
1802 * @switch_id: the uplink switch id
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1803 * @floating: set to true if the VEB is floating
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1804 * @statistic_index: index of the stats counter block for this VEB
1805 * @vebs_used: number of VEB's used by function
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1806 * @vebs_free: total VEB's not reserved by any function
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1807 * @cmd_details: pointer to command details structure or NULL
1808 *
1809 * This retrieves the parameters for a particular VEB, specified by
1810 * uplink_seid, and returns them to the caller.
1811 **/
1812i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1813 u16 veb_seid, u16 *switch_id,
1814 bool *floating, u16 *statistic_index,
1815 u16 *vebs_used, u16 *vebs_free,
1816 struct i40e_asq_cmd_details *cmd_details)
1817{
1818 struct i40e_aq_desc desc;
1819 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1820 (struct i40e_aqc_get_veb_parameters_completion *)
1821 &desc.params.raw;
1822 i40e_status status;
1823
1824 if (veb_seid == 0)
1825 return I40E_ERR_PARAM;
1826
1827 i40e_fill_default_direct_cmd_desc(&desc,
1828 i40e_aqc_opc_get_veb_parameters);
1829 cmd_resp->seid = cpu_to_le16(veb_seid);
1830
1831 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1832 if (status)
1833 goto get_veb_exit;
1834
1835 if (switch_id)
1836 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1837 if (statistic_index)
1838 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1839 if (vebs_used)
1840 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1841 if (vebs_free)
1842 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1843 if (floating) {
1844 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1845 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1846 *floating = true;
1847 else
1848 *floating = false;
1849 }
1850
1851get_veb_exit:
1852 return status;
1853}
1854
1855/**
1856 * i40e_aq_add_macvlan
1857 * @hw: pointer to the hw struct
1858 * @seid: VSI for the mac address
1859 * @mv_list: list of macvlans to be added
1860 * @count: length of the list
1861 * @cmd_details: pointer to command details structure or NULL
1862 *
1863 * Add MAC/VLAN addresses to the HW filtering
1864 **/
1865i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1866 struct i40e_aqc_add_macvlan_element_data *mv_list,
1867 u16 count, struct i40e_asq_cmd_details *cmd_details)
1868{
1869 struct i40e_aq_desc desc;
1870 struct i40e_aqc_macvlan *cmd =
1871 (struct i40e_aqc_macvlan *)&desc.params.raw;
1872 i40e_status status;
1873 u16 buf_size;
1874
1875 if (count == 0 || !mv_list || !hw)
1876 return I40E_ERR_PARAM;
1877
1878 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1879
1880 /* prep the rest of the request */
1881 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1882 cmd->num_addresses = cpu_to_le16(count);
1883 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1884 cmd->seid[1] = 0;
1885 cmd->seid[2] = 0;
1886
1887 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1888 if (buf_size > I40E_AQ_LARGE_BUF)
1889 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1890
1891 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1892 cmd_details);
1893
1894 return status;
1895}
1896
1897/**
1898 * i40e_aq_remove_macvlan
1899 * @hw: pointer to the hw struct
1900 * @seid: VSI for the mac address
1901 * @mv_list: list of macvlans to be removed
1902 * @count: length of the list
1903 * @cmd_details: pointer to command details structure or NULL
1904 *
1905 * Remove MAC/VLAN addresses from the HW filtering
1906 **/
1907i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1908 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1909 u16 count, struct i40e_asq_cmd_details *cmd_details)
1910{
1911 struct i40e_aq_desc desc;
1912 struct i40e_aqc_macvlan *cmd =
1913 (struct i40e_aqc_macvlan *)&desc.params.raw;
1914 i40e_status status;
1915 u16 buf_size;
1916
1917 if (count == 0 || !mv_list || !hw)
1918 return I40E_ERR_PARAM;
1919
1920 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1921
1922 /* prep the rest of the request */
1923 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1924 cmd->num_addresses = cpu_to_le16(count);
1925 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1926 cmd->seid[1] = 0;
1927 cmd->seid[2] = 0;
1928
1929 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1930 if (buf_size > I40E_AQ_LARGE_BUF)
1931 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1932
1933 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1934 cmd_details);
1935
1936 return status;
1937}
1938
1939/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1940 * i40e_aq_send_msg_to_vf
1941 * @hw: pointer to the hardware structure
1942 * @vfid: vf id to send msg
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1943 * @v_opcode: opcodes for VF-PF communication
1944 * @v_retval: return error code
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1945 * @msg: pointer to the msg buffer
1946 * @msglen: msg length
1947 * @cmd_details: pointer to command details
1948 *
1949 * send msg to vf
1950 **/
1951i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1952 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1953 struct i40e_asq_cmd_details *cmd_details)
1954{
1955 struct i40e_aq_desc desc;
1956 struct i40e_aqc_pf_vf_message *cmd =
1957 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1958 i40e_status status;
1959
1960 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1961 cmd->id = cpu_to_le32(vfid);
1962 desc.cookie_high = cpu_to_le32(v_opcode);
1963 desc.cookie_low = cpu_to_le32(v_retval);
1964 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1965 if (msglen) {
1966 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1967 I40E_AQ_FLAG_RD));
1968 if (msglen > I40E_AQ_LARGE_BUF)
1969 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1970 desc.datalen = cpu_to_le16(msglen);
1971 }
1972 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1973
1974 return status;
1975}
1976
1977/**
1978 * i40e_aq_set_hmc_resource_profile
1979 * @hw: pointer to the hw struct
1980 * @profile: type of profile the HMC is to be set as
1981 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1982 * @cmd_details: pointer to command details structure or NULL
1983 *
1984 * set the HMC profile of the device.
1985 **/
1986i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1987 enum i40e_aq_hmc_profile profile,
1988 u8 pe_vf_enabled_count,
1989 struct i40e_asq_cmd_details *cmd_details)
1990{
1991 struct i40e_aq_desc desc;
1992 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1993 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1994 i40e_status status;
1995
1996 i40e_fill_default_direct_cmd_desc(&desc,
1997 i40e_aqc_opc_set_hmc_resource_profile);
1998
1999 cmd->pm_profile = (u8)profile;
2000 cmd->pe_vf_enabled = pe_vf_enabled_count;
2001
2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003
2004 return status;
2005}
2006
2007/**
2008 * i40e_aq_request_resource
2009 * @hw: pointer to the hw struct
2010 * @resource: resource id
2011 * @access: access type
2012 * @sdp_number: resource number
2013 * @timeout: the maximum time in ms that the driver may hold the resource
2014 * @cmd_details: pointer to command details structure or NULL
2015 *
2016 * requests common resource using the admin queue commands
2017 **/
2018i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2019 enum i40e_aq_resources_ids resource,
2020 enum i40e_aq_resource_access_type access,
2021 u8 sdp_number, u64 *timeout,
2022 struct i40e_asq_cmd_details *cmd_details)
2023{
2024 struct i40e_aq_desc desc;
2025 struct i40e_aqc_request_resource *cmd_resp =
2026 (struct i40e_aqc_request_resource *)&desc.params.raw;
2027 i40e_status status;
2028
2029 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2030
2031 cmd_resp->resource_id = cpu_to_le16(resource);
2032 cmd_resp->access_type = cpu_to_le16(access);
2033 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2034
2035 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2036 /* The completion specifies the maximum time in ms that the driver
2037 * may hold the resource in the Timeout field.
2038 * If the resource is held by someone else, the command completes with
2039 * busy return value and the timeout field indicates the maximum time
2040 * the current owner of the resource has to free it.
2041 */
2042 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2043 *timeout = le32_to_cpu(cmd_resp->timeout);
2044
2045 return status;
2046}
2047
2048/**
2049 * i40e_aq_release_resource
2050 * @hw: pointer to the hw struct
2051 * @resource: resource id
2052 * @sdp_number: resource number
2053 * @cmd_details: pointer to command details structure or NULL
2054 *
2055 * release common resource using the admin queue commands
2056 **/
2057i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2058 enum i40e_aq_resources_ids resource,
2059 u8 sdp_number,
2060 struct i40e_asq_cmd_details *cmd_details)
2061{
2062 struct i40e_aq_desc desc;
2063 struct i40e_aqc_request_resource *cmd =
2064 (struct i40e_aqc_request_resource *)&desc.params.raw;
2065 i40e_status status;
2066
2067 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2068
2069 cmd->resource_id = cpu_to_le16(resource);
2070 cmd->resource_number = cpu_to_le32(sdp_number);
2071
2072 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2073
2074 return status;
2075}
2076
2077/**
2078 * i40e_aq_read_nvm
2079 * @hw: pointer to the hw struct
2080 * @module_pointer: module pointer location in words from the NVM beginning
2081 * @offset: byte offset from the module beginning
2082 * @length: length of the section to be read (in bytes from the offset)
2083 * @data: command buffer (size [bytes] = length)
2084 * @last_command: tells if this is the last command in a series
2085 * @cmd_details: pointer to command details structure or NULL
2086 *
2087 * Read the NVM using the admin queue commands
2088 **/
2089i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2090 u32 offset, u16 length, void *data,
2091 bool last_command,
2092 struct i40e_asq_cmd_details *cmd_details)
2093{
2094 struct i40e_aq_desc desc;
2095 struct i40e_aqc_nvm_update *cmd =
2096 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2097 i40e_status status;
2098
2099 /* In offset the highest byte must be zeroed. */
2100 if (offset & 0xFF000000) {
2101 status = I40E_ERR_PARAM;
2102 goto i40e_aq_read_nvm_exit;
2103 }
2104
2105 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2106
2107 /* If this is the last command in a series, set the proper flag. */
2108 if (last_command)
2109 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2110 cmd->module_pointer = module_pointer;
2111 cmd->offset = cpu_to_le32(offset);
2112 cmd->length = cpu_to_le16(length);
2113
2114 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2115 if (length > I40E_AQ_LARGE_BUF)
2116 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2117
2118 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2119
2120i40e_aq_read_nvm_exit:
2121 return status;
2122}
2123
2124#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2125#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2126#define I40E_DEV_FUNC_CAP_NPAR 0x03
2127#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2128#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2129#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2130#define I40E_DEV_FUNC_CAP_VF 0x13
2131#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2132#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2133#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2134#define I40E_DEV_FUNC_CAP_VSI 0x17
2135#define I40E_DEV_FUNC_CAP_DCB 0x18
2136#define I40E_DEV_FUNC_CAP_FCOE 0x21
2137#define I40E_DEV_FUNC_CAP_RSS 0x40
2138#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2139#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2140#define I40E_DEV_FUNC_CAP_MSIX 0x43
2141#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2142#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2143#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2144#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2145#define I40E_DEV_FUNC_CAP_CEM 0xF2
2146#define I40E_DEV_FUNC_CAP_IWARP 0x51
2147#define I40E_DEV_FUNC_CAP_LED 0x61
2148#define I40E_DEV_FUNC_CAP_SDP 0x62
2149#define I40E_DEV_FUNC_CAP_MDIO 0x63
2150
2151/**
2152 * i40e_parse_discover_capabilities
2153 * @hw: pointer to the hw struct
2154 * @buff: pointer to a buffer containing device/function capability records
2155 * @cap_count: number of capability records in the list
2156 * @list_type_opc: type of capabilities list to parse
2157 *
2158 * Parse the device/function capabilities list.
2159 **/
2160static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2161 u32 cap_count,
2162 enum i40e_admin_queue_opc list_type_opc)
2163{
2164 struct i40e_aqc_list_capabilities_element_resp *cap;
2165 u32 number, logical_id, phys_id;
2166 struct i40e_hw_capabilities *p;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2167 u32 i = 0;
2168 u16 id;
2169
2170 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2171
2172 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
Joe Perchesb58f2f72014-03-25 04:30:32 +0000[diff] [blame]2173 p = &hw->dev_caps;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2174 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
Joe Perchesb58f2f72014-03-25 04:30:32 +0000[diff] [blame]2175 p = &hw->func_caps;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2176 else
2177 return;
2178
2179 for (i = 0; i < cap_count; i++, cap++) {
2180 id = le16_to_cpu(cap->id);
2181 number = le32_to_cpu(cap->number);
2182 logical_id = le32_to_cpu(cap->logical_id);
2183 phys_id = le32_to_cpu(cap->phys_id);
2184
2185 switch (id) {
2186 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2187 p->switch_mode = number;
2188 break;
2189 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2190 p->management_mode = number;
2191 break;
2192 case I40E_DEV_FUNC_CAP_NPAR:
2193 p->npar_enable = number;
2194 break;
2195 case I40E_DEV_FUNC_CAP_OS2BMC:
2196 p->os2bmc = number;
2197 break;
2198 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2199 p->valid_functions = number;
2200 break;
2201 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2202 if (number == 1)
2203 p->sr_iov_1_1 = true;
2204 break;
2205 case I40E_DEV_FUNC_CAP_VF:
2206 p->num_vfs = number;
2207 p->vf_base_id = logical_id;
2208 break;
2209 case I40E_DEV_FUNC_CAP_VMDQ:
2210 if (number == 1)
2211 p->vmdq = true;
2212 break;
2213 case I40E_DEV_FUNC_CAP_802_1_QBG:
2214 if (number == 1)
2215 p->evb_802_1_qbg = true;
2216 break;
2217 case I40E_DEV_FUNC_CAP_802_1_QBH:
2218 if (number == 1)
2219 p->evb_802_1_qbh = true;
2220 break;
2221 case I40E_DEV_FUNC_CAP_VSI:
2222 p->num_vsis = number;
2223 break;
2224 case I40E_DEV_FUNC_CAP_DCB:
2225 if (number == 1) {
2226 p->dcb = true;
2227 p->enabled_tcmap = logical_id;
2228 p->maxtc = phys_id;
2229 }
2230 break;
2231 case I40E_DEV_FUNC_CAP_FCOE:
2232 if (number == 1)
2233 p->fcoe = true;
2234 break;
2235 case I40E_DEV_FUNC_CAP_RSS:
2236 p->rss = true;
Carolyn Wybornye157ea32014-06-03 23:50:22 +0000[diff] [blame]2237 p->rss_table_size = number;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2238 p->rss_table_entry_width = logical_id;
2239 break;
2240 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2241 p->num_rx_qp = number;
2242 p->base_queue = phys_id;
2243 break;
2244 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2245 p->num_tx_qp = number;
2246 p->base_queue = phys_id;
2247 break;
2248 case I40E_DEV_FUNC_CAP_MSIX:
2249 p->num_msix_vectors = number;
2250 break;
2251 case I40E_DEV_FUNC_CAP_MSIX_VF:
2252 p->num_msix_vectors_vf = number;
2253 break;
2254 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2255 if (number == 1)
2256 p->mfp_mode_1 = true;
2257 break;
2258 case I40E_DEV_FUNC_CAP_CEM:
2259 if (number == 1)
2260 p->mgmt_cem = true;
2261 break;
2262 case I40E_DEV_FUNC_CAP_IWARP:
2263 if (number == 1)
2264 p->iwarp = true;
2265 break;
2266 case I40E_DEV_FUNC_CAP_LED:
2267 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2268 p->led[phys_id] = true;
2269 break;
2270 case I40E_DEV_FUNC_CAP_SDP:
2271 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2272 p->sdp[phys_id] = true;
2273 break;
2274 case I40E_DEV_FUNC_CAP_MDIO:
2275 if (number == 1) {
2276 p->mdio_port_num = phys_id;
2277 p->mdio_port_mode = logical_id;
2278 }
2279 break;
2280 case I40E_DEV_FUNC_CAP_IEEE_1588:
2281 if (number == 1)
2282 p->ieee_1588 = true;
2283 break;
2284 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2285 p->fd = true;
2286 p->fd_filters_guaranteed = number;
2287 p->fd_filters_best_effort = logical_id;
2288 break;
2289 default:
2290 break;
2291 }
2292 }
2293
Vasu Dev566bb852014-04-09 05:59:06 +0000[diff] [blame]2294 /* Software override ensuring FCoE is disabled if npar or mfp
2295 * mode because it is not supported in these modes.
2296 */
2297 if (p->npar_enable || p->mfp_mode_1)
2298 p->fcoe = false;
2299
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2300 /* additional HW specific goodies that might
2301 * someday be HW version specific
2302 */
2303 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2304}
2305
2306/**
2307 * i40e_aq_discover_capabilities
2308 * @hw: pointer to the hw struct
2309 * @buff: a virtual buffer to hold the capabilities
2310 * @buff_size: Size of the virtual buffer
2311 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2312 * @list_type_opc: capabilities type to discover - pass in the command opcode
2313 * @cmd_details: pointer to command details structure or NULL
2314 *
2315 * Get the device capabilities descriptions from the firmware
2316 **/
2317i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2318 void *buff, u16 buff_size, u16 *data_size,
2319 enum i40e_admin_queue_opc list_type_opc,
2320 struct i40e_asq_cmd_details *cmd_details)
2321{
2322 struct i40e_aqc_list_capabilites *cmd;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2323 struct i40e_aq_desc desc;
Jesse Brandeburg8fb905b2014-01-17 15:36:33 -0800[diff] [blame]2324 i40e_status status = 0;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2325
2326 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2327
2328 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2329 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2330 status = I40E_ERR_PARAM;
2331 goto exit;
2332 }
2333
2334 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2335
2336 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2337 if (buff_size > I40E_AQ_LARGE_BUF)
2338 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2339
2340 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2341 *data_size = le16_to_cpu(desc.datalen);
2342
2343 if (status)
2344 goto exit;
2345
2346 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2347 list_type_opc);
2348
2349exit:
2350 return status;
2351}
2352
2353/**
2354 * i40e_aq_get_lldp_mib
2355 * @hw: pointer to the hw struct
2356 * @bridge_type: type of bridge requested
2357 * @mib_type: Local, Remote or both Local and Remote MIBs
2358 * @buff: pointer to a user supplied buffer to store the MIB block
2359 * @buff_size: size of the buffer (in bytes)
2360 * @local_len : length of the returned Local LLDP MIB
2361 * @remote_len: length of the returned Remote LLDP MIB
2362 * @cmd_details: pointer to command details structure or NULL
2363 *
2364 * Requests the complete LLDP MIB (entire packet).
2365 **/
2366i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2367 u8 mib_type, void *buff, u16 buff_size,
2368 u16 *local_len, u16 *remote_len,
2369 struct i40e_asq_cmd_details *cmd_details)
2370{
2371 struct i40e_aq_desc desc;
2372 struct i40e_aqc_lldp_get_mib *cmd =
2373 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2374 struct i40e_aqc_lldp_get_mib *resp =
2375 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2376 i40e_status status;
2377
2378 if (buff_size == 0 || !buff)
2379 return I40E_ERR_PARAM;
2380
2381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2382 /* Indirect Command */
2383 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2384
2385 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2386 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2387 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2388
2389 desc.datalen = cpu_to_le16(buff_size);
2390
2391 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2392 if (buff_size > I40E_AQ_LARGE_BUF)
2393 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2394
2395 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2396 if (!status) {
2397 if (local_len != NULL)
2398 *local_len = le16_to_cpu(resp->local_len);
2399 if (remote_len != NULL)
2400 *remote_len = le16_to_cpu(resp->remote_len);
2401 }
2402
2403 return status;
2404}
2405
2406/**
2407 * i40e_aq_cfg_lldp_mib_change_event
2408 * @hw: pointer to the hw struct
2409 * @enable_update: Enable or Disable event posting
2410 * @cmd_details: pointer to command details structure or NULL
2411 *
2412 * Enable or Disable posting of an event on ARQ when LLDP MIB
2413 * associated with the interface changes
2414 **/
2415i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2416 bool enable_update,
2417 struct i40e_asq_cmd_details *cmd_details)
2418{
2419 struct i40e_aq_desc desc;
2420 struct i40e_aqc_lldp_update_mib *cmd =
2421 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2422 i40e_status status;
2423
2424 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2425
2426 if (!enable_update)
2427 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2428
2429 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2430
2431 return status;
2432}
2433
2434/**
2435 * i40e_aq_stop_lldp
2436 * @hw: pointer to the hw struct
2437 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2438 * @cmd_details: pointer to command details structure or NULL
2439 *
2440 * Stop or Shutdown the embedded LLDP Agent
2441 **/
2442i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2443 struct i40e_asq_cmd_details *cmd_details)
2444{
2445 struct i40e_aq_desc desc;
2446 struct i40e_aqc_lldp_stop *cmd =
2447 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2448 i40e_status status;
2449
2450 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2451
2452 if (shutdown_agent)
2453 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2454
2455 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456
2457 return status;
2458}
2459
2460/**
2461 * i40e_aq_start_lldp
2462 * @hw: pointer to the hw struct
2463 * @cmd_details: pointer to command details structure or NULL
2464 *
2465 * Start the embedded LLDP Agent on all ports.
2466 **/
2467i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2468 struct i40e_asq_cmd_details *cmd_details)
2469{
2470 struct i40e_aq_desc desc;
2471 struct i40e_aqc_lldp_start *cmd =
2472 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2473 i40e_status status;
2474
2475 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2476
2477 cmd->command = I40E_AQ_LLDP_AGENT_START;
2478
2479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2480
2481 return status;
2482}
2483
2484/**
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2485 * i40e_aq_add_udp_tunnel
2486 * @hw: pointer to the hw struct
2487 * @udp_port: the UDP port to add
2488 * @header_len: length of the tunneling header length in DWords
2489 * @protocol_index: protocol index type
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]2490 * @filter_index: pointer to filter index
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2491 * @cmd_details: pointer to command details structure or NULL
2492 **/
2493i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
Kevin Scottf4f94b92014-04-05 07:46:10 +0000[diff] [blame]2494 u16 udp_port, u8 protocol_index,
2495 u8 *filter_index,
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2496 struct i40e_asq_cmd_details *cmd_details)
2497{
2498 struct i40e_aq_desc desc;
2499 struct i40e_aqc_add_udp_tunnel *cmd =
2500 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2501 struct i40e_aqc_del_udp_tunnel_completion *resp =
2502 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2503 i40e_status status;
2504
2505 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2506
2507 cmd->udp_port = cpu_to_le16(udp_port);
Shannon Nelson981b7542013-12-11 08:17:11 +0000[diff] [blame]2508 cmd->protocol_type = protocol_index;
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2509
2510 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2511
2512 if (!status)
2513 *filter_index = resp->index;
2514
2515 return status;
2516}
2517
2518/**
2519 * i40e_aq_del_udp_tunnel
2520 * @hw: pointer to the hw struct
2521 * @index: filter index
2522 * @cmd_details: pointer to command details structure or NULL
2523 **/
2524i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2525 struct i40e_asq_cmd_details *cmd_details)
2526{
2527 struct i40e_aq_desc desc;
2528 struct i40e_aqc_remove_udp_tunnel *cmd =
2529 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2530 i40e_status status;
2531
2532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2533
2534 cmd->index = index;
2535
2536 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2537
2538 return status;
2539}
2540
2541/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2542 * i40e_aq_delete_element - Delete switch element
2543 * @hw: pointer to the hw struct
2544 * @seid: the SEID to delete from the switch
2545 * @cmd_details: pointer to command details structure or NULL
2546 *
2547 * This deletes a switch element from the switch.
2548 **/
2549i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2550 struct i40e_asq_cmd_details *cmd_details)
2551{
2552 struct i40e_aq_desc desc;
2553 struct i40e_aqc_switch_seid *cmd =
2554 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2555 i40e_status status;
2556
2557 if (seid == 0)
2558 return I40E_ERR_PARAM;
2559
2560 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2561
2562 cmd->seid = cpu_to_le16(seid);
2563
2564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2565
2566 return status;
2567}
2568
2569/**
Neerav Parikhafb3ff02014-01-17 15:36:36 -0800[diff] [blame]2570 * i40e_aq_dcb_updated - DCB Updated Command
2571 * @hw: pointer to the hw struct
2572 * @cmd_details: pointer to command details structure or NULL
2573 *
2574 * EMP will return when the shared RPB settings have been
2575 * recomputed and modified. The retval field in the descriptor
2576 * will be set to 0 when RPB is modified.
2577 **/
2578i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2579 struct i40e_asq_cmd_details *cmd_details)
2580{
2581 struct i40e_aq_desc desc;
2582 i40e_status status;
2583
2584 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2585
2586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2587
2588 return status;
2589}
2590
2591/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2592 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2593 * @hw: pointer to the hw struct
2594 * @seid: seid for the physical port/switching component/vsi
2595 * @buff: Indirect buffer to hold data parameters and response
2596 * @buff_size: Indirect buffer size
2597 * @opcode: Tx scheduler AQ command opcode
2598 * @cmd_details: pointer to command details structure or NULL
2599 *
2600 * Generic command handler for Tx scheduler AQ commands
2601 **/
2602static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2603 void *buff, u16 buff_size,
2604 enum i40e_admin_queue_opc opcode,
2605 struct i40e_asq_cmd_details *cmd_details)
2606{
2607 struct i40e_aq_desc desc;
2608 struct i40e_aqc_tx_sched_ind *cmd =
2609 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2610 i40e_status status;
2611 bool cmd_param_flag = false;
2612
2613 switch (opcode) {
2614 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2615 case i40e_aqc_opc_configure_vsi_tc_bw:
2616 case i40e_aqc_opc_enable_switching_comp_ets:
2617 case i40e_aqc_opc_modify_switching_comp_ets:
2618 case i40e_aqc_opc_disable_switching_comp_ets:
2619 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2620 case i40e_aqc_opc_configure_switching_comp_bw_config:
2621 cmd_param_flag = true;
2622 break;
2623 case i40e_aqc_opc_query_vsi_bw_config:
2624 case i40e_aqc_opc_query_vsi_ets_sla_config:
2625 case i40e_aqc_opc_query_switching_comp_ets_config:
2626 case i40e_aqc_opc_query_port_ets_config:
2627 case i40e_aqc_opc_query_switching_comp_bw_config:
2628 cmd_param_flag = false;
2629 break;
2630 default:
2631 return I40E_ERR_PARAM;
2632 }
2633
2634 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2635
2636 /* Indirect command */
2637 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2638 if (cmd_param_flag)
2639 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2640 if (buff_size > I40E_AQ_LARGE_BUF)
2641 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2642
2643 desc.datalen = cpu_to_le16(buff_size);
2644
2645 cmd->vsi_seid = cpu_to_le16(seid);
2646
2647 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2648
2649 return status;
2650}
2651
2652/**
Mitch Williams6b192892014-03-06 09:02:29 +0000[diff] [blame]2653 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2654 * @hw: pointer to the hw struct
2655 * @seid: VSI seid
2656 * @credit: BW limit credits (0 = disabled)
2657 * @max_credit: Max BW limit credits
2658 * @cmd_details: pointer to command details structure or NULL
2659 **/
2660i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2661 u16 seid, u16 credit, u8 max_credit,
2662 struct i40e_asq_cmd_details *cmd_details)
2663{
2664 struct i40e_aq_desc desc;
2665 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2666 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2667 i40e_status status;
2668
2669 i40e_fill_default_direct_cmd_desc(&desc,
2670 i40e_aqc_opc_configure_vsi_bw_limit);
2671
2672 cmd->vsi_seid = cpu_to_le16(seid);
2673 cmd->credit = cpu_to_le16(credit);
2674 cmd->max_credit = max_credit;
2675
2676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2677
2678 return status;
2679}
2680
2681/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2682 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2683 * @hw: pointer to the hw struct
2684 * @seid: VSI seid
2685 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2686 * @cmd_details: pointer to command details structure or NULL
2687 **/
2688i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2689 u16 seid,
2690 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2691 struct i40e_asq_cmd_details *cmd_details)
2692{
2693 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2694 i40e_aqc_opc_configure_vsi_tc_bw,
2695 cmd_details);
2696}
2697
2698/**
Neerav Parikhafb3ff02014-01-17 15:36:36 -0800[diff] [blame]2699 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2700 * @hw: pointer to the hw struct
2701 * @seid: seid of the switching component connected to Physical Port
2702 * @ets_data: Buffer holding ETS parameters
2703 * @cmd_details: pointer to command details structure or NULL
2704 **/
2705i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2706 u16 seid,
2707 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2708 enum i40e_admin_queue_opc opcode,
2709 struct i40e_asq_cmd_details *cmd_details)
2710{
2711 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2712 sizeof(*ets_data), opcode, cmd_details);
2713}
2714
2715/**
2716 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2717 * @hw: pointer to the hw struct
2718 * @seid: seid of the switching component
2719 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2720 * @cmd_details: pointer to command details structure or NULL
2721 **/
2722i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2723 u16 seid,
2724 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2725 struct i40e_asq_cmd_details *cmd_details)
2726{
2727 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2728 i40e_aqc_opc_configure_switching_comp_bw_config,
2729 cmd_details);
2730}
2731
2732/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2733 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2734 * @hw: pointer to the hw struct
2735 * @seid: seid of the VSI
2736 * @bw_data: Buffer to hold VSI BW configuration
2737 * @cmd_details: pointer to command details structure or NULL
2738 **/
2739i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2740 u16 seid,
2741 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2742 struct i40e_asq_cmd_details *cmd_details)
2743{
2744 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2745 i40e_aqc_opc_query_vsi_bw_config,
2746 cmd_details);
2747}
2748
2749/**
2750 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2751 * @hw: pointer to the hw struct
2752 * @seid: seid of the VSI
2753 * @bw_data: Buffer to hold VSI BW configuration per TC
2754 * @cmd_details: pointer to command details structure or NULL
2755 **/
2756i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2757 u16 seid,
2758 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2759 struct i40e_asq_cmd_details *cmd_details)
2760{
2761 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2762 i40e_aqc_opc_query_vsi_ets_sla_config,
2763 cmd_details);
2764}
2765
2766/**
2767 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2768 * @hw: pointer to the hw struct
2769 * @seid: seid of the switching component
2770 * @bw_data: Buffer to hold switching component's per TC BW config
2771 * @cmd_details: pointer to command details structure or NULL
2772 **/
2773i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2774 u16 seid,
2775 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2776 struct i40e_asq_cmd_details *cmd_details)
2777{
2778 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2779 i40e_aqc_opc_query_switching_comp_ets_config,
2780 cmd_details);
2781}
2782
2783/**
2784 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2785 * @hw: pointer to the hw struct
2786 * @seid: seid of the VSI or switching component connected to Physical Port
2787 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2788 * @cmd_details: pointer to command details structure or NULL
2789 **/
2790i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2791 u16 seid,
2792 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2793 struct i40e_asq_cmd_details *cmd_details)
2794{
2795 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2796 i40e_aqc_opc_query_port_ets_config,
2797 cmd_details);
2798}
2799
2800/**
2801 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2802 * @hw: pointer to the hw struct
2803 * @seid: seid of the switching component
2804 * @bw_data: Buffer to hold switching component's BW configuration
2805 * @cmd_details: pointer to command details structure or NULL
2806 **/
2807i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2808 u16 seid,
2809 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2810 struct i40e_asq_cmd_details *cmd_details)
2811{
2812 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2813 i40e_aqc_opc_query_switching_comp_bw_config,
2814 cmd_details);
2815}
2816
2817/**
2818 * i40e_validate_filter_settings
2819 * @hw: pointer to the hardware structure
2820 * @settings: Filter control settings
2821 *
2822 * Check and validate the filter control settings passed.
2823 * The function checks for the valid filter/context sizes being
2824 * passed for FCoE and PE.
2825 *
2826 * Returns 0 if the values passed are valid and within
2827 * range else returns an error.
2828 **/
2829static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2830 struct i40e_filter_control_settings *settings)
2831{
2832 u32 fcoe_cntx_size, fcoe_filt_size;
2833 u32 pe_cntx_size, pe_filt_size;
Anjali Singhai Jain467d7292014-05-10 04:49:02 +0000[diff] [blame]2834 u32 fcoe_fmax;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2835 u32 val;
2836
2837 /* Validate FCoE settings passed */
2838 switch (settings->fcoe_filt_num) {
2839 case I40E_HASH_FILTER_SIZE_1K:
2840 case I40E_HASH_FILTER_SIZE_2K:
2841 case I40E_HASH_FILTER_SIZE_4K:
2842 case I40E_HASH_FILTER_SIZE_8K:
2843 case I40E_HASH_FILTER_SIZE_16K:
2844 case I40E_HASH_FILTER_SIZE_32K:
2845 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2846 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2847 break;
2848 default:
2849 return I40E_ERR_PARAM;
2850 }
2851
2852 switch (settings->fcoe_cntx_num) {
2853 case I40E_DMA_CNTX_SIZE_512:
2854 case I40E_DMA_CNTX_SIZE_1K:
2855 case I40E_DMA_CNTX_SIZE_2K:
2856 case I40E_DMA_CNTX_SIZE_4K:
2857 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2858 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2859 break;
2860 default:
2861 return I40E_ERR_PARAM;
2862 }
2863
2864 /* Validate PE settings passed */
2865 switch (settings->pe_filt_num) {
2866 case I40E_HASH_FILTER_SIZE_1K:
2867 case I40E_HASH_FILTER_SIZE_2K:
2868 case I40E_HASH_FILTER_SIZE_4K:
2869 case I40E_HASH_FILTER_SIZE_8K:
2870 case I40E_HASH_FILTER_SIZE_16K:
2871 case I40E_HASH_FILTER_SIZE_32K:
2872 case I40E_HASH_FILTER_SIZE_64K:
2873 case I40E_HASH_FILTER_SIZE_128K:
2874 case I40E_HASH_FILTER_SIZE_256K:
2875 case I40E_HASH_FILTER_SIZE_512K:
2876 case I40E_HASH_FILTER_SIZE_1M:
2877 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2878 pe_filt_size <<= (u32)settings->pe_filt_num;
2879 break;
2880 default:
2881 return I40E_ERR_PARAM;
2882 }
2883
2884 switch (settings->pe_cntx_num) {
2885 case I40E_DMA_CNTX_SIZE_512:
2886 case I40E_DMA_CNTX_SIZE_1K:
2887 case I40E_DMA_CNTX_SIZE_2K:
2888 case I40E_DMA_CNTX_SIZE_4K:
2889 case I40E_DMA_CNTX_SIZE_8K:
2890 case I40E_DMA_CNTX_SIZE_16K:
2891 case I40E_DMA_CNTX_SIZE_32K:
2892 case I40E_DMA_CNTX_SIZE_64K:
2893 case I40E_DMA_CNTX_SIZE_128K:
2894 case I40E_DMA_CNTX_SIZE_256K:
2895 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2896 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2897 break;
2898 default:
2899 return I40E_ERR_PARAM;
2900 }
2901
2902 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2903 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2904 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2905 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2906 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2907 return I40E_ERR_INVALID_SIZE;
2908
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2909 return 0;
2910}
2911
2912/**
2913 * i40e_set_filter_control
2914 * @hw: pointer to the hardware structure
2915 * @settings: Filter control settings
2916 *
2917 * Set the Queue Filters for PE/FCoE and enable filters required
2918 * for a single PF. It is expected that these settings are programmed
2919 * at the driver initialization time.
2920 **/
2921i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2922 struct i40e_filter_control_settings *settings)
2923{
2924 i40e_status ret = 0;
2925 u32 hash_lut_size = 0;
2926 u32 val;
2927
2928 if (!settings)
2929 return I40E_ERR_PARAM;
2930
2931 /* Validate the input settings */
2932 ret = i40e_validate_filter_settings(hw, settings);
2933 if (ret)
2934 return ret;
2935
2936 /* Read the PF Queue Filter control register */
2937 val = rd32(hw, I40E_PFQF_CTL_0);
2938
2939 /* Program required PE hash buckets for the PF */
2940 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2941 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2942 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2943 /* Program required PE contexts for the PF */
2944 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2945 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2946 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2947
2948 /* Program required FCoE hash buckets for the PF */
2949 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2950 val |= ((u32)settings->fcoe_filt_num <<
2951 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2952 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2953 /* Program required FCoE DDP contexts for the PF */
2954 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2955 val |= ((u32)settings->fcoe_cntx_num <<
2956 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2957 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2958
2959 /* Program Hash LUT size for the PF */
2960 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2961 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2962 hash_lut_size = 1;
2963 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2964 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2965
2966 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2967 if (settings->enable_fdir)
2968 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2969 if (settings->enable_ethtype)
2970 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2971 if (settings->enable_macvlan)
2972 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2973
2974 wr32(hw, I40E_PFQF_CTL_0, val);
2975
2976 return 0;
2977}
Neerav Parikhafb3ff02014-01-17 15:36:36 -0800[diff] [blame]2978
2979/**
2980 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2981 * @hw: pointer to the hw struct
2982 * @mac_addr: MAC address to use in the filter
2983 * @ethtype: Ethertype to use in the filter
2984 * @flags: Flags that needs to be applied to the filter
2985 * @vsi_seid: seid of the control VSI
2986 * @queue: VSI queue number to send the packet to
2987 * @is_add: Add control packet filter if True else remove
2988 * @stats: Structure to hold information on control filter counts
2989 * @cmd_details: pointer to command details structure or NULL
2990 *
2991 * This command will Add or Remove control packet filter for a control VSI.
2992 * In return it will update the total number of perfect filter count in
2993 * the stats member.
2994 **/
2995i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2996 u8 *mac_addr, u16 ethtype, u16 flags,
2997 u16 vsi_seid, u16 queue, bool is_add,
2998 struct i40e_control_filter_stats *stats,
2999 struct i40e_asq_cmd_details *cmd_details)
3000{
3001 struct i40e_aq_desc desc;
3002 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3003 (struct i40e_aqc_add_remove_control_packet_filter *)
3004 &desc.params.raw;
3005 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3006 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3007 &desc.params.raw;
3008 i40e_status status;
3009
3010 if (vsi_seid == 0)
3011 return I40E_ERR_PARAM;
3012
3013 if (is_add) {
3014 i40e_fill_default_direct_cmd_desc(&desc,
3015 i40e_aqc_opc_add_control_packet_filter);
3016 cmd->queue = cpu_to_le16(queue);
3017 } else {
3018 i40e_fill_default_direct_cmd_desc(&desc,
3019 i40e_aqc_opc_remove_control_packet_filter);
3020 }
3021
3022 if (mac_addr)
3023 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3024
3025 cmd->etype = cpu_to_le16(ethtype);
3026 cmd->flags = cpu_to_le16(flags);
3027 cmd->seid = cpu_to_le16(vsi_seid);
3028
3029 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3030
3031 if (!status && stats) {
3032 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3033 stats->etype_used = le16_to_cpu(resp->etype_used);
3034 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3035 stats->etype_free = le16_to_cpu(resp->etype_free);
3036 }
3037
3038 return status;
3039}
3040
Catherine Sullivand4dfb812013-11-28 06:39:21 +0000[diff] [blame]3041/**
3042 * i40e_set_pci_config_data - store PCI bus info
3043 * @hw: pointer to hardware structure
3044 * @link_status: the link status word from PCI config space
3045 *
3046 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3047 **/
3048void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3049{
3050 hw->bus.type = i40e_bus_type_pci_express;
3051
3052 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3053 case PCI_EXP_LNKSTA_NLW_X1:
3054 hw->bus.width = i40e_bus_width_pcie_x1;
3055 break;
3056 case PCI_EXP_LNKSTA_NLW_X2:
3057 hw->bus.width = i40e_bus_width_pcie_x2;
3058 break;
3059 case PCI_EXP_LNKSTA_NLW_X4:
3060 hw->bus.width = i40e_bus_width_pcie_x4;
3061 break;
3062 case PCI_EXP_LNKSTA_NLW_X8:
3063 hw->bus.width = i40e_bus_width_pcie_x8;
3064 break;
3065 default:
3066 hw->bus.width = i40e_bus_width_unknown;
3067 break;
3068 }
3069
3070 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3071 case PCI_EXP_LNKSTA_CLS_2_5GB:
3072 hw->bus.speed = i40e_bus_speed_2500;
3073 break;
3074 case PCI_EXP_LNKSTA_CLS_5_0GB:
3075 hw->bus.speed = i40e_bus_speed_5000;
3076 break;
3077 case PCI_EXP_LNKSTA_CLS_8_0GB:
3078 hw->bus.speed = i40e_bus_speed_8000;
3079 break;
3080 default:
3081 hw->bus.speed = i40e_bus_speed_unknown;
3082 break;
3083 }
3084}