blob: 9b94a8cdf9bd4141b367fc5f9fa6237eb02c2f1a [file] [log] [blame]
Jeeja KPd8c2dab2015-07-09 15:20:09 +05301/*
2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 */
23
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/pm_runtime.h>
27#include <linux/platform_device.h>
28#include <sound/pcm.h>
29#include "skl.h"
30
31/*
32 * initialize the PCI registers
33 */
34static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
35 unsigned char mask, unsigned char val)
36{
37 unsigned char data;
38
39 pci_read_config_byte(pci, reg, &data);
40 data &= ~mask;
41 data |= (val & mask);
42 pci_write_config_byte(pci, reg, data);
43}
44
45static void skl_init_pci(struct skl *skl)
46{
47 struct hdac_ext_bus *ebus = &skl->ebus;
48
49 /*
50 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
51 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
52 * Ensuring these bits are 0 clears playback static on some HD Audio
53 * codecs.
54 * The PCI register TCSEL is defined in the Intel manuals.
55 */
56 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
57 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
58}
59
60/* called from IRQ */
61static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
62{
63 snd_pcm_period_elapsed(hstr->substream);
64}
65
66static irqreturn_t skl_interrupt(int irq, void *dev_id)
67{
68 struct hdac_ext_bus *ebus = dev_id;
69 struct hdac_bus *bus = ebus_to_hbus(ebus);
70 u32 status;
71
72 if (!pm_runtime_active(bus->dev))
73 return IRQ_NONE;
74
75 spin_lock(&bus->reg_lock);
76
77 status = snd_hdac_chip_readl(bus, INTSTS);
78 if (status == 0 || status == 0xffffffff) {
79 spin_unlock(&bus->reg_lock);
80 return IRQ_NONE;
81 }
82
83 /* clear rirb int */
84 status = snd_hdac_chip_readb(bus, RIRBSTS);
85 if (status & RIRB_INT_MASK) {
86 if (status & RIRB_INT_RESPONSE)
87 snd_hdac_bus_update_rirb(bus);
88 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
89 }
90
91 spin_unlock(&bus->reg_lock);
92
93 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
94}
95
96static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
97{
98 struct hdac_ext_bus *ebus = dev_id;
99 struct hdac_bus *bus = ebus_to_hbus(ebus);
100 u32 status;
101
102 status = snd_hdac_chip_readl(bus, INTSTS);
103
104 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
105
106 return IRQ_HANDLED;
107}
108
109static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
110{
111 struct skl *skl = ebus_to_skl(ebus);
112 struct hdac_bus *bus = ebus_to_hbus(ebus);
113 int ret;
114
115 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
116 skl_threaded_handler,
117 IRQF_SHARED,
118 KBUILD_MODNAME, ebus);
119 if (ret) {
120 dev_err(bus->dev,
121 "unable to grab IRQ %d, disabling device\n",
122 skl->pci->irq);
123 return ret;
124 }
125
126 bus->irq = skl->pci->irq;
127 pci_intx(skl->pci, 1);
128
129 return 0;
130}
131
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530132#ifdef CONFIG_PM
Jeeja KP61722f42015-10-27 09:23:00 +0900133static int _skl_suspend(struct hdac_ext_bus *ebus)
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530134{
Jeeja KP2a29b202015-10-07 11:31:58 +0100135 struct skl *skl = ebus_to_skl(ebus);
Jeeja KP61722f42015-10-27 09:23:00 +0900136 struct hdac_bus *bus = ebus_to_hbus(ebus);
Jeeja KP2a29b202015-10-07 11:31:58 +0100137 int ret;
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530138
Jeeja KP01bb84b2015-10-09 09:01:51 +0100139 snd_hdac_ext_bus_link_power_down_all(ebus);
140
Jeeja KP2a29b202015-10-07 11:31:58 +0100141 ret = skl_suspend_dsp(skl);
142 if (ret < 0)
143 return ret;
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530144
145 snd_hdac_bus_stop_chip(bus);
146 snd_hdac_bus_enter_link_reset(bus);
147
148 return 0;
149}
150
Jeeja KP61722f42015-10-27 09:23:00 +0900151static int _skl_resume(struct hdac_ext_bus *ebus)
152{
153 struct skl *skl = ebus_to_skl(ebus);
154 struct hdac_bus *bus = ebus_to_hbus(ebus);
155
156 skl_init_pci(skl);
157 snd_hdac_bus_init_chip(bus, true);
158
159 return skl_resume_dsp(skl);
160}
161#endif
162
163#ifdef CONFIG_PM_SLEEP
164/*
165 * power management
166 */
167static int skl_suspend(struct device *dev)
168{
169 struct pci_dev *pci = to_pci_dev(dev);
170 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
171
172 return _skl_suspend(ebus);
173}
174
175static int skl_resume(struct device *dev)
176{
177 struct pci_dev *pci = to_pci_dev(dev);
178 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
179
180 return _skl_resume(ebus);
181}
182#endif /* CONFIG_PM_SLEEP */
183
184#ifdef CONFIG_PM
185static int skl_runtime_suspend(struct device *dev)
186{
187 struct pci_dev *pci = to_pci_dev(dev);
188 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
189 struct hdac_bus *bus = ebus_to_hbus(ebus);
190
191 dev_dbg(bus->dev, "in %s\n", __func__);
192
193 /* enable controller wake up event */
194 snd_hdac_chip_updatew(bus, WAKEEN, 0, STATESTS_INT_MASK);
195
196 return _skl_suspend(ebus);
197}
198
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530199static int skl_runtime_resume(struct device *dev)
200{
201 struct pci_dev *pci = to_pci_dev(dev);
202 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
203 struct hdac_bus *bus = ebus_to_hbus(ebus);
Jeeja KP2a29b202015-10-07 11:31:58 +0100204 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530205 int status;
206
207 dev_dbg(bus->dev, "in %s\n", __func__);
208
209 /* Read STATESTS before controller reset */
210 status = snd_hdac_chip_readw(bus, STATESTS);
211
Jeeja KP2a29b202015-10-07 11:31:58 +0100212 skl_init_pci(skl);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530213 snd_hdac_bus_init_chip(bus, true);
214 /* disable controller Wake Up event */
215 snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, 0);
216
Jeeja KP61722f42015-10-27 09:23:00 +0900217 return _skl_resume(ebus);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530218}
219#endif /* CONFIG_PM */
220
221static const struct dev_pm_ops skl_pm = {
222 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
223 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
224};
225
226/*
227 * destructor
228 */
229static int skl_free(struct hdac_ext_bus *ebus)
230{
231 struct skl *skl = ebus_to_skl(ebus);
232 struct hdac_bus *bus = ebus_to_hbus(ebus);
233
234 skl->init_failed = 1; /* to be sure */
235
236 snd_hdac_ext_stop_streams(ebus);
237
238 if (bus->irq >= 0)
239 free_irq(bus->irq, (void *)bus);
240 if (bus->remap_addr)
241 iounmap(bus->remap_addr);
242
243 snd_hdac_bus_free_stream_pages(bus);
244 snd_hdac_stream_free_all(ebus);
245 snd_hdac_link_free_all(ebus);
246 pci_release_regions(skl->pci);
247 pci_disable_device(skl->pci);
248
249 snd_hdac_ext_bus_exit(ebus);
250
251 return 0;
252}
253
254static int skl_dmic_device_register(struct skl *skl)
255{
256 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
257 struct platform_device *pdev;
258 int ret;
259
260 /* SKL has one dmic port, so allocate dmic device for this */
261 pdev = platform_device_alloc("dmic-codec", -1);
262 if (!pdev) {
263 dev_err(bus->dev, "failed to allocate dmic device\n");
264 return -ENOMEM;
265 }
266
267 ret = platform_device_add(pdev);
268 if (ret) {
269 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
270 platform_device_put(pdev);
271 return ret;
272 }
273 skl->dmic_dev = pdev;
274
275 return 0;
276}
277
278static void skl_dmic_device_unregister(struct skl *skl)
279{
280 if (skl->dmic_dev)
281 platform_device_unregister(skl->dmic_dev);
282}
283
284/*
285 * Probe the given codec address
286 */
287static int probe_codec(struct hdac_ext_bus *ebus, int addr)
288{
289 struct hdac_bus *bus = ebus_to_hbus(ebus);
290 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
291 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
292 unsigned int res;
293
294 mutex_lock(&bus->cmd_mutex);
295 snd_hdac_bus_send_cmd(bus, cmd);
296 snd_hdac_bus_get_response(bus, addr, &res);
297 mutex_unlock(&bus->cmd_mutex);
298 if (res == -1)
299 return -EIO;
300 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
301
302 return snd_hdac_ext_bus_device_init(ebus, addr);
303}
304
305/* Codec initialization */
306static int skl_codec_create(struct hdac_ext_bus *ebus)
307{
308 struct hdac_bus *bus = ebus_to_hbus(ebus);
309 int c, max_slots;
310
311 max_slots = HDA_MAX_CODECS;
312
313 /* First try to probe all given codec slots */
314 for (c = 0; c < max_slots; c++) {
315 if ((bus->codec_mask & (1 << c))) {
316 if (probe_codec(ebus, c) < 0) {
317 /*
318 * Some BIOSen give you wrong codec addresses
319 * that don't exist
320 */
321 dev_warn(bus->dev,
322 "Codec #%d probe error; disabling it...\n", c);
323 bus->codec_mask &= ~(1 << c);
324 /*
325 * More badly, accessing to a non-existing
326 * codec often screws up the controller bus,
327 * and disturbs the further communications.
328 * Thus if an error occurs during probing,
329 * better to reset the controller bus to get
330 * back to the sanity state.
331 */
332 snd_hdac_bus_stop_chip(bus);
333 snd_hdac_bus_init_chip(bus, true);
334 }
335 }
336 }
337
338 return 0;
339}
340
341static const struct hdac_bus_ops bus_core_ops = {
342 .command = snd_hdac_bus_send_cmd,
343 .get_response = snd_hdac_bus_get_response,
344};
345
346/*
347 * constructor
348 */
349static int skl_create(struct pci_dev *pci,
350 const struct hdac_io_ops *io_ops,
351 struct skl **rskl)
352{
353 struct skl *skl;
354 struct hdac_ext_bus *ebus;
355
356 int err;
357
358 *rskl = NULL;
359
360 err = pci_enable_device(pci);
361 if (err < 0)
362 return err;
363
364 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
365 if (!skl) {
366 pci_disable_device(pci);
367 return -ENOMEM;
368 }
369 ebus = &skl->ebus;
370 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
371 ebus->bus.use_posbuf = 1;
372 skl->pci = pci;
373
374 ebus->bus.bdl_pos_adj = 0;
375
376 *rskl = skl;
377
378 return 0;
379}
380
381static int skl_first_init(struct hdac_ext_bus *ebus)
382{
383 struct skl *skl = ebus_to_skl(ebus);
384 struct hdac_bus *bus = ebus_to_hbus(ebus);
385 struct pci_dev *pci = skl->pci;
386 int err;
387 unsigned short gcap;
388 int cp_streams, pb_streams, start_idx;
389
390 err = pci_request_regions(pci, "Skylake HD audio");
391 if (err < 0)
392 return err;
393
394 bus->addr = pci_resource_start(pci, 0);
395 bus->remap_addr = pci_ioremap_bar(pci, 0);
396 if (bus->remap_addr == NULL) {
397 dev_err(bus->dev, "ioremap error\n");
398 return -ENXIO;
399 }
400
Jeeja KP05057002015-07-09 15:20:11 +0530401 snd_hdac_ext_bus_parse_capabilities(ebus);
402
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530403 if (skl_acquire_irq(ebus, 0) < 0)
404 return -EBUSY;
405
406 pci_set_master(pci);
407 synchronize_irq(bus->irq);
408
409 gcap = snd_hdac_chip_readw(bus, GCAP);
410 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
411
412 /* allow 64bit DMA address if supported by H/W */
413 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
414 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
415 } else {
416 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
417 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
418 }
419
420 /* read number of streams from GCAP register */
421 cp_streams = (gcap >> 8) & 0x0f;
422 pb_streams = (gcap >> 12) & 0x0f;
423
424 if (!pb_streams && !cp_streams)
425 return -EIO;
426
427 ebus->num_streams = cp_streams + pb_streams;
428
429 /* initialize streams */
430 snd_hdac_ext_stream_init_all
431 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
432 start_idx = cp_streams;
433 snd_hdac_ext_stream_init_all
434 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
435
436 err = snd_hdac_bus_alloc_stream_pages(bus);
437 if (err < 0)
438 return err;
439
440 /* initialize chip */
441 skl_init_pci(skl);
442
443 snd_hdac_bus_init_chip(bus, true);
444
445 /* codec detection */
446 if (!bus->codec_mask) {
Jeeja KP029890c2015-10-27 09:22:47 +0900447 dev_info(bus->dev, "no hda codecs found!\n");
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530448 }
449
450 return 0;
451}
452
453static int skl_probe(struct pci_dev *pci,
454 const struct pci_device_id *pci_id)
455{
456 struct skl *skl;
457 struct hdac_ext_bus *ebus = NULL;
458 struct hdac_bus *bus = NULL;
459 int err;
460
461 /* we use ext core ops, so provide NULL for ops here */
462 err = skl_create(pci, NULL, &skl);
463 if (err < 0)
464 return err;
465
466 ebus = &skl->ebus;
467 bus = ebus_to_hbus(ebus);
468
469 err = skl_first_init(ebus);
470 if (err < 0)
471 goto out_free;
472
Jeeja KP87b2bdf2015-10-07 11:31:59 +0100473 skl->nhlt = skl_nhlt_init(bus->dev);
474
475 if (skl->nhlt == NULL)
476 goto out_free;
477
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530478 pci_set_drvdata(skl->pci, ebus);
479
Jeeja KP05057002015-07-09 15:20:11 +0530480 /* check if dsp is there */
481 if (ebus->ppcap) {
Jeeja KP2a29b202015-10-07 11:31:58 +0100482 err = skl_init_dsp(skl);
483 if (err < 0) {
484 dev_dbg(bus->dev, "error failed to register dsp\n");
485 goto out_free;
486 }
Jeeja KP05057002015-07-09 15:20:11 +0530487 }
Jeeja KP05057002015-07-09 15:20:11 +0530488 if (ebus->mlcap)
489 snd_hdac_ext_bus_get_ml_capabilities(ebus);
490
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530491 /* create device for soc dmic */
492 err = skl_dmic_device_register(skl);
493 if (err < 0)
Jeeja KP2a29b202015-10-07 11:31:58 +0100494 goto out_dsp_free;
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530495
496 /* register platform dai and controls */
497 err = skl_platform_register(bus->dev);
498 if (err < 0)
499 goto out_dmic_free;
500
501 /* create codec instances */
502 err = skl_codec_create(ebus);
503 if (err < 0)
504 goto out_unregister;
505
506 /*configure PM */
507 pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY);
508 pm_runtime_use_autosuspend(bus->dev);
509 pm_runtime_put_noidle(bus->dev);
510 pm_runtime_allow(bus->dev);
511
512 return 0;
513
514out_unregister:
515 skl_platform_unregister(bus->dev);
516out_dmic_free:
517 skl_dmic_device_unregister(skl);
Jeeja KP2a29b202015-10-07 11:31:58 +0100518out_dsp_free:
519 skl_free_dsp(skl);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530520out_free:
521 skl->init_failed = 1;
522 skl_free(ebus);
523
524 return err;
525}
526
527static void skl_remove(struct pci_dev *pci)
528{
529 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
530 struct skl *skl = ebus_to_skl(ebus);
531
532 if (pci_dev_run_wake(pci))
533 pm_runtime_get_noresume(&pci->dev);
534 pci_dev_put(pci);
535 skl_platform_unregister(&pci->dev);
Jeeja KP2a29b202015-10-07 11:31:58 +0100536 skl_free_dsp(skl);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530537 skl_dmic_device_unregister(skl);
538 skl_free(ebus);
539 dev_set_drvdata(&pci->dev, NULL);
540}
541
542/* PCI IDs */
543static const struct pci_device_id skl_ids[] = {
544 /* Sunrise Point-LP */
545 { PCI_DEVICE(0x8086, 0x9d70), 0},
546 { 0, }
547};
548MODULE_DEVICE_TABLE(pci, skl_ids);
549
550/* pci_driver definition */
551static struct pci_driver skl_driver = {
552 .name = KBUILD_MODNAME,
553 .id_table = skl_ids,
554 .probe = skl_probe,
555 .remove = skl_remove,
556 .driver = {
557 .pm = &skl_pm,
558 },
559};
560module_pci_driver(skl_driver);
561
562MODULE_LICENSE("GPL v2");
563MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");