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yanyang15fc3aee2015-05-22 14:39:35 -04001/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
Jammy Zhou0b2daf02015-07-21 17:41:48 +080026#define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
27
28/*
Jammy Zhou2f7d10b2015-07-22 11:29:01 +080029 * Supported ASIC types
30 */
31enum amd_asic_type {
Ken Wang26d721c2016-01-21 17:00:06 +080032 CHIP_TAHITI = 0,
33 CHIP_PITCAIRN,
34 CHIP_VERDE,
35 CHIP_OLAND,
36 CHIP_HAINAN,
37 CHIP_BONAIRE,
Jammy Zhou2f7d10b2015-07-22 11:29:01 +080038 CHIP_KAVERI,
39 CHIP_KABINI,
40 CHIP_HAWAII,
41 CHIP_MULLINS,
42 CHIP_TOPAZ,
43 CHIP_TONGA,
David Zhang48299f92015-07-08 01:05:16 +080044 CHIP_FIJI,
Jammy Zhou2f7d10b2015-07-22 11:29:01 +080045 CHIP_CARRIZO,
Samuel Li139f4912015-10-08 14:50:27 -040046 CHIP_STONEY,
Flora Cui2cc0c0b2016-03-14 18:33:29 -040047 CHIP_POLARIS10,
48 CHIP_POLARIS11,
Jammy Zhou2f7d10b2015-07-22 11:29:01 +080049 CHIP_LAST,
50};
51
52/*
53 * Chip flags
54 */
55enum amd_chip_flags {
56 AMD_ASIC_MASK = 0x0000ffffUL,
57 AMD_FLAGS_MASK = 0xffff0000UL,
58 AMD_IS_MOBILITY = 0x00010000UL,
59 AMD_IS_APU = 0x00020000UL,
60 AMD_IS_PX = 0x00040000UL,
61 AMD_EXP_HW_SUPPORT = 0x00080000UL,
62};
63
yanyang15fc3aee2015-05-22 14:39:35 -040064enum amd_ip_block_type {
65 AMD_IP_BLOCK_TYPE_COMMON,
66 AMD_IP_BLOCK_TYPE_GMC,
67 AMD_IP_BLOCK_TYPE_IH,
68 AMD_IP_BLOCK_TYPE_SMC,
69 AMD_IP_BLOCK_TYPE_DCE,
70 AMD_IP_BLOCK_TYPE_GFX,
71 AMD_IP_BLOCK_TYPE_SDMA,
72 AMD_IP_BLOCK_TYPE_UVD,
73 AMD_IP_BLOCK_TYPE_VCE,
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -040074 AMD_IP_BLOCK_TYPE_ACP,
yanyang15fc3aee2015-05-22 14:39:35 -040075};
76
77enum amd_clockgating_state {
78 AMD_CG_STATE_GATE = 0,
79 AMD_CG_STATE_UNGATE,
80};
81
82enum amd_powergating_state {
83 AMD_PG_STATE_GATE = 0,
84 AMD_PG_STATE_UNGATE,
85};
86
Alex Deuchere3b04bc2016-02-05 10:56:22 -050087/* CG flags */
88#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
89#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
90#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
91#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
92#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
93#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
94#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
95#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
96#define AMD_CG_SUPPORT_MC_LS (1 << 8)
97#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
98#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
99#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
100#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
101#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
102#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
103#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
104#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
Alex Deucher4fae91c2016-04-08 00:52:24 -0400105#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
Alex Deuchere3b04bc2016-02-05 10:56:22 -0500106
107/* PG flags */
108#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
109#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
110#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
111#define AMD_PG_SUPPORT_UVD (1 << 3)
112#define AMD_PG_SUPPORT_VCE (1 << 4)
113#define AMD_PG_SUPPORT_CP (1 << 5)
114#define AMD_PG_SUPPORT_GDS (1 << 6)
115#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
116#define AMD_PG_SUPPORT_SDMA (1 << 8)
117#define AMD_PG_SUPPORT_ACP (1 << 9)
118#define AMD_PG_SUPPORT_SAMU (1 << 10)
Alex Deucher6b0432b2016-05-04 10:06:21 -0400119#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
120#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
Alex Deuchere3b04bc2016-02-05 10:56:22 -0500121
Rex Zhu3a2c7882015-08-25 15:57:43 +0800122enum amd_pm_state_type {
123 /* not used for dpm */
124 POWER_STATE_TYPE_DEFAULT,
125 POWER_STATE_TYPE_POWERSAVE,
126 /* user selectable states */
127 POWER_STATE_TYPE_BATTERY,
128 POWER_STATE_TYPE_BALANCED,
129 POWER_STATE_TYPE_PERFORMANCE,
130 /* internal states */
131 POWER_STATE_TYPE_INTERNAL_UVD,
132 POWER_STATE_TYPE_INTERNAL_UVD_SD,
133 POWER_STATE_TYPE_INTERNAL_UVD_HD,
134 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
135 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
136 POWER_STATE_TYPE_INTERNAL_BOOT,
137 POWER_STATE_TYPE_INTERNAL_THERMAL,
138 POWER_STATE_TYPE_INTERNAL_ACPI,
139 POWER_STATE_TYPE_INTERNAL_ULV,
140 POWER_STATE_TYPE_INTERNAL_3DPERF,
141};
142
yanyang15fc3aee2015-05-22 14:39:35 -0400143struct amd_ip_funcs {
Tom St Denis88a907d2016-05-04 14:28:35 -0400144 /* Name of IP block */
145 char *name;
yanyang15fc3aee2015-05-22 14:39:35 -0400146 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
147 int (*early_init)(void *handle);
148 /* sets up late driver/hw state (post hw_init) - Optional */
149 int (*late_init)(void *handle);
150 /* sets up driver state, does not configure hw */
151 int (*sw_init)(void *handle);
152 /* tears down driver state, does not configure hw */
153 int (*sw_fini)(void *handle);
154 /* sets up the hw state */
155 int (*hw_init)(void *handle);
156 /* tears down the hw state */
157 int (*hw_fini)(void *handle);
Monk Liu212cb3b2016-05-19 14:35:17 +0800158 void (*late_fini)(void *handle);
yanyang15fc3aee2015-05-22 14:39:35 -0400159 /* handles IP specific hw/sw changes for suspend */
160 int (*suspend)(void *handle);
161 /* handles IP specific hw/sw changes for resume */
162 int (*resume)(void *handle);
163 /* returns current IP block idle status */
164 bool (*is_idle)(void *handle);
165 /* poll for idle */
166 int (*wait_for_idle)(void *handle);
Chunming Zhou63fbf422016-07-15 11:19:20 +0800167 /* check soft reset the IP block */
Alex Deucherda146d32016-10-13 16:07:03 -0400168 bool (*check_soft_reset)(void *handle);
Chunming Zhoud31a5012016-07-18 10:04:34 +0800169 /* pre soft reset the IP block */
170 int (*pre_soft_reset)(void *handle);
yanyang15fc3aee2015-05-22 14:39:35 -0400171 /* soft reset the IP block */
172 int (*soft_reset)(void *handle);
Chunming Zhou35d782f2016-07-15 15:57:13 +0800173 /* post soft reset the IP block */
174 int (*post_soft_reset)(void *handle);
yanyang15fc3aee2015-05-22 14:39:35 -0400175 /* enable/disable cg for the IP block */
176 int (*set_clockgating_state)(void *handle,
177 enum amd_clockgating_state state);
178 /* enable/disable pg for the IP block */
179 int (*set_powergating_state)(void *handle,
180 enum amd_powergating_state state);
181};
182
183#endif /* __AMD_SHARED_H__ */