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Alex Deucher97b2e202015-04-20 16:51:00 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
Chris Wilsonf54d1862016-10-25 13:00:45 +010037#include <linux/dma-fence.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040038
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
Chunming Zhoud03846a2015-07-28 14:20:03 -040045#include <drm/drmP.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040046#include <drm/drm_gem.h>
Chunming Zhou7e5a5472015-04-24 17:37:30 +080047#include <drm/amdgpu_drm.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040048
yanyang15fc3aee2015-05-22 14:39:35 -040049#include "amd_shared.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040050#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
Flora Cuic632d792016-08-02 11:32:41 +080054#include "amdgpu_ttm.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040055#include "amdgpu_gds.h"
Christian König56113502016-09-28 12:36:44 +020056#include "amdgpu_sync.h"
Christian König78023012016-09-28 15:33:18 +020057#include "amdgpu_ring.h"
Christian König073440d2016-09-28 15:41:50 +020058#include "amdgpu_vm.h"
Alex Deucher1f7371b2015-12-02 17:46:21 -050059#include "amd_powerplay.h"
Alex Deuchercf0978812016-10-07 11:40:09 -040060#include "amdgpu_dpm.h"
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -040061#include "amdgpu_acp.h"
Leo Liu4df654d2017-01-02 10:07:33 -050062#include "amdgpu_uvd.h"
Leo Liu5e568172017-01-10 11:02:58 -050063#include "amdgpu_vce.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040064
Alex Deucherb80d8472015-08-16 22:55:02 -040065#include "gpu_scheduler.h"
Monk Liuceeb50e2016-09-19 12:13:58 +080066#include "amdgpu_virt.h"
Alex Deucherb80d8472015-08-16 22:55:02 -040067
Alex Deucher97b2e202015-04-20 16:51:00 -040068/*
69 * Modules parameters.
70 */
71extern int amdgpu_modeset;
72extern int amdgpu_vram_limit;
73extern int amdgpu_gart_size;
Marek Olšák95844d22016-08-17 23:49:27 +020074extern int amdgpu_moverate;
Alex Deucher97b2e202015-04-20 16:51:00 -040075extern int amdgpu_benchmarking;
76extern int amdgpu_testing;
77extern int amdgpu_audio;
78extern int amdgpu_disp_priority;
79extern int amdgpu_hw_i2c;
80extern int amdgpu_pcie_gen2;
81extern int amdgpu_msi;
82extern int amdgpu_lockup_timeout;
83extern int amdgpu_dpm;
Huang Ruie635ee02016-11-01 15:35:38 +080084extern int amdgpu_fw_load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -040085extern int amdgpu_aspm;
86extern int amdgpu_runtime_pm;
Alex Deucher97b2e202015-04-20 16:51:00 -040087extern unsigned amdgpu_ip_block_mask;
88extern int amdgpu_bapm;
89extern int amdgpu_deep_color;
90extern int amdgpu_vm_size;
91extern int amdgpu_vm_block_size;
Christian Königd9c13152015-09-28 12:31:26 +020092extern int amdgpu_vm_fault_stop;
Christian Königb495bd32015-09-10 14:00:35 +020093extern int amdgpu_vm_debug;
Jammy Zhou1333f722015-07-30 16:36:58 +080094extern int amdgpu_sched_jobs;
Jammy Zhou4afcb302015-07-30 16:44:05 +080095extern int amdgpu_sched_hw_submission;
Rex Zhu3ca67302016-11-02 13:38:37 +080096extern int amdgpu_no_evict;
97extern int amdgpu_direct_gma_size;
Alex Deuchercd474ba2016-02-04 10:21:23 -050098extern unsigned amdgpu_pcie_gen_cap;
99extern unsigned amdgpu_pcie_lane_cap;
Nicolai Hähnle395d1fb2016-06-02 12:32:07 +0200100extern unsigned amdgpu_cg_mask;
101extern unsigned amdgpu_pg_mask;
Nicolai Hähnle6f8941a2016-06-17 19:31:33 +0200102extern char *amdgpu_disable_cu;
Emily Deng9accf2f2016-08-10 16:01:25 +0800103extern char *amdgpu_virtual_display;
Rex Zhu5141e9d2016-09-06 16:34:37 +0800104extern unsigned amdgpu_pp_feature_mask;
Christian König6a7f76e2016-08-24 15:51:49 +0200105extern int amdgpu_vram_page_split;
Alex Deucher97b2e202015-04-20 16:51:00 -0400106
Chunming Zhou4b559c92015-07-21 15:53:04 +0800107#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
Alex Deucher97b2e202015-04-20 16:51:00 -0400108#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
111#define AMDGPU_IB_POOL_SIZE 16
112#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
113#define AMDGPUFB_CONN_LIMIT 4
Alex Deuchera5bde2f2016-09-23 16:23:41 -0400114#define AMDGPU_BIOS_NUM_SCRATCH 16
Alex Deucher97b2e202015-04-20 16:51:00 -0400115
Jammy Zhou36f523a2015-09-01 12:54:27 +0800116/* max number of IP instances */
117#define AMDGPU_MAX_SDMA_INSTANCES 2
118
Alex Deucher97b2e202015-04-20 16:51:00 -0400119/* hardcode that limit for now */
120#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
121
122/* hard reset data */
123#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
124
125/* reset flags */
126#define AMDGPU_RESET_GFX (1 << 0)
127#define AMDGPU_RESET_COMPUTE (1 << 1)
128#define AMDGPU_RESET_DMA (1 << 2)
129#define AMDGPU_RESET_CP (1 << 3)
130#define AMDGPU_RESET_GRBM (1 << 4)
131#define AMDGPU_RESET_DMA1 (1 << 5)
132#define AMDGPU_RESET_RLC (1 << 6)
133#define AMDGPU_RESET_SEM (1 << 7)
134#define AMDGPU_RESET_IH (1 << 8)
135#define AMDGPU_RESET_VMC (1 << 9)
136#define AMDGPU_RESET_MC (1 << 10)
137#define AMDGPU_RESET_DISPLAY (1 << 11)
138#define AMDGPU_RESET_UVD (1 << 12)
139#define AMDGPU_RESET_VCE (1 << 13)
140#define AMDGPU_RESET_VCE1 (1 << 14)
141
Alex Deucher97b2e202015-04-20 16:51:00 -0400142/* GFX current status */
143#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
144#define AMDGPU_GFX_SAFE_MODE 0x00000001L
145#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
146#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
147#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
148
149/* max cursor sizes (in pixels) */
150#define CIK_CURSOR_WIDTH 128
151#define CIK_CURSOR_HEIGHT 128
152
153struct amdgpu_device;
Alex Deucher97b2e202015-04-20 16:51:00 -0400154struct amdgpu_ib;
Alex Deucher97b2e202015-04-20 16:51:00 -0400155struct amdgpu_cs_parser;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800156struct amdgpu_job;
Alex Deucher97b2e202015-04-20 16:51:00 -0400157struct amdgpu_irq_src;
Alex Deucher0b492a42015-08-16 22:48:26 -0400158struct amdgpu_fpriv;
Alex Deucher97b2e202015-04-20 16:51:00 -0400159
160enum amdgpu_cp_irq {
161 AMDGPU_CP_IRQ_GFX_EOP = 0,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
170
171 AMDGPU_CP_IRQ_LAST
172};
173
174enum amdgpu_sdma_irq {
175 AMDGPU_SDMA_IRQ_TRAP0 = 0,
176 AMDGPU_SDMA_IRQ_TRAP1,
177
178 AMDGPU_SDMA_IRQ_LAST
179};
180
181enum amdgpu_thermal_irq {
182 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
183 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
184
185 AMDGPU_THERMAL_IRQ_LAST
186};
187
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800188enum amdgpu_kiq_irq {
189 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
190 AMDGPU_CP_KIQ_IRQ_LAST
191};
192
Alex Deucher97b2e202015-04-20 16:51:00 -0400193int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400194 enum amd_ip_block_type block_type,
195 enum amd_clockgating_state state);
Alex Deucher97b2e202015-04-20 16:51:00 -0400196int amdgpu_set_powergating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400197 enum amd_ip_block_type block_type,
198 enum amd_powergating_state state);
Huang Rui6cb2d4e2017-01-05 18:44:41 +0800199void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
Alex Deucher5dbbb602016-06-23 11:41:04 -0400200int amdgpu_wait_for_idle(struct amdgpu_device *adev,
201 enum amd_ip_block_type block_type);
202bool amdgpu_is_idle(struct amdgpu_device *adev,
203 enum amd_ip_block_type block_type);
Alex Deucher97b2e202015-04-20 16:51:00 -0400204
Alex Deuchera1255102016-10-13 17:41:13 -0400205#define AMDGPU_MAX_IP_NUM 16
206
207struct amdgpu_ip_block_status {
208 bool valid;
209 bool sw;
210 bool hw;
211 bool late_initialized;
212 bool hang;
213};
214
Alex Deucher97b2e202015-04-20 16:51:00 -0400215struct amdgpu_ip_block_version {
Alex Deuchera1255102016-10-13 17:41:13 -0400216 const enum amd_ip_block_type type;
217 const u32 major;
218 const u32 minor;
219 const u32 rev;
yanyang15fc3aee2015-05-22 14:39:35 -0400220 const struct amd_ip_funcs *funcs;
Alex Deucher97b2e202015-04-20 16:51:00 -0400221};
222
Alex Deuchera1255102016-10-13 17:41:13 -0400223struct amdgpu_ip_block {
224 struct amdgpu_ip_block_status status;
225 const struct amdgpu_ip_block_version *version;
226};
227
Alex Deucher97b2e202015-04-20 16:51:00 -0400228int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400229 enum amd_ip_block_type type,
Alex Deucher97b2e202015-04-20 16:51:00 -0400230 u32 major, u32 minor);
231
Alex Deuchera1255102016-10-13 17:41:13 -0400232struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
233 enum amd_ip_block_type type);
234
235int amdgpu_ip_block_add(struct amdgpu_device *adev,
236 const struct amdgpu_ip_block_version *ip_block_version);
Alex Deucher97b2e202015-04-20 16:51:00 -0400237
238/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
239struct amdgpu_buffer_funcs {
240 /* maximum bytes in a single operation */
241 uint32_t copy_max_bytes;
242
243 /* number of dw to reserve per operation */
244 unsigned copy_num_dw;
245
246 /* used for buffer migration */
Chunming Zhouc7ae72c2015-08-25 17:23:45 +0800247 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400248 /* src addr in bytes */
249 uint64_t src_offset,
250 /* dst addr in bytes */
251 uint64_t dst_offset,
252 /* number of byte to transfer */
253 uint32_t byte_count);
254
255 /* maximum bytes in a single operation */
256 uint32_t fill_max_bytes;
257
258 /* number of dw to reserve per operation */
259 unsigned fill_num_dw;
260
261 /* used for buffer clearing */
Chunming Zhou6e7a3842015-08-27 13:46:09 +0800262 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400263 /* value to write to memory */
264 uint32_t src_data,
265 /* dst addr in bytes */
266 uint64_t dst_offset,
267 /* number of byte to fill */
268 uint32_t byte_count);
269};
270
271/* provided by hw blocks that can write ptes, e.g., sdma */
272struct amdgpu_vm_pte_funcs {
273 /* copy pte entries from GART */
274 void (*copy_pte)(struct amdgpu_ib *ib,
275 uint64_t pe, uint64_t src,
276 unsigned count);
277 /* write pte one entry at a time with addr mapping */
Christian Königde9ea7b2016-08-12 11:33:30 +0200278 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
279 uint64_t value, unsigned count,
280 uint32_t incr);
Alex Deucher97b2e202015-04-20 16:51:00 -0400281 /* for linear pte/pde updates without addr mapping */
282 void (*set_pte_pde)(struct amdgpu_ib *ib,
283 uint64_t pe,
284 uint64_t addr, unsigned count,
Chunming Zhou6b777602016-09-21 16:19:19 +0800285 uint32_t incr, uint64_t flags);
Alex Deucher97b2e202015-04-20 16:51:00 -0400286};
287
288/* provided by the gmc block */
289struct amdgpu_gart_funcs {
290 /* flush the vm tlb via mmio */
291 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
292 uint32_t vmid);
293 /* write pte/pde updates using the cpu */
294 int (*set_pte_pde)(struct amdgpu_device *adev,
295 void *cpu_pt_addr, /* cpu addr of page table */
296 uint32_t gpu_page_idx, /* pte/pde to update */
297 uint64_t addr, /* addr to write into pte/pde */
Chunming Zhou6b777602016-09-21 16:19:19 +0800298 uint64_t flags); /* access flags */
Christian König284710f2017-01-30 11:09:31 +0100299 /* enable/disable PRT support */
300 void (*set_prt)(struct amdgpu_device *adev, bool enable);
Alex Xie54635452017-02-14 12:22:57 -0500301 /* set pte flags based per asic */
302 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
303 uint32_t flags);
Alex Deucher97b2e202015-04-20 16:51:00 -0400304};
305
306/* provided by the ih block */
307struct amdgpu_ih_funcs {
308 /* ring read/write ptr handling, called from interrupt context */
309 u32 (*get_wptr)(struct amdgpu_device *adev);
310 void (*decode_iv)(struct amdgpu_device *adev,
311 struct amdgpu_iv_entry *entry);
312 void (*set_rptr)(struct amdgpu_device *adev);
313};
314
Alex Deucher97b2e202015-04-20 16:51:00 -0400315/*
316 * BIOS.
317 */
318bool amdgpu_get_bios(struct amdgpu_device *adev);
319bool amdgpu_read_bios(struct amdgpu_device *adev);
320
321/*
322 * Dummy page
323 */
324struct amdgpu_dummy_page {
325 struct page *page;
326 dma_addr_t addr;
327};
328int amdgpu_dummy_page_init(struct amdgpu_device *adev);
329void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
330
331
332/*
333 * Clocks
334 */
335
336#define AMDGPU_MAX_PPLL 3
337
338struct amdgpu_clock {
339 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
340 struct amdgpu_pll spll;
341 struct amdgpu_pll mpll;
342 /* 10 Khz units */
343 uint32_t default_mclk;
344 uint32_t default_sclk;
345 uint32_t default_dispclk;
346 uint32_t current_dispclk;
347 uint32_t dp_extclk;
348 uint32_t max_pixel_clock;
349};
350
351/*
Flora Cuic632d792016-08-02 11:32:41 +0800352 * BO.
Alex Deucher97b2e202015-04-20 16:51:00 -0400353 */
Alex Deucher97b2e202015-04-20 16:51:00 -0400354struct amdgpu_bo_list_entry {
355 struct amdgpu_bo *robj;
356 struct ttm_validate_buffer tv;
357 struct amdgpu_bo_va *bo_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400358 uint32_t priority;
Christian König2f568db2016-02-23 12:36:59 +0100359 struct page **user_pages;
360 int user_invalidated;
Alex Deucher97b2e202015-04-20 16:51:00 -0400361};
362
363struct amdgpu_bo_va_mapping {
364 struct list_head list;
365 struct interval_tree_node it;
366 uint64_t offset;
Christian König268c3002017-01-18 14:49:43 +0100367 uint64_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400368};
369
370/* bo virtual addresses in a specific vm */
371struct amdgpu_bo_va {
372 /* protected by bo being reserved */
373 struct list_head bo_list;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100374 struct dma_fence *last_pt_update;
Alex Deucher97b2e202015-04-20 16:51:00 -0400375 unsigned ref_count;
376
Christian König7fc11952015-07-30 11:53:42 +0200377 /* protected by vm mutex and spinlock */
Alex Deucher97b2e202015-04-20 16:51:00 -0400378 struct list_head vm_status;
379
Christian König7fc11952015-07-30 11:53:42 +0200380 /* mappings for this bo_va */
381 struct list_head invalids;
382 struct list_head valids;
383
Alex Deucher97b2e202015-04-20 16:51:00 -0400384 /* constant after initialization */
385 struct amdgpu_vm *vm;
386 struct amdgpu_bo *bo;
387};
388
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800389#define AMDGPU_GEM_DOMAIN_MAX 0x3
390
Alex Deucher97b2e202015-04-20 16:51:00 -0400391struct amdgpu_bo {
Alex Deucher97b2e202015-04-20 16:51:00 -0400392 /* Protected by tbo.reserved */
Christian König1ea863f2015-12-18 22:13:12 +0100393 u32 prefered_domains;
394 u32 allowed_domains;
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800395 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400396 struct ttm_placement placement;
397 struct ttm_buffer_object tbo;
398 struct ttm_bo_kmap_obj kmap;
399 u64 flags;
400 unsigned pin_count;
401 void *kptr;
402 u64 tiling_flags;
403 u64 metadata_flags;
404 void *metadata;
405 u32 metadata_size;
Mario Kleiner8e94a462016-11-09 02:25:15 +0100406 unsigned prime_shared_count;
Alex Deucher97b2e202015-04-20 16:51:00 -0400407 /* list of all virtual address to which this bo
408 * is associated to
409 */
410 struct list_head va;
411 /* Constant after initialization */
Alex Deucher97b2e202015-04-20 16:51:00 -0400412 struct drm_gem_object gem_base;
Christian König82b9c552015-11-27 16:49:00 +0100413 struct amdgpu_bo *parent;
Chunming Zhoue7893c42016-07-26 14:13:21 +0800414 struct amdgpu_bo *shadow;
Alex Deucher97b2e202015-04-20 16:51:00 -0400415
416 struct ttm_bo_kmap_obj dma_buf_vmap;
Alex Deucher97b2e202015-04-20 16:51:00 -0400417 struct amdgpu_mn *mn;
418 struct list_head mn_list;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +0800419 struct list_head shadow_list;
Alex Deucher97b2e202015-04-20 16:51:00 -0400420};
421#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
422
423void amdgpu_gem_object_free(struct drm_gem_object *obj);
424int amdgpu_gem_object_open(struct drm_gem_object *obj,
425 struct drm_file *file_priv);
426void amdgpu_gem_object_close(struct drm_gem_object *obj,
427 struct drm_file *file_priv);
428unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
429struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
Christian König4d9c5142016-05-03 18:46:19 +0200430struct drm_gem_object *
431amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
432 struct dma_buf_attachment *attach,
433 struct sg_table *sg);
Alex Deucher97b2e202015-04-20 16:51:00 -0400434struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
435 struct drm_gem_object *gobj,
436 int flags);
437int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
438void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
439struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
440void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
441void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
442int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
443
444/* sub-allocation manager, it has to be protected by another lock.
445 * By conception this is an helper for other part of the driver
446 * like the indirect buffer or semaphore, which both have their
447 * locking.
448 *
449 * Principe is simple, we keep a list of sub allocation in offset
450 * order (first entry has offset == 0, last entry has the highest
451 * offset).
452 *
453 * When allocating new object we first check if there is room at
454 * the end total_size - (last_object_offset + last_object_size) >=
455 * alloc_size. If so we allocate new object there.
456 *
457 * When there is not enough room at the end, we start waiting for
458 * each sub object until we reach object_offset+object_size >=
459 * alloc_size, this object then become the sub object we return.
460 *
461 * Alignment can't be bigger than page size.
462 *
463 * Hole are not considered for allocation to keep things simple.
464 * Assumption is that there won't be hole (all object on same
465 * alignment).
466 */
Christian König6ba60b82016-03-11 14:50:08 +0100467
468#define AMDGPU_SA_NUM_FENCE_LISTS 32
469
Alex Deucher97b2e202015-04-20 16:51:00 -0400470struct amdgpu_sa_manager {
471 wait_queue_head_t wq;
472 struct amdgpu_bo *bo;
473 struct list_head *hole;
Christian König6ba60b82016-03-11 14:50:08 +0100474 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
Alex Deucher97b2e202015-04-20 16:51:00 -0400475 struct list_head olist;
476 unsigned size;
477 uint64_t gpu_addr;
478 void *cpu_ptr;
479 uint32_t domain;
480 uint32_t align;
481};
482
Alex Deucher97b2e202015-04-20 16:51:00 -0400483/* sub-allocation buffer */
484struct amdgpu_sa_bo {
485 struct list_head olist;
486 struct list_head flist;
487 struct amdgpu_sa_manager *manager;
488 unsigned soffset;
489 unsigned eoffset;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100490 struct dma_fence *fence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400491};
492
493/*
494 * GEM objects.
495 */
Christian König418aa0c2016-02-15 16:59:57 +0100496void amdgpu_gem_force_release(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400497int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
498 int alignment, u32 initial_domain,
499 u64 flags, bool kernel,
500 struct drm_gem_object **obj);
501
502int amdgpu_mode_dumb_create(struct drm_file *file_priv,
503 struct drm_device *dev,
504 struct drm_mode_create_dumb *args);
505int amdgpu_mode_dumb_mmap(struct drm_file *filp,
506 struct drm_device *dev,
507 uint32_t handle, uint64_t *offset_p);
Rex Zhud573de22016-05-12 13:27:28 +0800508int amdgpu_fence_slab_init(void);
509void amdgpu_fence_slab_fini(void);
Alex Deucher97b2e202015-04-20 16:51:00 -0400510
511/*
512 * GART structures, functions & helpers
513 */
514struct amdgpu_mc;
515
516#define AMDGPU_GPU_PAGE_SIZE 4096
517#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
518#define AMDGPU_GPU_PAGE_SHIFT 12
519#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
520
521struct amdgpu_gart {
522 dma_addr_t table_addr;
523 struct amdgpu_bo *robj;
524 void *ptr;
525 unsigned num_gpu_pages;
526 unsigned num_cpu_pages;
527 unsigned table_size;
Christian Königa1d29472016-03-30 14:42:57 +0200528#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
Alex Deucher97b2e202015-04-20 16:51:00 -0400529 struct page **pages;
Christian Königa1d29472016-03-30 14:42:57 +0200530#endif
Alex Deucher97b2e202015-04-20 16:51:00 -0400531 bool ready;
Alex Xie4b98e0c2017-02-14 12:31:36 -0500532
533 /* Asic default pte flags */
534 uint64_t gart_pte_flags;
535
Alex Deucher97b2e202015-04-20 16:51:00 -0400536 const struct amdgpu_gart_funcs *gart_funcs;
537};
538
539int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
540void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
541int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
542void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
543int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
544void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
545int amdgpu_gart_init(struct amdgpu_device *adev);
546void amdgpu_gart_fini(struct amdgpu_device *adev);
Felix Kuehlingcab0b8d2016-08-12 19:25:21 -0400547void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
Alex Deucher97b2e202015-04-20 16:51:00 -0400548 int pages);
Felix Kuehlingcab0b8d2016-08-12 19:25:21 -0400549int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
Alex Deucher97b2e202015-04-20 16:51:00 -0400550 int pages, struct page **pagelist,
Chunming Zhou6b777602016-09-21 16:19:19 +0800551 dma_addr_t *dma_addr, uint64_t flags);
Chunming Zhou2c0d7312016-08-30 16:36:25 +0800552int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400553
554/*
555 * GPU MC structures, functions & helpers
556 */
557struct amdgpu_mc {
558 resource_size_t aper_size;
559 resource_size_t aper_base;
560 resource_size_t agp_base;
561 /* for some chips with <= 32MB we need to lie
562 * about vram size near mc fb location */
563 u64 mc_vram_size;
564 u64 visible_vram_size;
565 u64 gtt_size;
566 u64 gtt_start;
567 u64 gtt_end;
568 u64 vram_start;
569 u64 vram_end;
570 unsigned vram_width;
571 u64 real_vram_size;
572 int vram_mtrr;
573 u64 gtt_base_align;
574 u64 mc_mask;
575 const struct firmware *fw; /* MC firmware */
576 uint32_t fw_version;
577 struct amdgpu_irq_src vm_fault;
Ken Wang81c59f52015-06-03 21:02:01 +0800578 uint32_t vram_type;
Chunming Zhou50b01972016-07-18 16:59:24 +0800579 uint32_t srbm_soft_reset;
580 struct amdgpu_mode_mc_save save;
Christian Königf7c35ab2017-01-27 11:56:05 +0100581 bool prt_warning;
Junwei Zhang8fe73322016-03-10 14:20:39 +0800582 /* apertures */
583 u64 shared_aperture_start;
584 u64 shared_aperture_end;
585 u64 private_aperture_start;
586 u64 private_aperture_end;
Alex Deucher97b2e202015-04-20 16:51:00 -0400587};
588
589/*
590 * GPU doorbell structures, functions & helpers
591 */
592typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
593{
594 AMDGPU_DOORBELL_KIQ = 0x000,
595 AMDGPU_DOORBELL_HIQ = 0x001,
596 AMDGPU_DOORBELL_DIQ = 0x002,
597 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
598 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
599 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
600 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
601 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
602 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
603 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
604 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
605 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
606 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
607 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
608 AMDGPU_DOORBELL_IH = 0x1E8,
609 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
610 AMDGPU_DOORBELL_INVALID = 0xFFFF
611} AMDGPU_DOORBELL_ASSIGNMENT;
612
613struct amdgpu_doorbell {
614 /* doorbell mmio */
615 resource_size_t base;
616 resource_size_t size;
617 u32 __iomem *ptr;
618 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
619};
620
621void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
622 phys_addr_t *aperture_base,
623 size_t *aperture_size,
624 size_t *start_offset);
625
626/*
627 * IRQS.
628 */
629
630struct amdgpu_flip_work {
Michel Dänzer325cbba2016-08-04 12:39:37 +0900631 struct delayed_work flip_work;
Alex Deucher97b2e202015-04-20 16:51:00 -0400632 struct work_struct unpin_work;
633 struct amdgpu_device *adev;
634 int crtc_id;
Michel Dänzer325cbba2016-08-04 12:39:37 +0900635 u32 target_vblank;
Alex Deucher97b2e202015-04-20 16:51:00 -0400636 uint64_t base;
637 struct drm_pending_vblank_event *event;
Christian König765e7fb2016-09-15 15:06:50 +0200638 struct amdgpu_bo *old_abo;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100639 struct dma_fence *excl;
Christian König1ffd2652015-08-11 17:29:52 +0200640 unsigned shared_count;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100641 struct dma_fence **shared;
642 struct dma_fence_cb cb;
Alex Deuchercb9e59d2016-05-05 16:03:57 -0400643 bool async;
Alex Deucher97b2e202015-04-20 16:51:00 -0400644};
645
646
647/*
648 * CP & rings.
649 */
650
651struct amdgpu_ib {
652 struct amdgpu_sa_bo *sa_bo;
653 uint32_t length_dw;
654 uint64_t gpu_addr;
655 uint32_t *ptr;
Jammy Zhoude807f82015-05-11 23:41:41 +0800656 uint32_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400657};
658
Nils Wallménius62250a92016-04-10 16:30:00 +0200659extern const struct amd_sched_backend_ops amdgpu_sched_ops;
Chunming Zhouc1b69ed2015-07-21 13:45:14 +0800660
Christian König50838c82016-02-03 13:44:52 +0100661int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
Monk Liuc5637832016-04-19 20:11:32 +0800662 struct amdgpu_job **job, struct amdgpu_vm *vm);
Christian Königd71518b2016-02-01 12:20:25 +0100663int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
664 struct amdgpu_job **job);
Monk Liub6723c82016-03-10 12:14:44 +0800665
Christian Königa5fb4ec2016-06-29 15:10:31 +0200666void amdgpu_job_free_resources(struct amdgpu_job *job);
Christian König50838c82016-02-03 13:44:52 +0100667void amdgpu_job_free(struct amdgpu_job *job);
Christian Königd71518b2016-02-01 12:20:25 +0100668int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
Christian König2bd9ccf2016-02-01 12:53:58 +0100669 struct amd_sched_entity *entity, void *owner,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100670 struct dma_fence **f);
Christian König8b4fb002015-11-15 16:04:16 +0100671
Alex Deucher97b2e202015-04-20 16:51:00 -0400672/*
673 * context related structures
674 */
675
Christian König21c16bf2015-07-07 17:24:49 +0200676struct amdgpu_ctx_ring {
Christian König91404fb2015-08-05 18:33:21 +0200677 uint64_t sequence;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100678 struct dma_fence **fences;
Christian König91404fb2015-08-05 18:33:21 +0200679 struct amd_sched_entity entity;
Christian König21c16bf2015-07-07 17:24:49 +0200680};
681
Alex Deucher97b2e202015-04-20 16:51:00 -0400682struct amdgpu_ctx {
Alex Deucher0b492a42015-08-16 22:48:26 -0400683 struct kref refcount;
Chunming Zhou9cb7e5a2015-07-21 13:17:19 +0800684 struct amdgpu_device *adev;
Alex Deucher0b492a42015-08-16 22:48:26 -0400685 unsigned reset_counter;
Christian König21c16bf2015-07-07 17:24:49 +0200686 spinlock_t ring_lock;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100687 struct dma_fence **fences;
Christian König21c16bf2015-07-07 17:24:49 +0200688 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
Monk Liu753ad492016-08-26 13:28:28 +0800689 bool preamble_presented;
Alex Deucher97b2e202015-04-20 16:51:00 -0400690};
691
692struct amdgpu_ctx_mgr {
Alex Deucher0b492a42015-08-16 22:48:26 -0400693 struct amdgpu_device *adev;
694 struct mutex lock;
695 /* protected by lock */
696 struct idr ctx_handles;
Alex Deucher97b2e202015-04-20 16:51:00 -0400697};
698
Alex Deucher0b492a42015-08-16 22:48:26 -0400699struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
700int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
701
Christian König21c16bf2015-07-07 17:24:49 +0200702uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100703 struct dma_fence *fence);
704struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
Christian König21c16bf2015-07-07 17:24:49 +0200705 struct amdgpu_ring *ring, uint64_t seq);
706
Alex Deucher0b492a42015-08-16 22:48:26 -0400707int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
708 struct drm_file *filp);
709
Christian Königefd4ccb2015-08-04 16:20:31 +0200710void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
711void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
Alex Deucher0b492a42015-08-16 22:48:26 -0400712
Alex Deucher97b2e202015-04-20 16:51:00 -0400713/*
714 * file private structure
715 */
716
717struct amdgpu_fpriv {
718 struct amdgpu_vm vm;
Junwei Zhangb85891b2017-01-16 13:59:01 +0800719 struct amdgpu_bo_va *prt_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400720 struct mutex bo_list_lock;
721 struct idr bo_list_handles;
Alex Deucher0b492a42015-08-16 22:48:26 -0400722 struct amdgpu_ctx_mgr ctx_mgr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400723};
724
725/*
726 * residency list
727 */
728
729struct amdgpu_bo_list {
730 struct mutex lock;
731 struct amdgpu_bo *gds_obj;
732 struct amdgpu_bo *gws_obj;
733 struct amdgpu_bo *oa_obj;
Christian König211dff52016-02-22 15:40:59 +0100734 unsigned first_userptr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400735 unsigned num_entries;
736 struct amdgpu_bo_list_entry *array;
737};
738
739struct amdgpu_bo_list *
740amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
Christian König636ce252015-12-18 21:26:47 +0100741void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
742 struct list_head *validated);
Alex Deucher97b2e202015-04-20 16:51:00 -0400743void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
744void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
745
746/*
747 * GFX stuff
748 */
749#include "clearstate_defs.h"
750
Alex Deucher79e54122016-04-08 15:45:13 -0400751struct amdgpu_rlc_funcs {
752 void (*enter_safe_mode)(struct amdgpu_device *adev);
753 void (*exit_safe_mode)(struct amdgpu_device *adev);
754};
755
Alex Deucher97b2e202015-04-20 16:51:00 -0400756struct amdgpu_rlc {
757 /* for power gating */
758 struct amdgpu_bo *save_restore_obj;
759 uint64_t save_restore_gpu_addr;
760 volatile uint32_t *sr_ptr;
761 const u32 *reg_list;
762 u32 reg_list_size;
763 /* for clear state */
764 struct amdgpu_bo *clear_state_obj;
765 uint64_t clear_state_gpu_addr;
766 volatile uint32_t *cs_ptr;
767 const struct cs_section_def *cs_data;
768 u32 clear_state_size;
769 /* for cp tables */
770 struct amdgpu_bo *cp_table_obj;
771 uint64_t cp_table_gpu_addr;
772 volatile uint32_t *cp_table_ptr;
773 u32 cp_table_size;
Alex Deucher79e54122016-04-08 15:45:13 -0400774
775 /* safe mode for updating CG/PG state */
776 bool in_safe_mode;
777 const struct amdgpu_rlc_funcs *funcs;
Eric Huang2b6cd972016-04-14 17:26:07 -0400778
779 /* for firmware data */
780 u32 save_and_restore_offset;
781 u32 clear_state_descriptor_offset;
782 u32 avail_scratch_ram_locations;
783 u32 reg_restore_list_size;
784 u32 reg_list_format_start;
785 u32 reg_list_format_separate_start;
786 u32 starting_offsets_start;
787 u32 reg_list_format_size_bytes;
788 u32 reg_list_size_bytes;
789
790 u32 *register_list_format;
791 u32 *register_restore;
Alex Deucher97b2e202015-04-20 16:51:00 -0400792};
793
794struct amdgpu_mec {
795 struct amdgpu_bo *hpd_eop_obj;
796 u64 hpd_eop_gpu_addr;
797 u32 num_pipe;
798 u32 num_mec;
799 u32 num_queue;
Xiangliang Yu59a82d72017-02-17 16:03:10 +0800800 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400801};
802
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800803struct amdgpu_kiq {
804 u64 eop_gpu_addr;
805 struct amdgpu_bo *eop_obj;
806 struct amdgpu_ring ring;
807 struct amdgpu_irq_src irq;
808};
809
Alex Deucher97b2e202015-04-20 16:51:00 -0400810/*
811 * GPU scratch registers structures, functions & helpers
812 */
813struct amdgpu_scratch {
814 unsigned num_reg;
815 uint32_t reg_base;
Nils Wallménius50261152017-01-16 21:56:48 +0100816 uint32_t free_mask;
Alex Deucher97b2e202015-04-20 16:51:00 -0400817};
818
819/*
820 * GFX configurations
821 */
Alex Deuchere3fa7632016-10-10 10:56:21 -0400822#define AMDGPU_GFX_MAX_SE 4
823#define AMDGPU_GFX_MAX_SH_PER_SE 2
824
825struct amdgpu_rb_config {
826 uint32_t rb_backend_disable;
827 uint32_t user_rb_backend_disable;
828 uint32_t raster_config;
829 uint32_t raster_config_1;
830};
831
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500832struct gb_addr_config {
833 uint16_t pipe_interleave_size;
834 uint8_t num_pipes;
835 uint8_t max_compress_frags;
836 uint8_t num_banks;
837 uint8_t num_se;
838 uint8_t num_rb_per_se;
839};
840
Junwei Zhangea323f82017-02-21 10:32:37 +0800841struct amdgpu_gfx_config {
Alex Deucher97b2e202015-04-20 16:51:00 -0400842 unsigned max_shader_engines;
843 unsigned max_tile_pipes;
844 unsigned max_cu_per_sh;
845 unsigned max_sh_per_se;
846 unsigned max_backends_per_se;
847 unsigned max_texture_channel_caches;
848 unsigned max_gprs;
849 unsigned max_gs_threads;
850 unsigned max_hw_contexts;
851 unsigned sc_prim_fifo_size_frontend;
852 unsigned sc_prim_fifo_size_backend;
853 unsigned sc_hiz_tile_fifo_size;
854 unsigned sc_earlyz_tile_fifo_size;
855
856 unsigned num_tile_pipes;
857 unsigned backend_enable_mask;
858 unsigned mem_max_burst_length_bytes;
859 unsigned mem_row_size_in_kb;
860 unsigned shader_engine_tile_size;
861 unsigned num_gpus;
862 unsigned multi_gpu_tile_size;
863 unsigned mc_arb_ramcfg;
864 unsigned gb_addr_config;
Alex Deucher8f8e00c2016-02-12 00:39:13 -0500865 unsigned num_rbs;
Alex Deucher97b2e202015-04-20 16:51:00 -0400866
867 uint32_t tile_mode_array[32];
868 uint32_t macrotile_mode_array[16];
Alex Deuchere3fa7632016-10-10 10:56:21 -0400869
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500870 struct gb_addr_config gb_addr_config_fields;
Alex Deuchere3fa7632016-10-10 10:56:21 -0400871 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
Junwei Zhangdf6e2c42017-02-17 11:05:49 +0800872
873 /* gfx configure feature */
874 uint32_t double_offchip_lds_buf;
Alex Deucher97b2e202015-04-20 16:51:00 -0400875};
876
Alex Deucher7dae69a2016-05-03 16:25:53 -0400877struct amdgpu_cu_info {
878 uint32_t number; /* total active CU number */
879 uint32_t ao_cu_mask;
880 uint32_t bitmap[4][4];
881};
882
Alex Deucherb95e31f2016-07-07 15:01:42 -0400883struct amdgpu_gfx_funcs {
884 /* get the gpu clock counter */
885 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
Tom St Denis9559ef52016-06-28 10:26:48 -0400886 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
Tom St Denis472259f2016-10-14 09:49:09 -0400887 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
Tom St Denisc5a60ce2016-12-05 11:39:19 -0500888 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
889 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
Alex Deucherb95e31f2016-07-07 15:01:42 -0400890};
891
Alex Deucher97b2e202015-04-20 16:51:00 -0400892struct amdgpu_gfx {
893 struct mutex gpu_clock_mutex;
Junwei Zhangea323f82017-02-21 10:32:37 +0800894 struct amdgpu_gfx_config config;
Alex Deucher97b2e202015-04-20 16:51:00 -0400895 struct amdgpu_rlc rlc;
896 struct amdgpu_mec mec;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800897 struct amdgpu_kiq kiq;
Alex Deucher97b2e202015-04-20 16:51:00 -0400898 struct amdgpu_scratch scratch;
899 const struct firmware *me_fw; /* ME firmware */
900 uint32_t me_fw_version;
901 const struct firmware *pfp_fw; /* PFP firmware */
902 uint32_t pfp_fw_version;
903 const struct firmware *ce_fw; /* CE firmware */
904 uint32_t ce_fw_version;
905 const struct firmware *rlc_fw; /* RLC firmware */
906 uint32_t rlc_fw_version;
907 const struct firmware *mec_fw; /* MEC firmware */
908 uint32_t mec_fw_version;
909 const struct firmware *mec2_fw; /* MEC2 firmware */
910 uint32_t mec2_fw_version;
Ken Wang02558a02015-06-03 19:52:06 +0800911 uint32_t me_feature_version;
912 uint32_t ce_feature_version;
913 uint32_t pfp_feature_version;
Jammy Zhou351643d2015-08-04 10:43:50 +0800914 uint32_t rlc_feature_version;
915 uint32_t mec_feature_version;
916 uint32_t mec2_feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -0400917 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
918 unsigned num_gfx_rings;
919 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
920 unsigned num_compute_rings;
921 struct amdgpu_irq_src eop_irq;
922 struct amdgpu_irq_src priv_reg_irq;
923 struct amdgpu_irq_src priv_inst_irq;
924 /* gfx status */
Alex Deucher7dae69a2016-05-03 16:25:53 -0400925 uint32_t gfx_current_status;
Ken Wanga101a892015-06-03 17:47:54 +0800926 /* ce ram size*/
Alex Deucher7dae69a2016-05-03 16:25:53 -0400927 unsigned ce_ram_size;
928 struct amdgpu_cu_info cu_info;
Alex Deucherb95e31f2016-07-07 15:01:42 -0400929 const struct amdgpu_gfx_funcs *funcs;
Chunming Zhou3d7c6382016-07-15 11:28:30 +0800930
931 /* reset mask */
932 uint32_t grbm_soft_reset;
933 uint32_t srbm_soft_reset;
Monk Liu223049c2017-01-26 15:32:16 +0800934 bool in_reset;
Alex Deucher97b2e202015-04-20 16:51:00 -0400935};
936
Christian Königb07c60c2016-01-31 12:29:04 +0100937int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
Alex Deucher97b2e202015-04-20 16:51:00 -0400938 unsigned size, struct amdgpu_ib *ib);
Christian König4d9c5142016-05-03 18:46:19 +0200939void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100940 struct dma_fence *f);
Christian Königb07c60c2016-01-31 12:29:04 +0100941int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
Junwei Zhang50ddc752017-01-23 16:30:38 +0800942 struct amdgpu_ib *ibs, struct amdgpu_job *job,
943 struct dma_fence **f);
Alex Deucher97b2e202015-04-20 16:51:00 -0400944int amdgpu_ib_pool_init(struct amdgpu_device *adev);
945void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
946int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400947
948/*
949 * CS.
950 */
951struct amdgpu_cs_chunk {
952 uint32_t chunk_id;
953 uint32_t length_dw;
Christian König758ac172016-05-06 22:14:00 +0200954 void *kdata;
Alex Deucher97b2e202015-04-20 16:51:00 -0400955};
956
957struct amdgpu_cs_parser {
958 struct amdgpu_device *adev;
959 struct drm_file *filp;
Christian König3cb485f2015-05-11 15:34:59 +0200960 struct amdgpu_ctx *ctx;
Christian Königc3cca412015-12-15 14:41:33 +0100961
Alex Deucher97b2e202015-04-20 16:51:00 -0400962 /* chunks */
963 unsigned nchunks;
964 struct amdgpu_cs_chunk *chunks;
Alex Deucher97b2e202015-04-20 16:51:00 -0400965
Christian König50838c82016-02-03 13:44:52 +0100966 /* scheduler job object */
967 struct amdgpu_job *job;
Alex Deucher97b2e202015-04-20 16:51:00 -0400968
Christian Königc3cca412015-12-15 14:41:33 +0100969 /* buffer objects */
970 struct ww_acquire_ctx ticket;
971 struct amdgpu_bo_list *bo_list;
972 struct amdgpu_bo_list_entry vm_pd;
973 struct list_head validated;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100974 struct dma_fence *fence;
Christian Königc3cca412015-12-15 14:41:33 +0100975 uint64_t bytes_moved_threshold;
976 uint64_t bytes_moved;
Christian König662bfa62016-09-01 12:13:18 +0200977 struct amdgpu_bo_list_entry *evictable;
Alex Deucher97b2e202015-04-20 16:51:00 -0400978
979 /* user fence */
Christian König91acbeb2015-12-14 16:42:31 +0100980 struct amdgpu_bo_list_entry uf_entry;
Alex Deucher97b2e202015-04-20 16:51:00 -0400981};
982
Monk Liu753ad492016-08-26 13:28:28 +0800983#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
984#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
985#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
Monk Liu7e6bf802017-01-17 10:55:42 +0800986#define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */
Monk Liu753ad492016-08-26 13:28:28 +0800987
Chunming Zhoubb977d32015-08-18 15:16:40 +0800988struct amdgpu_job {
989 struct amd_sched_job base;
990 struct amdgpu_device *adev;
Christian Königedf600d2016-05-03 15:54:54 +0200991 struct amdgpu_vm *vm;
Christian Königb07c60c2016-01-31 12:29:04 +0100992 struct amdgpu_ring *ring;
Christian Könige86f9ce2016-02-08 12:13:05 +0100993 struct amdgpu_sync sync;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800994 struct amdgpu_ib *ibs;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100995 struct dma_fence *fence; /* the hw fence */
Monk Liu753ad492016-08-26 13:28:28 +0800996 uint32_t preamble_status;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800997 uint32_t num_ibs;
Christian Könige2840222015-11-05 19:49:48 +0100998 void *owner;
Monk Liu3aecd242016-08-25 15:40:48 +0800999 uint64_t fence_ctx; /* the fence_context this job uses */
Chunming Zhoufd53be32016-07-01 17:59:01 +08001000 bool vm_needs_flush;
Christian Königd88bf582016-05-06 17:50:03 +02001001 unsigned vm_id;
1002 uint64_t vm_pd_addr;
1003 uint32_t gds_base, gds_size;
1004 uint32_t gws_base, gws_size;
1005 uint32_t oa_base, oa_size;
Christian König758ac172016-05-06 22:14:00 +02001006
1007 /* user fence handling */
Christian Königb5f5acb2016-06-29 13:26:41 +02001008 uint64_t uf_addr;
Christian König758ac172016-05-06 22:14:00 +02001009 uint64_t uf_sequence;
1010
Chunming Zhoubb977d32015-08-18 15:16:40 +08001011};
Junwei Zhanga6db8a32015-09-09 09:21:19 +08001012#define to_amdgpu_job(sched_job) \
1013 container_of((sched_job), struct amdgpu_job, base)
Chunming Zhoubb977d32015-08-18 15:16:40 +08001014
Christian König7270f832016-01-31 11:00:41 +01001015static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1016 uint32_t ib_idx, int idx)
Alex Deucher97b2e202015-04-20 16:51:00 -04001017{
Christian König50838c82016-02-03 13:44:52 +01001018 return p->job->ibs[ib_idx].ptr[idx];
Alex Deucher97b2e202015-04-20 16:51:00 -04001019}
1020
Christian König7270f832016-01-31 11:00:41 +01001021static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1022 uint32_t ib_idx, int idx,
1023 uint32_t value)
1024{
Christian König50838c82016-02-03 13:44:52 +01001025 p->job->ibs[ib_idx].ptr[idx] = value;
Christian König7270f832016-01-31 11:00:41 +01001026}
1027
Alex Deucher97b2e202015-04-20 16:51:00 -04001028/*
1029 * Writeback
1030 */
1031#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1032
1033struct amdgpu_wb {
1034 struct amdgpu_bo *wb_obj;
1035 volatile uint32_t *wb;
1036 uint64_t gpu_addr;
1037 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1038 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1039};
1040
1041int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1042void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
Ken Wang70142852016-03-18 15:08:49 +08001043int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1044void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
Alex Deucher97b2e202015-04-20 16:51:00 -04001045
Alex Deucherd0dd7f02015-11-11 19:45:06 -05001046void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1047
Alex Deucher97b2e202015-04-20 16:51:00 -04001048/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001049 * SDMA
1050 */
Alex Deucherc113ea12015-10-08 16:30:37 -04001051struct amdgpu_sdma_instance {
Alex Deucher97b2e202015-04-20 16:51:00 -04001052 /* SDMA firmware */
1053 const struct firmware *fw;
1054 uint32_t fw_version;
Jammy Zhoucfa21042015-08-04 10:50:47 +08001055 uint32_t feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001056
1057 struct amdgpu_ring ring;
Jammy Zhou18111de2015-08-31 14:06:39 +08001058 bool burst_nop;
Alex Deucher97b2e202015-04-20 16:51:00 -04001059};
1060
Alex Deucherc113ea12015-10-08 16:30:37 -04001061struct amdgpu_sdma {
1062 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
Ken Wang30d15742016-01-19 14:05:23 +08001063#ifdef CONFIG_DRM_AMDGPU_SI
1064 //SI DMA has a difference trap irq number for the second engine
1065 struct amdgpu_irq_src trap_irq_1;
1066#endif
Alex Deucherc113ea12015-10-08 16:30:37 -04001067 struct amdgpu_irq_src trap_irq;
1068 struct amdgpu_irq_src illegal_inst_irq;
Christian Königedf600d2016-05-03 15:54:54 +02001069 int num_instances;
Chunming Zhoue702a682016-07-13 10:28:56 +08001070 uint32_t srbm_soft_reset;
Alex Deucherc113ea12015-10-08 16:30:37 -04001071};
1072
Alex Deucher97b2e202015-04-20 16:51:00 -04001073/*
1074 * Firmware
1075 */
Huang Ruie635ee02016-11-01 15:35:38 +08001076enum amdgpu_firmware_load_type {
1077 AMDGPU_FW_LOAD_DIRECT = 0,
1078 AMDGPU_FW_LOAD_SMU,
1079 AMDGPU_FW_LOAD_PSP,
1080};
1081
Alex Deucher97b2e202015-04-20 16:51:00 -04001082struct amdgpu_firmware {
1083 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
Huang Ruie635ee02016-11-01 15:35:38 +08001084 enum amdgpu_firmware_load_type load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001085 struct amdgpu_bo *fw_buf;
1086 unsigned int fw_size;
1087};
1088
1089/*
1090 * Benchmarking
1091 */
1092void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1093
1094
1095/*
1096 * Testing
1097 */
1098void amdgpu_test_moves(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001099
1100/*
1101 * MMU Notifier
1102 */
1103#if defined(CONFIG_MMU_NOTIFIER)
1104int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1105void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1106#else
Harry Wentland1d1106b2015-07-15 07:10:41 -04001107static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
Alex Deucher97b2e202015-04-20 16:51:00 -04001108{
1109 return -ENODEV;
1110}
Harry Wentland1d1106b2015-07-15 07:10:41 -04001111static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
Alex Deucher97b2e202015-04-20 16:51:00 -04001112#endif
1113
1114/*
1115 * Debugfs
1116 */
1117struct amdgpu_debugfs {
Nils Wallménius06ab6832016-05-02 12:46:15 -04001118 const struct drm_info_list *files;
Alex Deucher97b2e202015-04-20 16:51:00 -04001119 unsigned num_files;
1120};
1121
1122int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
Nils Wallménius06ab6832016-05-02 12:46:15 -04001123 const struct drm_info_list *files,
Alex Deucher97b2e202015-04-20 16:51:00 -04001124 unsigned nfiles);
1125int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1126
1127#if defined(CONFIG_DEBUG_FS)
1128int amdgpu_debugfs_init(struct drm_minor *minor);
Alex Deucher97b2e202015-04-20 16:51:00 -04001129#endif
1130
Huang Rui50ab2532016-06-12 15:51:09 +08001131int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1132
Alex Deucher97b2e202015-04-20 16:51:00 -04001133/*
1134 * amdgpu smumgr functions
1135 */
1136struct amdgpu_smumgr_funcs {
1137 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1138 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1139 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1140};
1141
1142/*
1143 * amdgpu smumgr
1144 */
1145struct amdgpu_smumgr {
1146 struct amdgpu_bo *toc_buf;
1147 struct amdgpu_bo *smu_buf;
1148 /* asic priv smu data */
1149 void *priv;
1150 spinlock_t smu_lock;
1151 /* smumgr functions */
1152 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1153 /* ucode loading complete flag */
1154 uint32_t fw_flags;
1155};
1156
1157/*
1158 * ASIC specific register table accessible by UMD
1159 */
1160struct amdgpu_allowed_register_entry {
1161 uint32_t reg_offset;
1162 bool untouched;
1163 bool grbm_indexed;
1164};
1165
Alex Deucher97b2e202015-04-20 16:51:00 -04001166/*
1167 * ASIC specific functions.
1168 */
1169struct amdgpu_asic_funcs {
1170 bool (*read_disabled_bios)(struct amdgpu_device *adev);
Alex Deucher7946b872015-11-24 10:14:28 -05001171 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1172 u8 *bios, u32 length_bytes);
Alex Deucher97b2e202015-04-20 16:51:00 -04001173 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1174 u32 sh_num, u32 reg_offset, u32 *value);
1175 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1176 int (*reset)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001177 /* get the reference clock */
1178 u32 (*get_xclk)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001179 /* MM block clocks */
1180 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1181 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001182 /* static power management */
1183 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1184 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
Alex Deucherbbf282d2017-03-03 17:26:10 -05001185 /* get config memsize register */
1186 u32 (*get_config_memsize)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001187};
1188
1189/*
1190 * IOCTL.
1191 */
1192int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1193 struct drm_file *filp);
1194int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1195 struct drm_file *filp);
1196
1197int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1198 struct drm_file *filp);
1199int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1200 struct drm_file *filp);
1201int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1202 struct drm_file *filp);
1203int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1204 struct drm_file *filp);
1205int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1206 struct drm_file *filp);
1207int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1208 struct drm_file *filp);
1209int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1210int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Junwei Zhangeef18a82016-11-04 16:16:10 -04001211int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1212 struct drm_file *filp);
Alex Deucher97b2e202015-04-20 16:51:00 -04001213
1214int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1215 struct drm_file *filp);
1216
1217/* VRAM scratch page for HDP bug, default vram page */
1218struct amdgpu_vram_scratch {
1219 struct amdgpu_bo *robj;
1220 volatile uint32_t *ptr;
1221 u64 gpu_addr;
1222};
1223
1224/*
1225 * ACPI
1226 */
1227struct amdgpu_atif_notification_cfg {
1228 bool enabled;
1229 int command_code;
1230};
1231
1232struct amdgpu_atif_notifications {
1233 bool display_switch;
1234 bool expansion_mode_change;
1235 bool thermal_state;
1236 bool forced_power_state;
1237 bool system_power_state;
1238 bool display_conf_change;
1239 bool px_gfx_switch;
1240 bool brightness_change;
1241 bool dgpu_display_event;
1242};
1243
1244struct amdgpu_atif_functions {
1245 bool system_params;
1246 bool sbios_requests;
1247 bool select_active_disp;
1248 bool lid_state;
1249 bool get_tv_standard;
1250 bool set_tv_standard;
1251 bool get_panel_expansion_mode;
1252 bool set_panel_expansion_mode;
1253 bool temperature_change;
1254 bool graphics_device_types;
1255};
1256
1257struct amdgpu_atif {
1258 struct amdgpu_atif_notifications notifications;
1259 struct amdgpu_atif_functions functions;
1260 struct amdgpu_atif_notification_cfg notification_cfg;
1261 struct amdgpu_encoder *encoder_for_bl;
1262};
1263
1264struct amdgpu_atcs_functions {
1265 bool get_ext_state;
1266 bool pcie_perf_req;
1267 bool pcie_dev_rdy;
1268 bool pcie_bus_width;
1269};
1270
1271struct amdgpu_atcs {
1272 struct amdgpu_atcs_functions functions;
1273};
1274
Alex Deucher97b2e202015-04-20 16:51:00 -04001275/*
Chunming Zhoud03846a2015-07-28 14:20:03 -04001276 * CGS
1277 */
Dave Airlie110e6f22016-04-12 13:25:48 +10001278struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1279void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001280
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001281/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001282 * Core structure, functions and helpers.
1283 */
1284typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1285typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1286
1287typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1288typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1289
1290struct amdgpu_device {
1291 struct device *dev;
1292 struct drm_device *ddev;
1293 struct pci_dev *pdev;
Alex Deucher97b2e202015-04-20 16:51:00 -04001294
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001295#ifdef CONFIG_DRM_AMD_ACP
1296 struct amdgpu_acp acp;
1297#endif
1298
Alex Deucher97b2e202015-04-20 16:51:00 -04001299 /* ASIC */
Jammy Zhou2f7d10b2015-07-22 11:29:01 +08001300 enum amd_asic_type asic_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001301 uint32_t family;
1302 uint32_t rev_id;
1303 uint32_t external_rev_id;
1304 unsigned long flags;
1305 int usec_timeout;
1306 const struct amdgpu_asic_funcs *asic_funcs;
1307 bool shutdown;
Alex Deucher97b2e202015-04-20 16:51:00 -04001308 bool need_dma32;
1309 bool accel_working;
Christian Königedf600d2016-05-03 15:54:54 +02001310 struct work_struct reset_work;
Alex Deucher97b2e202015-04-20 16:51:00 -04001311 struct notifier_block acpi_nb;
1312 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1313 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Christian Königedf600d2016-05-03 15:54:54 +02001314 unsigned debugfs_count;
Alex Deucher97b2e202015-04-20 16:51:00 -04001315#if defined(CONFIG_DEBUG_FS)
Tom St Denisadcec282016-04-15 13:08:44 -04001316 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001317#endif
1318 struct amdgpu_atif atif;
1319 struct amdgpu_atcs atcs;
1320 struct mutex srbm_mutex;
1321 /* GRBM index mutex. Protects concurrent access to GRBM index */
1322 struct mutex grbm_idx_mutex;
1323 struct dev_pm_domain vga_pm_domain;
1324 bool have_disp_power_ref;
1325
1326 /* BIOS */
Alex Deucher0cdd5002017-02-13 16:01:58 -05001327 bool is_atom_fw;
Alex Deucher97b2e202015-04-20 16:51:00 -04001328 uint8_t *bios;
Evan Quana9f5db92016-12-07 09:56:46 +08001329 uint32_t bios_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001330 struct amdgpu_bo *stollen_vga_memory;
Alex Deuchera5bde2f2016-09-23 16:23:41 -04001331 uint32_t bios_scratch_reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001332 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1333
1334 /* Register/doorbell mmio */
1335 resource_size_t rmmio_base;
1336 resource_size_t rmmio_size;
1337 void __iomem *rmmio;
1338 /* protects concurrent MM_INDEX/DATA based register access */
1339 spinlock_t mmio_idx_lock;
1340 /* protects concurrent SMC based register access */
1341 spinlock_t smc_idx_lock;
1342 amdgpu_rreg_t smc_rreg;
1343 amdgpu_wreg_t smc_wreg;
1344 /* protects concurrent PCIE register access */
1345 spinlock_t pcie_idx_lock;
1346 amdgpu_rreg_t pcie_rreg;
1347 amdgpu_wreg_t pcie_wreg;
Huang Rui36b9a952016-08-31 13:23:25 +08001348 amdgpu_rreg_t pciep_rreg;
1349 amdgpu_wreg_t pciep_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001350 /* protects concurrent UVD register access */
1351 spinlock_t uvd_ctx_idx_lock;
1352 amdgpu_rreg_t uvd_ctx_rreg;
1353 amdgpu_wreg_t uvd_ctx_wreg;
1354 /* protects concurrent DIDT register access */
1355 spinlock_t didt_idx_lock;
1356 amdgpu_rreg_t didt_rreg;
1357 amdgpu_wreg_t didt_wreg;
Rex Zhuccdbb202016-06-08 12:47:41 +08001358 /* protects concurrent gc_cac register access */
1359 spinlock_t gc_cac_idx_lock;
1360 amdgpu_rreg_t gc_cac_rreg;
1361 amdgpu_wreg_t gc_cac_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001362 /* protects concurrent ENDPOINT (audio) register access */
1363 spinlock_t audio_endpt_idx_lock;
1364 amdgpu_block_rreg_t audio_endpt_rreg;
1365 amdgpu_block_wreg_t audio_endpt_wreg;
1366 void __iomem *rio_mem;
1367 resource_size_t rio_mem_size;
1368 struct amdgpu_doorbell doorbell;
1369
1370 /* clock/pll info */
1371 struct amdgpu_clock clock;
1372
1373 /* MC */
1374 struct amdgpu_mc mc;
1375 struct amdgpu_gart gart;
1376 struct amdgpu_dummy_page dummy_page;
1377 struct amdgpu_vm_manager vm_manager;
1378
1379 /* memory management */
1380 struct amdgpu_mman mman;
Alex Deucher97b2e202015-04-20 16:51:00 -04001381 struct amdgpu_vram_scratch vram_scratch;
1382 struct amdgpu_wb wb;
1383 atomic64_t vram_usage;
1384 atomic64_t vram_vis_usage;
1385 atomic64_t gtt_usage;
1386 atomic64_t num_bytes_moved;
Christian Königdbd5ed62016-06-21 16:28:14 +02001387 atomic64_t num_evictions;
Marek Olšákd94aed52015-05-05 21:13:49 +02001388 atomic_t gpu_reset_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -04001389
Marek Olšák95844d22016-08-17 23:49:27 +02001390 /* data for buffer migration throttling */
1391 struct {
1392 spinlock_t lock;
1393 s64 last_update_us;
1394 s64 accum_us; /* accumulated microseconds */
1395 u32 log2_max_MBps;
1396 } mm_stats;
1397
Alex Deucher97b2e202015-04-20 16:51:00 -04001398 /* display */
Emily Deng9accf2f2016-08-10 16:01:25 +08001399 bool enable_virtual_display;
Alex Deucher97b2e202015-04-20 16:51:00 -04001400 struct amdgpu_mode_info mode_info;
1401 struct work_struct hotplug_work;
1402 struct amdgpu_irq_src crtc_irq;
1403 struct amdgpu_irq_src pageflip_irq;
1404 struct amdgpu_irq_src hpd_irq;
1405
1406 /* rings */
Christian König76bf0db2016-06-01 15:10:02 +02001407 u64 fence_context;
Alex Deucher97b2e202015-04-20 16:51:00 -04001408 unsigned num_rings;
1409 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1410 bool ib_pool_ready;
1411 struct amdgpu_sa_manager ring_tmp_bo;
1412
1413 /* interrupts */
1414 struct amdgpu_irq irq;
1415
Alex Deucher1f7371b2015-12-02 17:46:21 -05001416 /* powerplay */
1417 struct amd_powerplay powerplay;
Jammy Zhoue61710c2015-11-10 18:31:08 -05001418 bool pp_enabled;
Eric Huangf3898ea2015-12-11 16:24:34 -05001419 bool pp_force_state_enabled;
Alex Deucher1f7371b2015-12-02 17:46:21 -05001420
Alex Deucher97b2e202015-04-20 16:51:00 -04001421 /* dpm */
1422 struct amdgpu_pm pm;
1423 u32 cg_flags;
1424 u32 pg_flags;
1425
1426 /* amdgpu smumgr */
1427 struct amdgpu_smumgr smu;
1428
1429 /* gfx */
1430 struct amdgpu_gfx gfx;
1431
1432 /* sdma */
Alex Deucherc113ea12015-10-08 16:30:37 -04001433 struct amdgpu_sdma sdma;
Alex Deucher97b2e202015-04-20 16:51:00 -04001434
1435 /* uvd */
Alex Deucher97b2e202015-04-20 16:51:00 -04001436 struct amdgpu_uvd uvd;
1437
1438 /* vce */
1439 struct amdgpu_vce vce;
1440
1441 /* firmwares */
1442 struct amdgpu_firmware firmware;
1443
1444 /* GDS */
1445 struct amdgpu_gds gds;
1446
Alex Deuchera1255102016-10-13 17:41:13 -04001447 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
Alex Deucher97b2e202015-04-20 16:51:00 -04001448 int num_ip_blocks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001449 struct mutex mn_lock;
1450 DECLARE_HASHTABLE(mn_hash, 7);
1451
1452 /* tracking pinned memory */
1453 u64 vram_pin_size;
Chunming Zhoue131b912016-04-05 10:48:48 +08001454 u64 invisible_pin_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001455 u64 gart_pin_size;
Oded Gabbay130e0372015-06-12 21:35:14 +03001456
1457 /* amdkfd interface */
1458 struct kfd_dev *kfd;
Chunming Zhou23ca0e42015-07-06 13:42:58 +08001459
Xiangliang Yu5a5099c2017-01-09 18:06:57 -05001460 struct amdgpu_virt virt;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +08001461
1462 /* link all shadow bo */
1463 struct list_head shadow_list;
1464 struct mutex shadow_list_lock;
Chunming Zhou5c1354b2016-08-30 16:13:10 +08001465 /* link all gtt */
1466 spinlock_t gtt_list_lock;
1467 struct list_head gtt_list;
1468
Jim Quc836fec2017-02-10 15:59:59 +08001469 /* record hw reset is performed */
1470 bool has_hw_reset;
1471
Alex Deucher97b2e202015-04-20 16:51:00 -04001472};
1473
Christian Königa7d64de2016-09-15 14:58:48 +02001474static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1475{
1476 return container_of(bdev, struct amdgpu_device, mman.bdev);
1477}
1478
Alex Deucher97b2e202015-04-20 16:51:00 -04001479bool amdgpu_device_is_px(struct drm_device *dev);
1480int amdgpu_device_init(struct amdgpu_device *adev,
1481 struct drm_device *ddev,
1482 struct pci_dev *pdev,
1483 uint32_t flags);
1484void amdgpu_device_fini(struct amdgpu_device *adev);
1485int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1486
1487uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
Monk Liu15d72fd2017-01-25 15:07:40 +08001488 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001489void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
Monk Liu15d72fd2017-01-25 15:07:40 +08001490 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001491u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1492void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1493
1494u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1495void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
Ken Wang832be402016-03-18 15:23:08 +08001496u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1497void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
Alex Deucher97b2e202015-04-20 16:51:00 -04001498
1499/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001500 * Registers read & write functions.
1501 */
Monk Liu15d72fd2017-01-25 15:07:40 +08001502
1503#define AMDGPU_REGS_IDX (1<<0)
1504#define AMDGPU_REGS_NO_KIQ (1<<1)
1505
1506#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1507#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1508
1509#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1510#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1511#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1512#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1513#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
Alex Deucher97b2e202015-04-20 16:51:00 -04001514#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1515#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1516#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1517#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
Huang Rui36b9a952016-08-31 13:23:25 +08001518#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1519#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001520#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1521#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1522#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1523#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1524#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1525#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
Rex Zhuccdbb202016-06-08 12:47:41 +08001526#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1527#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001528#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1529#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1530#define WREG32_P(reg, val, mask) \
1531 do { \
1532 uint32_t tmp_ = RREG32(reg); \
1533 tmp_ &= (mask); \
1534 tmp_ |= ((val) & ~(mask)); \
1535 WREG32(reg, tmp_); \
1536 } while (0)
1537#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1538#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1539#define WREG32_PLL_P(reg, val, mask) \
1540 do { \
1541 uint32_t tmp_ = RREG32_PLL(reg); \
1542 tmp_ &= (mask); \
1543 tmp_ |= ((val) & ~(mask)); \
1544 WREG32_PLL(reg, tmp_); \
1545 } while (0)
1546#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1547#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1548#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1549
1550#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1551#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
Ken Wang832be402016-03-18 15:23:08 +08001552#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1553#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001554
1555#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1556#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1557
1558#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1559 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1560 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1561
1562#define REG_GET_FIELD(value, reg, field) \
1563 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1564
Tom St Denis61cb8ce2016-08-09 10:13:21 -04001565#define WREG32_FIELD(reg, field, val) \
1566 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1567
Alex Deucher97b2e202015-04-20 16:51:00 -04001568/*
1569 * BIOS helpers.
1570 */
1571#define RBIOS8(i) (adev->bios[i])
1572#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1573#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1574
1575/*
1576 * RING helpers.
1577 */
1578static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1579{
1580 if (ring->count_dw <= 0)
Jammy Zhou86c2b792015-05-13 22:52:42 +08001581 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
Ken Wang536fbf92016-03-12 09:32:30 +08001582 ring->ring[ring->wptr++ & ring->buf_mask] = v;
Alex Deucher97b2e202015-04-20 16:51:00 -04001583 ring->wptr &= ring->ptr_mask;
1584 ring->count_dw--;
Alex Deucher97b2e202015-04-20 16:51:00 -04001585}
1586
Monk Liu0a8e1472017-01-17 10:52:33 +08001587static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
1588{
1589 unsigned occupied, chunk1, chunk2;
1590 void *dst;
1591
1592 if (ring->count_dw < count_dw) {
1593 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1594 } else {
1595 occupied = ring->wptr & ring->ptr_mask;
1596 dst = (void *)&ring->ring[occupied];
1597 chunk1 = ring->ptr_mask + 1 - occupied;
1598 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
1599 chunk2 = count_dw - chunk1;
1600 chunk1 <<= 2;
1601 chunk2 <<= 2;
1602
1603 if (chunk1)
1604 memcpy(dst, src, chunk1);
1605
1606 if (chunk2) {
1607 src += chunk1;
1608 dst = (void *)ring->ring;
1609 memcpy(dst, src, chunk2);
1610 }
1611
1612 ring->wptr += count_dw;
1613 ring->wptr &= ring->ptr_mask;
1614 ring->count_dw -= count_dw;
1615 }
1616}
1617
Alex Deucherc113ea12015-10-08 16:30:37 -04001618static inline struct amdgpu_sdma_instance *
1619amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001620{
1621 struct amdgpu_device *adev = ring->adev;
1622 int i;
1623
Alex Deucherc113ea12015-10-08 16:30:37 -04001624 for (i = 0; i < adev->sdma.num_instances; i++)
1625 if (&adev->sdma.instance[i].ring == ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001626 break;
1627
1628 if (i < AMDGPU_MAX_SDMA_INSTANCES)
Alex Deucherc113ea12015-10-08 16:30:37 -04001629 return &adev->sdma.instance[i];
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001630 else
1631 return NULL;
1632}
1633
Alex Deucher97b2e202015-04-20 16:51:00 -04001634/*
1635 * ASICs macro.
1636 */
1637#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1638#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001639#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1640#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1641#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001642#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1643#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1644#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001645#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
Alex Deucher7946b872015-11-24 10:14:28 -05001646#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
Alex Deucher97b2e202015-04-20 16:51:00 -04001647#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
Alex Deucherbbf282d2017-03-03 17:26:10 -05001648#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001649#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1650#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1651#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
Christian Königde9ea7b2016-08-12 11:33:30 +02001652#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
Alex Deucher97b2e202015-04-20 16:51:00 -04001653#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
Alex Xie54635452017-02-14 12:22:57 -05001654#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001655#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1656#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
Christian Königbbec97a2016-07-05 21:07:17 +02001657#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
Alex Deucher97b2e202015-04-20 16:51:00 -04001658#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1659#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1660#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
Christian Königd88bf582016-05-06 17:50:03 +02001661#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
Christian Königb8c7b392016-03-01 15:42:52 +01001662#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
Alex Deucher97b2e202015-04-20 16:51:00 -04001663#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
Chunming Zhou890ee232015-06-01 14:35:03 +08001664#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001665#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
Christian Königd2edb072015-05-11 14:10:34 +02001666#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
Chunming Zhou11afbde2016-03-03 11:38:48 +08001667#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
Monk Liuc2167a62016-08-26 14:12:37 +08001668#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
Monk Liu753ad492016-08-26 13:28:28 +08001669#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
Xiangliang Yub6091c12017-01-10 12:53:52 +08001670#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1671#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
Christian König9e5d53092016-01-31 12:20:55 +01001672#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
Monk Liu03ccf482016-01-14 19:07:38 +08001673#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1674#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
Alex Deucher97b2e202015-04-20 16:51:00 -04001675#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1676#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1677#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1678#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1679#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1680#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
Alex Deucher97b2e202015-04-20 16:51:00 -04001681#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1682#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1683#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1684#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1685#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1686#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
Alex Deuchercb9e59d2016-05-05 16:03:57 -04001687#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
Alex Deucher97b2e202015-04-20 16:51:00 -04001688#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1689#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1690#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1691#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1692#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
Chunming Zhouc7ae72c2015-08-25 17:23:45 +08001693#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
Chunming Zhou6e7a3842015-08-27 13:46:09 +08001694#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
Alex Deucherb95e31f2016-07-07 15:01:42 -04001695#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
Tom St Denis9559ef52016-06-28 10:26:48 -04001696#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
Alex Deucher97b2e202015-04-20 16:51:00 -04001697#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1698
1699/* Common functions */
1700int amdgpu_gpu_reset(struct amdgpu_device *adev);
Chunming Zhou3ad81f12016-08-05 17:30:17 +08001701bool amdgpu_need_backup(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001702void amdgpu_pci_config_reset(struct amdgpu_device *adev);
Jim Quc836fec2017-02-10 15:59:59 +08001703bool amdgpu_need_post(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001704void amdgpu_update_display_priority(struct amdgpu_device *adev);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001705
Alex Deucher97b2e202015-04-20 16:51:00 -04001706int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1707int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1708 u32 ip_instance, u32 ring,
1709 struct amdgpu_ring **out_ring);
Samuel Pitoisetfad06122017-02-09 11:33:37 +01001710void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
Christian König765e7fb2016-09-15 15:06:50 +02001711void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
Alex Deucher97b2e202015-04-20 16:51:00 -04001712bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
Christian König2f568db2016-02-23 12:36:59 +01001713int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
Alex Deucher97b2e202015-04-20 16:51:00 -04001714int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1715 uint32_t flags);
1716bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
Christian Königcc325d12016-02-08 11:08:35 +01001717struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
Christian Königd7006962016-02-08 10:57:22 +01001718bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1719 unsigned long end);
Christian König2f568db2016-02-23 12:36:59 +01001720bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1721 int *last_invalidated);
Alex Deucher97b2e202015-04-20 16:51:00 -04001722bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
Chunming Zhou6b777602016-09-21 16:19:19 +08001723uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001724 struct ttm_mem_reg *mem);
1725void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1726void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1727void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
Baoyou Xie9f31a0b02016-09-15 21:43:26 +08001728int amdgpu_ttm_init(struct amdgpu_device *adev);
1729void amdgpu_ttm_fini(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001730void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1731 const u32 *registers,
1732 const u32 array_size);
1733
1734bool amdgpu_device_is_px(struct drm_device *dev);
1735/* atpx handler */
1736#if defined(CONFIG_VGA_SWITCHEROO)
1737void amdgpu_register_atpx_handler(void);
1738void amdgpu_unregister_atpx_handler(void);
Alex Deuchera78fe132016-06-01 13:08:21 -04001739bool amdgpu_has_atpx_dgpu_power_cntl(void);
Alex Deucher2f5af822016-06-02 09:04:01 -04001740bool amdgpu_is_atpx_hybrid(void);
Alex Deucherefc83cf2016-09-14 14:01:41 -04001741bool amdgpu_atpx_dgpu_req_power_for_displays(void);
Alex Deucher97b2e202015-04-20 16:51:00 -04001742#else
1743static inline void amdgpu_register_atpx_handler(void) {}
1744static inline void amdgpu_unregister_atpx_handler(void) {}
Alex Deuchera78fe132016-06-01 13:08:21 -04001745static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
Alex Deucher2f5af822016-06-02 09:04:01 -04001746static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
Alex Deucherefc83cf2016-09-14 14:01:41 -04001747static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
Alex Deucher97b2e202015-04-20 16:51:00 -04001748#endif
1749
1750/*
1751 * KMS
1752 */
1753extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
Nils Wallméniusf498d9e2016-04-10 16:29:59 +02001754extern const int amdgpu_max_kms_ioctl;
Alex Deucher97b2e202015-04-20 16:51:00 -04001755
1756int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -02001757void amdgpu_driver_unload_kms(struct drm_device *dev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001758void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1759int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1760void amdgpu_driver_postclose_kms(struct drm_device *dev,
1761 struct drm_file *file_priv);
Alex Deucherfaefba92016-12-06 10:38:29 -05001762int amdgpu_suspend(struct amdgpu_device *adev);
Alex Deucher810ddc32016-08-23 13:25:49 -04001763int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1764int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
Thierry Reding88e72712015-09-24 18:35:31 +02001765u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1766int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1767void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1768int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
Alex Deucher97b2e202015-04-20 16:51:00 -04001769 int *max_error,
1770 struct timeval *vblank_time,
1771 unsigned flags);
1772long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1773 unsigned long arg);
1774
1775/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001776 * functions used by amdgpu_encoder.c
1777 */
1778struct amdgpu_afmt_acr {
1779 u32 clock;
1780
1781 int n_32khz;
1782 int cts_32khz;
1783
1784 int n_44_1khz;
1785 int cts_44_1khz;
1786
1787 int n_48khz;
1788 int cts_48khz;
1789
1790};
1791
1792struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1793
1794/* amdgpu_acpi.c */
1795#if defined(CONFIG_ACPI)
1796int amdgpu_acpi_init(struct amdgpu_device *adev);
1797void amdgpu_acpi_fini(struct amdgpu_device *adev);
1798bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1799int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1800 u8 perf_req, bool advertise);
1801int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1802#else
1803static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1804static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1805#endif
1806
1807struct amdgpu_bo_va_mapping *
1808amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1809 uint64_t addr, struct amdgpu_bo **bo);
Christian Königc855e252016-09-05 17:00:57 +02001810int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
Alex Deucher97b2e202015-04-20 16:51:00 -04001811
1812#include "amdgpu_object.h"
Alex Deucher97b2e202015-04-20 16:51:00 -04001813#endif