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gerrit-public.fairphone.software / kernel / msm-5.4 / 20c8ccb1975b8d5639789d1025ad6ada38bd6f48 / . / arch / mips / lantiq / xway / prom.c
blob: 9475b2510adbfb680361f74a1a3159446352fc69 [file] [log] [blame]
John Crispin215ed202012-04-30 11:33:08 +0200[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
John Crispin97b92102016-05-05 09:57:56 +0200[diff] [blame]6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
Hauke Mehrtensa5c1aad2015-10-28 23:37:39 +0100[diff] [blame]7 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
John Crispin215ed202012-04-30 11:33:08 +0200[diff] [blame]8 */
9
10#include <linux/export.h>
11#include <linux/clk.h>
12#include <asm/bootinfo.h>
13#include <asm/time.h>
14
15#include <lantiq_soc.h>
16
17#include "../prom.h"
18
19#define SOC_DANUBE "Danube"
20#define SOC_TWINPASS "Twinpass"
21#define SOC_AMAZON_SE "Amazon_SE"
22#define SOC_AR9 "AR9"
Hauke Mehrtensa5c1aad2015-10-28 23:37:39 +0100[diff] [blame]23#define SOC_GR9 "GRX200"
24#define SOC_VR9 "xRX200"
Hauke Mehrtens13648d72015-10-28 23:37:43 +0100[diff] [blame]25#define SOC_VRX220 "xRX220"
Hauke Mehrtensa5c1aad2015-10-28 23:37:39 +0100[diff] [blame]26#define SOC_AR10 "xRX300"
27#define SOC_GRX390 "xRX330"
John Crispin215ed202012-04-30 11:33:08 +0200[diff] [blame]28
29#define COMP_DANUBE "lantiq,danube"
30#define COMP_TWINPASS "lantiq,twinpass"
31#define COMP_AMAZON_SE "lantiq,ase"
32#define COMP_AR9 "lantiq,ar9"
33#define COMP_GR9 "lantiq,gr9"
34#define COMP_VR9 "lantiq,vr9"
Hauke Mehrtensa5c1aad2015-10-28 23:37:39 +0100[diff] [blame]35#define COMP_AR10 "lantiq,ar10"
36#define COMP_GRX390 "lantiq,grx390"
John Crispin215ed202012-04-30 11:33:08 +0200[diff] [blame]37
38#define PART_SHIFT 12
39#define PART_MASK 0x0FFFFFFF
40#define REV_SHIFT 28
41#define REV_MASK 0xF0000000
42
43void __init ltq_soc_detect(struct ltq_soc_info *i)
44{
45 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
46 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
47 sprintf(i->rev_type, "1.%d", i->rev);
48 switch (i->partnum) {
49 case SOC_ID_DANUBE1:
50 case SOC_ID_DANUBE2:
51 i->name = SOC_DANUBE;
52 i->type = SOC_TYPE_DANUBE;
53 i->compatible = COMP_DANUBE;
54 break;
55
56 case SOC_ID_TWINPASS:
57 i->name = SOC_TWINPASS;
58 i->type = SOC_TYPE_DANUBE;
59 i->compatible = COMP_TWINPASS;
60 break;
61
62 case SOC_ID_ARX188:
63 case SOC_ID_ARX168_1:
64 case SOC_ID_ARX168_2:
65 case SOC_ID_ARX182:
66 i->name = SOC_AR9;
67 i->type = SOC_TYPE_AR9;
68 i->compatible = COMP_AR9;
69 break;
70
71 case SOC_ID_GRX188:
72 case SOC_ID_GRX168:
73 i->name = SOC_GR9;
74 i->type = SOC_TYPE_AR9;
75 i->compatible = COMP_GR9;
76 break;
77
78 case SOC_ID_AMAZON_SE_1:
79 case SOC_ID_AMAZON_SE_2:
80#ifdef CONFIG_PCI
81 panic("ase is only supported for non pci kernels");
82#endif
83 i->name = SOC_AMAZON_SE;
84 i->type = SOC_TYPE_AMAZON_SE;
85 i->compatible = COMP_AMAZON_SE;
86 break;
87
88 case SOC_ID_VRX282:
89 case SOC_ID_VRX268:
90 case SOC_ID_VRX288:
91 i->name = SOC_VR9;
92 i->type = SOC_TYPE_VR9;
93 i->compatible = COMP_VR9;
94 break;
95
96 case SOC_ID_GRX268:
97 case SOC_ID_GRX288:
98 i->name = SOC_GR9;
99 i->type = SOC_TYPE_VR9;
100 i->compatible = COMP_GR9;
101 break;
102
103 case SOC_ID_VRX268_2:
104 case SOC_ID_VRX288_2:
105 i->name = SOC_VR9;
106 i->type = SOC_TYPE_VR9_2;
107 i->compatible = COMP_VR9;
108 break;
109
Hauke Mehrtens13648d72015-10-28 23:37:43 +0100[diff] [blame]110 case SOC_ID_VRX220:
111 i->name = SOC_VRX220;
112 i->type = SOC_TYPE_VRX220;
113 i->compatible = COMP_VR9;
114 break;
115
John Crispin215ed202012-04-30 11:33:08 +0200[diff] [blame]116 case SOC_ID_GRX282_2:
117 case SOC_ID_GRX288_2:
118 i->name = SOC_GR9;
119 i->type = SOC_TYPE_VR9_2;
120 i->compatible = COMP_GR9;
121 break;
122
Hauke Mehrtensa5c1aad2015-10-28 23:37:39 +0100[diff] [blame]123 case SOC_ID_ARX362:
124 case SOC_ID_ARX368:
125 case SOC_ID_ARX382:
126 case SOC_ID_ARX388:
127 case SOC_ID_URX388:
128 i->name = SOC_AR10;
129 i->type = SOC_TYPE_AR10;
130 i->compatible = COMP_AR10;
131 break;
132
133 case SOC_ID_GRX383:
134 case SOC_ID_GRX369:
135 case SOC_ID_GRX387:
136 case SOC_ID_GRX389:
137 i->name = SOC_GRX390;
138 i->type = SOC_TYPE_GRX390;
139 i->compatible = COMP_GRX390;
140 break;
141
John Crispin215ed202012-04-30 11:33:08 +0200[diff] [blame]142 default:
143 unreachable();
144 break;
145 }
146}