blob: 6c4aec25c4ba868ca05dbcf5d2848b9761ab4004 [file] [log] [blame]
Scott Wood0b2cca82008-04-29 01:38:13 +10001/*
2 * Enter and leave sleep state on chips with 6xx-style HID0
3 * power management bits, which don't leave sleep state via reset.
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 *
7 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <asm/ppc_asm.h>
15#include <asm/reg.h>
16#include <asm/thread_info.h>
17#include <asm/asm-offsets.h>
18
19_GLOBAL(mpc6xx_enter_standby)
20 mflr r4
21
22 mfspr r5, SPRN_HID0
23 rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
24 oris r5, r5, HID0_SLEEP@h
25 mtspr SPRN_HID0, r5
26 isync
27
28 lis r5, ret_from_standby@h
29 ori r5, r5, ret_from_standby@l
30 mtlr r5
31
Christophe Leroyf7354cc2019-01-31 10:09:04 +000032 lwz r6, TI_LOCAL_FLAGS(r2)
Scott Wood0b2cca82008-04-29 01:38:13 +100033 ori r6, r6, _TLF_SLEEPING
Christophe Leroyf7354cc2019-01-31 10:09:04 +000034 stw r6, TI_LOCAL_FLAGS(r2)
Scott Wood0b2cca82008-04-29 01:38:13 +100035
36 mfmsr r5
37 ori r5, r5, MSR_EE
38 oris r5, r5, MSR_POW@h
39 sync
40 mtmsr r5
41 isync
42
431: b 1b
44
45ret_from_standby:
46 mfspr r5, SPRN_HID0
47 rlwinm r5, r5, 0, ~HID0_SLEEP
48 mtspr SPRN_HID0, r5
49
50 mtlr r4
51 blr