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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
Arto Merilainende2ba662013-03-22 16:34:08 +02002 * Copyright (C) 2012-2013 Avionic Design GmbH
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00003 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
Arto Merilainende2ba662013-03-22 16:34:08 +02005 * Based on the KMS/FB CMA helpers
6 * Copyright (C) 2012 Analog Device Inc.
7 *
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
Thierry Reding986c58d2015-08-11 13:11:49 +020013#include <linux/console.h>
14
Arto Merilainende2ba662013-03-22 16:34:08 +020015#include "drm.h"
16#include "gem.h"
Daniel Stone0bc6af02018-03-30 15:11:26 +010017#include <drm/drm_gem_framebuffer_helper.h>
Daniel Vetterfcd70cd2019-01-17 22:03:34 +010018#include <drm/drm_modeset_helper.h>
Arto Merilainende2ba662013-03-22 16:34:08 +020019
Archit Tanejab110ef32015-10-27 13:40:59 +053020#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020021static inline struct tegra_fbdev *to_tegra_fbdev(struct drm_fb_helper *helper)
22{
23 return container_of(helper, struct tegra_fbdev, base);
24}
Thierry Reding60c2f702013-10-31 13:28:50 +010025#endif
Arto Merilainende2ba662013-03-22 16:34:08 +020026
27struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
28 unsigned int index)
29{
Daniel Stone0bc6af02018-03-30 15:11:26 +010030 return to_tegra_bo(drm_gem_fb_get_obj(framebuffer, index));
Arto Merilainende2ba662013-03-22 16:34:08 +020031}
32
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020033bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
34{
Daniel Stone0bc6af02018-03-30 15:11:26 +010035 struct tegra_bo *bo = tegra_fb_get_plane(framebuffer, 0);
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020036
Daniel Stone0bc6af02018-03-30 15:11:26 +010037 if (bo->flags & TEGRA_BO_BOTTOM_UP)
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020038 return true;
39
40 return false;
41}
42
Thierry Redingc134f012014-06-03 14:48:12 +020043int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
44 struct tegra_bo_tiling *tiling)
Thierry Reding773af772013-10-04 22:34:01 +020045{
Daniel Stone0bc6af02018-03-30 15:11:26 +010046 uint64_t modifier = framebuffer->modifier;
Thierry Reding773af772013-10-04 22:34:01 +020047
Thierry Reding268892c2017-10-12 16:39:20 +020048 switch (modifier) {
Thierry Reding4ae4b5c2018-03-15 16:45:45 +010049 case DRM_FORMAT_MOD_LINEAR:
50 tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
51 tiling->value = 0;
52 break;
53
Thierry Reding268892c2017-10-12 16:39:20 +020054 case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
Alexandre Courbot5e911442016-11-08 16:50:42 +090055 tiling->mode = TEGRA_BO_TILING_MODE_TILED;
56 tiling->value = 0;
57 break;
58
Thierry Reding268892c2017-10-12 16:39:20 +020059 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
Alexandre Courbot5e911442016-11-08 16:50:42 +090060 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
Thierry Reding268892c2017-10-12 16:39:20 +020061 tiling->value = 0;
62 break;
63
64 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
65 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
66 tiling->value = 1;
67 break;
68
69 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
70 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
71 tiling->value = 2;
72 break;
73
74 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
75 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
76 tiling->value = 3;
77 break;
78
79 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
80 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
81 tiling->value = 4;
82 break;
83
84 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
85 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
86 tiling->value = 5;
Alexandre Courbot5e911442016-11-08 16:50:42 +090087 break;
88
89 default:
Thierry Reding4ae4b5c2018-03-15 16:45:45 +010090 return -EINVAL;
Alexandre Courbot5e911442016-11-08 16:50:42 +090091 }
Thierry Reding773af772013-10-04 22:34:01 +020092
Thierry Redingc134f012014-06-03 14:48:12 +020093 return 0;
Thierry Reding773af772013-10-04 22:34:01 +020094}
95
Ville Syrjälä4ecae782015-12-15 12:21:13 +010096static const struct drm_framebuffer_funcs tegra_fb_funcs = {
Daniel Stone5cb8b992018-03-30 15:11:29 +010097 .destroy = drm_gem_fb_destroy,
Daniel Stone0bc6af02018-03-30 15:11:26 +010098 .create_handle = drm_gem_fb_create_handle,
Arto Merilainende2ba662013-03-22 16:34:08 +020099};
100
Daniel Stonedbc33c72018-03-30 15:11:27 +0100101static struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm,
102 const struct drm_mode_fb_cmd2 *mode_cmd,
103 struct tegra_bo **planes,
104 unsigned int num_planes)
Arto Merilainende2ba662013-03-22 16:34:08 +0200105{
Daniel Stonedbc33c72018-03-30 15:11:27 +0100106 struct drm_framebuffer *fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200107 unsigned int i;
108 int err;
109
110 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
111 if (!fb)
112 return ERR_PTR(-ENOMEM);
113
Daniel Stonedbc33c72018-03-30 15:11:27 +0100114 drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd);
Arto Merilainende2ba662013-03-22 16:34:08 +0200115
Daniel Stonedbc33c72018-03-30 15:11:27 +0100116 for (i = 0; i < fb->format->num_planes; i++)
117 fb->obj[i] = &planes[i]->gem;
Arto Merilainende2ba662013-03-22 16:34:08 +0200118
Daniel Stonedbc33c72018-03-30 15:11:27 +0100119 err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs);
Arto Merilainende2ba662013-03-22 16:34:08 +0200120 if (err < 0) {
121 dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
122 err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200123 kfree(fb);
124 return ERR_PTR(err);
125 }
126
127 return fb;
128}
129
Thierry Redingf9914212014-11-26 13:03:57 +0100130struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
131 struct drm_file *file,
Ville Syrjälä1eb83452015-11-11 19:11:29 +0200132 const struct drm_mode_fb_cmd2 *cmd)
Arto Merilainende2ba662013-03-22 16:34:08 +0200133{
134 unsigned int hsub, vsub, i;
135 struct tegra_bo *planes[4];
136 struct drm_gem_object *gem;
Daniel Stonedbc33c72018-03-30 15:11:27 +0100137 struct drm_framebuffer *fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200138 int err;
139
140 hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format);
141 vsub = drm_format_vert_chroma_subsampling(cmd->pixel_format);
142
143 for (i = 0; i < drm_format_num_planes(cmd->pixel_format); i++) {
144 unsigned int width = cmd->width / (i ? hsub : 1);
145 unsigned int height = cmd->height / (i ? vsub : 1);
146 unsigned int size, bpp;
147
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100148 gem = drm_gem_object_lookup(file, cmd->handles[i]);
Arto Merilainende2ba662013-03-22 16:34:08 +0200149 if (!gem) {
150 err = -ENXIO;
151 goto unreference;
152 }
153
154 bpp = drm_format_plane_cpp(cmd->pixel_format, i);
155
156 size = (height - 1) * cmd->pitches[i] +
157 width * bpp + cmd->offsets[i];
158
159 if (gem->size < size) {
160 err = -EINVAL;
161 goto unreference;
162 }
163
164 planes[i] = to_tegra_bo(gem);
165 }
166
167 fb = tegra_fb_alloc(drm, cmd, planes, i);
168 if (IS_ERR(fb)) {
169 err = PTR_ERR(fb);
170 goto unreference;
171 }
172
Daniel Stonedbc33c72018-03-30 15:11:27 +0100173 return fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200174
175unreference:
176 while (i--)
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300177 drm_gem_object_put_unlocked(&planes[i]->gem);
Arto Merilainende2ba662013-03-22 16:34:08 +0200178
179 return ERR_PTR(err);
180}
181
Archit Tanejab110ef32015-10-27 13:40:59 +0530182#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingb8f3f502018-02-07 18:45:56 +0100183static int tegra_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
184{
185 struct drm_fb_helper *helper = info->par;
186 struct tegra_bo *bo;
187 int err;
188
189 bo = tegra_fb_get_plane(helper->fb, 0);
190
191 err = drm_gem_mmap_obj(&bo->gem, bo->gem.size, vma);
192 if (err < 0)
193 return err;
194
195 return __tegra_gem_mmap(&bo->gem, vma);
196}
197
Arto Merilainende2ba662013-03-22 16:34:08 +0200198static struct fb_ops tegra_fb_ops = {
199 .owner = THIS_MODULE,
Stefan Christ902c2552016-11-14 00:03:22 +0100200 DRM_FB_HELPER_DEFAULT_OPS,
Archit Taneja0f7d9052015-07-22 14:58:07 +0530201 .fb_fillrect = drm_fb_helper_sys_fillrect,
202 .fb_copyarea = drm_fb_helper_sys_copyarea,
203 .fb_imageblit = drm_fb_helper_sys_imageblit,
Thierry Redingb8f3f502018-02-07 18:45:56 +0100204 .fb_mmap = tegra_fb_mmap,
Arto Merilainende2ba662013-03-22 16:34:08 +0200205};
206
207static int tegra_fbdev_probe(struct drm_fb_helper *helper,
208 struct drm_fb_helper_surface_size *sizes)
209{
210 struct tegra_fbdev *fbdev = to_tegra_fbdev(helper);
Thierry Redingd1f3e1e2014-07-11 08:29:14 +0200211 struct tegra_drm *tegra = helper->dev->dev_private;
Arto Merilainende2ba662013-03-22 16:34:08 +0200212 struct drm_device *drm = helper->dev;
213 struct drm_mode_fb_cmd2 cmd = { 0 };
214 unsigned int bytes_per_pixel;
215 struct drm_framebuffer *fb;
216 unsigned long offset;
217 struct fb_info *info;
218 struct tegra_bo *bo;
219 size_t size;
220 int err;
221
222 bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);
223
224 cmd.width = sizes->surface_width;
225 cmd.height = sizes->surface_height;
Thierry Redingd1f3e1e2014-07-11 08:29:14 +0200226 cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
227 tegra->pitch_align);
Thierry Reding71835ca2017-11-14 16:09:30 +0100228
Arto Merilainende2ba662013-03-22 16:34:08 +0200229 cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
230 sizes->surface_depth);
231
232 size = cmd.pitches[0] * cmd.height;
233
Thierry Reding773af772013-10-04 22:34:01 +0200234 bo = tegra_bo_create(drm, size, 0);
Arto Merilainende2ba662013-03-22 16:34:08 +0200235 if (IS_ERR(bo))
236 return PTR_ERR(bo);
237
Archit Taneja0f7d9052015-07-22 14:58:07 +0530238 info = drm_fb_helper_alloc_fbi(helper);
239 if (IS_ERR(info)) {
Arto Merilainende2ba662013-03-22 16:34:08 +0200240 dev_err(drm->dev, "failed to allocate framebuffer info\n");
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300241 drm_gem_object_put_unlocked(&bo->gem);
Archit Taneja0f7d9052015-07-22 14:58:07 +0530242 return PTR_ERR(info);
Arto Merilainende2ba662013-03-22 16:34:08 +0200243 }
244
245 fbdev->fb = tegra_fb_alloc(drm, &cmd, &bo, 1);
246 if (IS_ERR(fbdev->fb)) {
Arto Merilainende2ba662013-03-22 16:34:08 +0200247 err = PTR_ERR(fbdev->fb);
Thierry Redingcb10c812014-11-06 14:36:19 +0100248 dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n",
249 err);
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300250 drm_gem_object_put_unlocked(&bo->gem);
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100251 return PTR_ERR(fbdev->fb);
Arto Merilainende2ba662013-03-22 16:34:08 +0200252 }
253
Daniel Stonedbc33c72018-03-30 15:11:27 +0100254 fb = fbdev->fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200255 helper->fb = fb;
256 helper->fbdev = info;
257
Arto Merilainende2ba662013-03-22 16:34:08 +0200258 info->fbops = &tegra_fb_ops;
259
Daniel Vetter4a536932019-03-26 14:20:05 +0100260 drm_fb_helper_fill_info(info, helper, sizes);
Arto Merilainende2ba662013-03-22 16:34:08 +0200261
262 offset = info->var.xoffset * bytes_per_pixel +
263 info->var.yoffset * fb->pitches[0];
264
Thierry Redingdf06b752014-06-26 21:41:53 +0200265 if (bo->pages) {
266 bo->vaddr = vmap(bo->pages, bo->num_pages, VM_MAP,
267 pgprot_writecombine(PAGE_KERNEL));
268 if (!bo->vaddr) {
269 dev_err(drm->dev, "failed to vmap() framebuffer\n");
270 err = -ENOMEM;
271 goto destroy;
272 }
273 }
274
Arto Merilainende2ba662013-03-22 16:34:08 +0200275 drm->mode_config.fb_base = (resource_size_t)bo->paddr;
Thierry Reding9ab34152013-11-08 13:18:14 +0100276 info->screen_base = (void __iomem *)bo->vaddr + offset;
Arto Merilainende2ba662013-03-22 16:34:08 +0200277 info->screen_size = size;
278 info->fix.smem_start = (unsigned long)(bo->paddr + offset);
279 info->fix.smem_len = size;
280
281 return 0;
282
283destroy:
Daniel Vetter3e7d2fdd2016-12-27 11:49:25 +0100284 drm_framebuffer_remove(fb);
Arto Merilainende2ba662013-03-22 16:34:08 +0200285 return err;
286}
287
Thierry Reding3a493872014-06-27 17:19:23 +0200288static const struct drm_fb_helper_funcs tegra_fb_helper_funcs = {
Arto Merilainende2ba662013-03-22 16:34:08 +0200289 .fb_probe = tegra_fbdev_probe,
290};
291
Thierry Redinge2215322014-06-27 17:19:25 +0200292static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm)
Arto Merilainende2ba662013-03-22 16:34:08 +0200293{
Arto Merilainende2ba662013-03-22 16:34:08 +0200294 struct tegra_fbdev *fbdev;
Arto Merilainende2ba662013-03-22 16:34:08 +0200295
296 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
297 if (!fbdev) {
298 dev_err(drm->dev, "failed to allocate DRM fbdev\n");
299 return ERR_PTR(-ENOMEM);
300 }
301
Thierry Reding10a23102014-06-27 17:19:24 +0200302 drm_fb_helper_prepare(drm, &fbdev->base, &tegra_fb_helper_funcs);
Arto Merilainende2ba662013-03-22 16:34:08 +0200303
Thierry Redinge2215322014-06-27 17:19:25 +0200304 return fbdev;
305}
306
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100307static void tegra_fbdev_free(struct tegra_fbdev *fbdev)
308{
309 kfree(fbdev);
310}
311
Thierry Redinge2215322014-06-27 17:19:25 +0200312static int tegra_fbdev_init(struct tegra_fbdev *fbdev,
313 unsigned int preferred_bpp,
314 unsigned int num_crtc,
315 unsigned int max_connectors)
316{
317 struct drm_device *drm = fbdev->base.dev;
318 int err;
319
Gabriel Krisman Bertazie4563f62017-02-02 14:26:40 -0200320 err = drm_fb_helper_init(drm, &fbdev->base, max_connectors);
Arto Merilainende2ba662013-03-22 16:34:08 +0200321 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100322 dev_err(drm->dev, "failed to initialize DRM FB helper: %d\n",
323 err);
Thierry Redinge2215322014-06-27 17:19:25 +0200324 return err;
Arto Merilainende2ba662013-03-22 16:34:08 +0200325 }
326
327 err = drm_fb_helper_single_add_all_connectors(&fbdev->base);
328 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100329 dev_err(drm->dev, "failed to add connectors: %d\n", err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200330 goto fini;
331 }
332
Arto Merilainende2ba662013-03-22 16:34:08 +0200333 err = drm_fb_helper_initial_config(&fbdev->base, preferred_bpp);
334 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100335 dev_err(drm->dev, "failed to set initial configuration: %d\n",
336 err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200337 goto fini;
338 }
339
Thierry Redinge2215322014-06-27 17:19:25 +0200340 return 0;
Arto Merilainende2ba662013-03-22 16:34:08 +0200341
342fini:
343 drm_fb_helper_fini(&fbdev->base);
Thierry Redinge2215322014-06-27 17:19:25 +0200344 return err;
Arto Merilainende2ba662013-03-22 16:34:08 +0200345}
346
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100347static void tegra_fbdev_exit(struct tegra_fbdev *fbdev)
Arto Merilainende2ba662013-03-22 16:34:08 +0200348{
Archit Taneja0f7d9052015-07-22 14:58:07 +0530349 drm_fb_helper_unregister_fbi(&fbdev->base);
Arto Merilainende2ba662013-03-22 16:34:08 +0200350
Daniel Stonec34a9972018-03-30 15:11:28 +0100351 if (fbdev->fb) {
352 struct tegra_bo *bo = tegra_fb_get_plane(fbdev->fb, 0);
353
354 /* Undo the special mapping we made in fbdev probe. */
355 if (bo && bo->pages) {
356 vunmap(bo->vaddr);
Souptick Joarder53f1e062018-08-01 01:37:05 +0530357 bo->vaddr = NULL;
Daniel Stonec34a9972018-03-30 15:11:28 +0100358 }
359
Daniel Stonedbc33c72018-03-30 15:11:27 +0100360 drm_framebuffer_remove(fbdev->fb);
Daniel Stonec34a9972018-03-30 15:11:28 +0100361 }
Arto Merilainende2ba662013-03-22 16:34:08 +0200362
363 drm_fb_helper_fini(&fbdev->base);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100364 tegra_fbdev_free(fbdev);
Arto Merilainende2ba662013-03-22 16:34:08 +0200365}
Thierry Reding60c2f702013-10-31 13:28:50 +0100366#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000367
Thierry Redinge2215322014-06-27 17:19:25 +0200368int tegra_drm_fb_prepare(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000369{
Archit Tanejab110ef32015-10-27 13:40:59 +0530370#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200371 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000372
Thierry Redinge2215322014-06-27 17:19:25 +0200373 tegra->fbdev = tegra_fbdev_create(drm);
Thierry Reding60c2f702013-10-31 13:28:50 +0100374 if (IS_ERR(tegra->fbdev))
375 return PTR_ERR(tegra->fbdev);
376#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000377
378 return 0;
379}
380
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100381void tegra_drm_fb_free(struct drm_device *drm)
382{
Archit Tanejab110ef32015-10-27 13:40:59 +0530383#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100384 struct tegra_drm *tegra = drm->dev_private;
385
386 tegra_fbdev_free(tegra->fbdev);
387#endif
388}
389
Thierry Redinge2215322014-06-27 17:19:25 +0200390int tegra_drm_fb_init(struct drm_device *drm)
391{
Archit Tanejab110ef32015-10-27 13:40:59 +0530392#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redinge2215322014-06-27 17:19:25 +0200393 struct tegra_drm *tegra = drm->dev_private;
394 int err;
395
396 err = tegra_fbdev_init(tegra->fbdev, 32, drm->mode_config.num_crtc,
397 drm->mode_config.num_connector);
398 if (err < 0)
399 return err;
400#endif
401
402 return 0;
403}
404
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000405void tegra_drm_fb_exit(struct drm_device *drm)
406{
Archit Tanejab110ef32015-10-27 13:40:59 +0530407#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200408 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000409
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100410 tegra_fbdev_exit(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100411#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000412}