blob: 479087c0705a78a65acadc6c1bbe82cbe377d1ca [file] [log] [blame]
Thierry Redingc4755fb2017-11-13 11:08:13 +01001/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef TEGRA_HUB_H
10#define TEGRA_HUB_H 1
11
12#include <drm/drmP.h>
13#include <drm/drm_plane.h>
14
15#include "plane.h"
16
17struct tegra_dc;
18
19struct tegra_windowgroup {
20 unsigned int usecount;
21 struct mutex lock;
22
23 unsigned int index;
24 struct device *parent;
25 struct reset_control *rst;
26};
27
28struct tegra_shared_plane {
29 struct tegra_plane base;
30 struct tegra_windowgroup *wgrp;
Thierry Redingc4755fb2017-11-13 11:08:13 +010031};
32
33static inline struct tegra_shared_plane *
34to_tegra_shared_plane(struct drm_plane *plane)
35{
36 return container_of(plane, struct tegra_shared_plane, base.base);
37}
38
39struct tegra_display_hub_soc {
40 unsigned int num_wgrps;
Thierry Reding5725daa2018-09-21 12:27:43 +020041 bool supports_dsc;
Thierry Redingc4755fb2017-11-13 11:08:13 +010042};
43
44struct tegra_display_hub {
Thierry Reding0281c412017-11-28 11:20:40 +010045 struct drm_private_obj base;
Thierry Redingc4755fb2017-11-13 11:08:13 +010046 struct host1x_client client;
47 struct clk *clk_disp;
48 struct clk *clk_dsc;
49 struct clk *clk_hub;
50 struct reset_control *rst;
51
Thierry Reding0cffbde2018-11-29 17:24:34 +010052 unsigned int num_heads;
53 struct clk **clk_heads;
54
Thierry Redingc4755fb2017-11-13 11:08:13 +010055 const struct tegra_display_hub_soc *soc;
56 struct tegra_windowgroup *wgrps;
57};
58
59static inline struct tegra_display_hub *
60to_tegra_display_hub(struct host1x_client *client)
61{
62 return container_of(client, struct tegra_display_hub, client);
63}
64
Thierry Reding0281c412017-11-28 11:20:40 +010065struct tegra_display_hub_state {
66 struct drm_private_state base;
67
68 struct tegra_dc *dc;
69 unsigned long rate;
70 struct clk *clk;
71};
72
73static inline struct tegra_display_hub_state *
74to_tegra_display_hub_state(struct drm_private_state *priv)
75{
76 return container_of(priv, struct tegra_display_hub_state, base);
77}
78
Thierry Redingc4755fb2017-11-13 11:08:13 +010079struct tegra_dc;
80struct tegra_plane;
81
82int tegra_display_hub_prepare(struct tegra_display_hub *hub);
83void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
84
85struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
86 struct tegra_dc *dc,
87 unsigned int wgrp,
88 unsigned int index);
89
Thierry Reding0281c412017-11-28 11:20:40 +010090int tegra_display_hub_atomic_check(struct drm_device *drm,
91 struct drm_atomic_state *state);
Thierry Redingc4755fb2017-11-13 11:08:13 +010092void tegra_display_hub_atomic_commit(struct drm_device *drm,
93 struct drm_atomic_state *state);
94
95#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
96#define LATENCY_EVENT (1 << 3)
97
98#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
99#define CURS_SLOTS(x) (((x) & 0xff) << 8)
100#define WGRP_SLOTS(x) (((x) & 0xff) << 0)
101
102#endif /* TEGRA_HUB_H */